Crate riscv_isa

RISC-V instruction set architecture library.

Supports decoding RV32 and RV64 from the following specs and extensions:

• I, M, A, F, D, Q, C, B
• Zicsr, Zifencei
• Zawrs
• Zfh
• Zba, Zbb, Zbs, Zbkb, Zbc

Example

use std::str::FromStr;
use riscv_isa::{Decoder, Instruction, Target};

let target = Target::from_str("RV32IMACZifencei_Zicsr").unwrap();
let instructions = [
    0x83, 0xa2, 0xad, 0x00, // lw x5, 10(x27)
    0x33, 0x82, 0x78, 0x03, // mul x4, x17, x23
];

let mut decoder = Decoder::from_le_bytes(target, &instructions[..]);

assert_eq!(decoder.next(), Some(Instruction::LW { rd: 5, rs1: 27, offset: 10 }));
assert_eq!(decoder.next(), Some(Instruction::MUL { rd: 4, rs1: 17, rs2: 23 }));
assert_eq!(decoder.next(), None);

Structs

Csr

Control and status register.

Decoder

RISC-V instruction decoder.

Target

RISC-V target configuration.

Enums

Compressed

Compressed RISC-V instruction.

Instruction

RISC-V instruction.

Privilege

Privilege mode, e.g. User or Machine.

Xlen

Supported register widths.

Functions

decode_compressed

Decode a 16-bit compressed instruction.

decode_full

Decode a 32-bit instruction.

decode_le_bytes

Decode one instruction from the start of some little-endian bytes. The decoded instruction and its length in bytes are returned if successful.