riscv_decode/
instruction.rs

1use crate::types::*;
2
3#[derive(Clone, Copy, Debug, Eq, Hash, PartialEq)]
4pub enum Instruction {
5    // LUI
6    Lui(UType),
7
8    // AUIPC
9    Auipc(UType),
10
11    // Jal
12    Jal(JType),
13
14    // Jalr
15    Jalr(IType),
16
17    // Branch
18    Beq(BType),
19    Bne(BType),
20    Blt(BType),
21    Bge(BType),
22    Bltu(BType),
23    Bgeu(BType),
24
25    // Load
26    Lb(IType),
27    Lh(IType),
28    Lw(IType),
29    Lbu(IType),
30    Lhu(IType),
31    Lwu(IType),
32    Ld(IType),
33
34    // Store
35    Sb(SType),
36    Sh(SType),
37    Sw(SType),
38    Sd(SType),
39
40    // OP-imm
41    Addi(IType),
42    Slti(IType),
43    Sltiu(IType),
44    Xori(IType),
45    Ori(IType),
46    Andi(IType),
47    Slli(ShiftType),
48    Srli(ShiftType),
49    Srai(ShiftType),
50
51    // OP
52    Add(RType),
53    Sub(RType),
54    Sll(RType),
55    Slt(RType),
56    Sltu(RType),
57    Xor(RType),
58    Srl(RType),
59    Sra(RType),
60    Or(RType),
61    And(RType),
62    Mul(RType),
63    Mulh(RType),
64    Mulhsu(RType),
65    Mulhu(RType),
66    Div(RType),
67    Divu(RType),
68    Rem(RType),
69    Remu(RType),
70
71    // Misc-mem
72    Fence(FenceType),
73    FenceI,
74
75    // System
76    Ecall,
77    Ebreak,
78    Uret,
79    Sret,
80    Mret,
81    Wfi,
82    SfenceVma(RType),
83    Csrrw(CsrType),
84    Csrrs(CsrType),
85    Csrrc(CsrType),
86    Csrrwi(CsrIType),
87    Csrrsi(CsrIType),
88    Csrrci(CsrIType),
89
90    // OP-imm 32
91    Addiw(IType),
92    Slliw(ShiftType),
93    Srliw(ShiftType),
94    Sraiw(ShiftType),
95
96    // OP 32
97    Addw(RType),
98    Subw(RType),
99    Sllw(RType),
100    Srlw(RType),
101    Sraw(RType),
102    Mulw(RType),
103    Divw(RType),
104    Divuw(RType),
105    Remw(RType),
106    Remuw(RType),
107
108    // RV32F Extension
109    Flw(IType),
110    Fsw(SType),
111    Fmadds(R4Type),
112    Fmsubs(R4Type),
113    Fnmsubs(R4Type),
114    Fnmadds(R4Type),
115    Fadds(RType),
116    Fsubs(RType),
117    Fmuls(RType),
118    Fdivs(RType),
119    Fsqrts(RType),
120    Fsgnjs(RType),
121    Fsgnjns(RType),
122    Fsgnjxs(RType),
123    Fmins(RType),
124    Fmaxs(RType),
125    Fcvtws(RType),
126    Fcvtwus(RType),
127    Fmvxw(RType),
128    Feqs(RType),
129    Flts(RType),
130    Fles(RType),
131    Fclasss(RType),
132    Fcvtsw(RType),
133    Fcvtswu(RType),
134    Fmvwx(RType),
135
136    // RV32A Standard Extension
137    AmoswapW(RType),
138    AmoaddW(RType),
139    AmoxorW(RType),
140    AmoandW(RType),
141    AmoorW(RType),
142    AmominW(RType),
143    AmomaxW(RType),
144    AmominuW(RType),
145    AmomaxuW(RType),
146
147    LrW(RType),
148    ScW(RType),
149
150    // RV64A Standard Extension
151    AmoswapD(RType),
152    AmoaddD(RType),
153    AmoxorD(RType),
154    AmoandD(RType),
155    AmoorD(RType),
156    AmominD(RType),
157    AmomaxD(RType),
158    AmominuD(RType),
159    AmomaxuD(RType),
160
161    LrD(RType),
162    ScD(RType),
163
164    // Illegal
165    Illegal,
166
167    #[doc(hidden)]
168    __Nonexhaustive,
169}
riscv_decode/instruction.rs

riscv_decode/
instruction.rs
