riscfetch_core/
extensions.rs

1//! RISC-V extension definitions
2//!
3//! This module contains the constant definitions for all supported RISC-V extensions.
4//! Based on RISC-V ISA specification (2026-09) and LLVM mainline support.
5
6/// Standard extension definitions
7/// Format: (char, name, description)
8pub const STANDARD_EXTENSIONS: &[(char, &str, &str)] = &[
9    ('i', "I", "Base Integer Instructions"),
10    ('e', "E", "Embedded (16 registers)"),
11    ('m', "M", "Integer Multiply/Divide"),
12    ('a', "A", "Atomic Instructions"),
13    ('f', "F", "Single-Precision Float"),
14    ('d', "D", "Double-Precision Float"),
15    ('q', "Q", "Quad-Precision Float"),
16    ('c', "C", "Compressed (16-bit)"),
17    ('b', "B", "Bit Manipulation"),
18    ('v', "V", "Vector (SIMD)"),
19    ('h', "H", "Hypervisor"),
20];
21
22/// Z-extension definitions (Unprivileged)
23/// Format: (pattern, name, description, category)
24pub const Z_EXTENSIONS: &[(&str, &str, &str, &str)] = &[
25    // Base/CSR
26    ("zicsr", "Zicsr", "CSR Instructions", "base"),
27    ("zifencei", "Zifencei", "Instruction-Fetch Fence", "base"),
28    ("zicntr", "Zicntr", "Base Counters/Timers", "base"),
29    ("zihpm", "Zihpm", "Hardware Perf Counters", "base"),
30    // Hints
31    ("zihintpause", "Zihintpause", "Pause Hint", "hint"),
32    ("zihintntl", "Zihintntl", "Non-Temporal Hints", "hint"),
33    // Cache
34    ("zicbom", "Zicbom", "Cache-Block Management", "cache"),
35    ("zicboz", "Zicboz", "Cache-Block Zero", "cache"),
36    ("zicbop", "Zicbop", "Cache-Block Prefetch", "cache"),
37    // Conditional
38    ("zicond", "Zicond", "Conditional Operations", "cond"),
39    // Bit Manipulation
40    ("zba", "Zba", "Address Generation", "bit"),
41    ("zbb", "Zbb", "Basic Bit Manipulation", "bit"),
42    ("zbc", "Zbc", "Carry-less Multiply", "bit"),
43    ("zbs", "Zbs", "Single-bit Operations", "bit"),
44    // Scalar Cryptography
45    ("zbkb", "Zbkb", "Bit Manip for Crypto", "crypto"),
46    ("zbkc", "Zbkc", "Carry-less for Crypto", "crypto"),
47    ("zbkx", "Zbkx", "Crossbar for Crypto", "crypto"),
48    ("zk", "Zk", "Scalar Crypto (All)", "crypto"),
49    ("zkn", "Zkn", "NIST Algorithm Suite", "crypto"),
50    ("zknd", "Zknd", "AES Decryption", "crypto"),
51    ("zkne", "Zkne", "AES Encryption", "crypto"),
52    ("zknh", "Zknh", "SHA-2 Hash", "crypto"),
53    ("zks", "Zks", "ShangMi Suite", "crypto"),
54    ("zksed", "Zksed", "SM4 Block Cipher", "crypto"),
55    ("zksh", "Zksh", "SM3 Hash", "crypto"),
56    ("zkr", "Zkr", "Entropy Source", "crypto"),
57    ("zkt", "Zkt", "Data-Indep Timing", "crypto"),
58    // Floating Point
59    ("zfh", "Zfh", "Half-Precision Float", "fp"),
60    ("zfhmin", "Zfhmin", "Minimal Half-Precision", "fp"),
61    ("zfa", "Zfa", "Additional FP Instrs", "fp"),
62    ("zfinx", "Zfinx", "Float in Int Regs", "fp"),
63    ("zdinx", "Zdinx", "Double in Int Regs", "fp"),
64    ("zhinx", "Zhinx", "Half in Int Regs", "fp"),
65    ("zhinxmin", "Zhinxmin", "Min Half in Int Regs", "fp"),
66    ("zfbfmin", "Zfbfmin", "Scalar BFloat16", "fp"),
67    // Compressed
68    ("zca", "Zca", "Compressed Base", "comp"),
69    ("zcb", "Zcb", "Compressed Basic Ops", "comp"),
70    ("zcd", "Zcd", "Compressed Double FP", "comp"),
71    ("zce", "Zce", "Compressed for Embedded", "comp"),
72    ("zcf", "Zcf", "Compressed Single FP", "comp"),
73    ("zclsd", "Zclsd", "Compressed LD/SD Pair", "comp"),
74    ("zcmop", "Zcmop", "Compressed May-Be-Ops", "comp"),
75    ("zcmp", "Zcmp", "Compressed Push/Pop", "comp"),
76    ("zcmt", "Zcmt", "Compressed Table Jump", "comp"),
77    // Atomics
78    ("zaamo", "Zaamo", "Atomic AMO Subset", "atomic"),
79    ("zabha", "Zabha", "Atomic Byte/Halfword", "atomic"),
80    ("zacas", "Zacas", "Atomic Compare-and-Swap", "atomic"),
81    ("zalasr", "Zalasr", "Load-Acquire/Store-Release", "atomic"),
82    ("zalrsc", "Zalrsc", "Atomic LR/SC Subset", "atomic"),
83    ("zawrs", "Zawrs", "Wait-on-Reservation-Set", "atomic"),
84    // Memory Model
85    ("za64rs", "Za64rs", "Reservation Set 64B", "mem"),
86    ("za128rs", "Za128rs", "Reservation Set 128B", "mem"),
87    ("zama16b", "Zama16b", "Misaligned Atomics 16B", "mem"),
88    ("zic64b", "Zic64b", "64-byte Cache Block", "mem"),
89    ("ziccamoa", "Ziccamoa", "Main Mem Atomics AMO", "mem"),
90    ("ziccamoc", "Ziccamoc", "Main Mem Atomics CAS", "mem"),
91    ("ziccid", "Ziccid", "Inst/Data Coherence", "mem"),
92    ("ziccif", "Ziccif", "Inst Fetch Coherence", "mem"),
93    ("zicclsm", "Zicclsm", "Load/Store Misaligned", "mem"),
94    ("ziccrse", "Ziccrse", "Reservation Set Size", "mem"),
95    ("ztso", "Ztso", "Total Store Ordering", "mem"),
96    // Multiply
97    ("zmmul", "Zmmul", "Multiply Only (no Div)", "mul"),
98    // Other
99    ("zicfilp", "Zicfilp", "CFI Landing Pads", "other"),
100    ("zicfiss", "Zicfiss", "CFI Shadow Stack", "other"),
101    ("zimop", "Zimop", "May-Be-Operations", "other"),
102    ("zilsd", "Zilsd", "Load/Store Pair", "other"),
103    // Vector
104    ("zve32f", "Zve32f", "Vector 32-bit Float", "vec"),
105    ("zve32x", "Zve32x", "Vector 32-bit Int", "vec"),
106    ("zve64d", "Zve64d", "Vector 64-bit Double", "vec"),
107    ("zve64f", "Zve64f", "Vector 64-bit Float", "vec"),
108    ("zve64x", "Zve64x", "Vector 64-bit Int", "vec"),
109    ("zvfh", "Zvfh", "Vector Half-Precision", "vec"),
110    ("zvfhmin", "Zvfhmin", "Min Vector Half-Prec", "vec"),
111    ("zvfbfmin", "Zvfbfmin", "Vector BFloat16 Conv", "vec"),
112    ("zvfbfwma", "Zvfbfwma", "Vector BF16 Widen MA", "vec"),
113    ("zvl32b", "Zvl32b", "VLEN >= 32 bits", "vec"),
114    ("zvl64b", "Zvl64b", "VLEN >= 64 bits", "vec"),
115    ("zvl128b", "Zvl128b", "VLEN >= 128 bits", "vec"),
116    ("zvl256b", "Zvl256b", "VLEN >= 256 bits", "vec"),
117    ("zvl512b", "Zvl512b", "VLEN >= 512 bits", "vec"),
118    ("zvl1024b", "Zvl1024b", "VLEN >= 1024 bits", "vec"),
119    ("zvl2048b", "Zvl2048b", "VLEN >= 2048 bits", "vec"),
120    ("zvl4096b", "Zvl4096b", "VLEN >= 4096 bits", "vec"),
121    ("zvl8192b", "Zvl8192b", "VLEN >= 8192 bits", "vec"),
122    ("zvl16384b", "Zvl16384b", "VLEN >= 16384 bits", "vec"),
123    ("zvl32768b", "Zvl32768b", "VLEN >= 32768 bits", "vec"),
124    ("zvl65536b", "Zvl65536b", "VLEN >= 65536 bits", "vec"),
125    // Vector Cryptography
126    ("zvbb", "Zvbb", "Vector Bit Manipulation", "vcrypto"),
127    ("zvbc", "Zvbc", "Vector Carry-less Mul", "vcrypto"),
128    ("zvkb", "Zvkb", "Vector Crypto Bit Manip", "vcrypto"),
129    ("zvkg", "Zvkg", "Vector GCM/GMAC", "vcrypto"),
130    ("zvkn", "Zvkn", "Vector NIST (All)", "vcrypto"),
131    ("zvknc", "Zvknc", "Vector NIST+Carryless", "vcrypto"),
132    ("zvkned", "Zvkned", "Vector AES", "vcrypto"),
133    ("zvkng", "Zvkng", "Vector NIST+GCM", "vcrypto"),
134    ("zvknha", "Zvknha", "Vector SHA-2 (256)", "vcrypto"),
135    ("zvknhb", "Zvknhb", "Vector SHA-2 (512)", "vcrypto"),
136    ("zvks", "Zvks", "Vector ShangMi (All)", "vcrypto"),
137    ("zvksc", "Zvksc", "Vector SM+Carryless", "vcrypto"),
138    ("zvksed", "Zvksed", "Vector SM4", "vcrypto"),
139    ("zvksg", "Zvksg", "Vector SM+GCM", "vcrypto"),
140    ("zvksh", "Zvksh", "Vector SM3", "vcrypto"),
141    ("zvkt", "Zvkt", "Vector Data-Indep Time", "vcrypto"),
142];
143
144/// S-extension definitions (Privileged/Supervisor)
145/// Format: (pattern, name, description, category)
146pub const S_EXTENSIONS: &[(&str, &str, &str, &str)] = &[
147    // Virtual Memory (Sv*)
148    ("svinval", "Svinval", "Fine-Grained TLB Inv", "vm"),
149    ("svnapot", "Svnapot", "NAPOT Translation", "vm"),
150    ("svpbmt", "Svpbmt", "Page-Based Mem Types", "vm"),
151    ("svade", "Svade", "A/D Update on Fault", "vm"),
152    ("svadu", "Svadu", "A/D Hardware Update", "vm"),
153    ("svbare", "Svbare", "Bare Translation Mode", "vm"),
154    ("svrsw60t59b", "Svrsw60t59b", "PTE Bits 60-59 for SW", "vm"),
155    ("svvptc", "Svvptc", "VPTC Invalidation", "vm"),
156    // Supervisor (Ss*)
157    ("ssaia", "Ssaia", "Adv Interrupt Arch", "sup"),
158    ("ssccfg", "Ssccfg", "Counter Config", "sup"),
159    ("ssccptr", "Ssccptr", "Common Ptr Convention", "sup"),
160    ("sscofpmf", "Sscofpmf", "Count Overflow/Filter", "sup"),
161    ("sscounterenw", "Sscounterenw", "Counter Enables", "sup"),
162    ("sscsrind", "Sscsrind", "Indirect CSR Access", "sup"),
163    ("ssctr", "Ssctr", "Control Transfer Rec", "sup"),
164    ("ssdbltrp", "Ssdbltrp", "Double Trap", "sup"),
165    ("ssnpm", "Ssnpm", "Pointer Masking", "sup"),
166    ("sspm", "Sspm", "Pointer Masking", "sup"),
167    ("sspmp", "Sspmp", "S-mode Phys Mem Protection", "sup"),
168    ("ssqosid", "Ssqosid", "QoS Identifiers", "sup"),
169    ("ssstateen", "Ssstateen", "State Enable", "sup"),
170    ("ssstrict", "Ssstrict", "No Non-Conforming Ext", "sup"),
171    ("sstc", "Sstc", "Supervisor Timer", "sup"),
172    ("sstvala", "Sstvala", "Trap Value Address", "sup"),
173    ("sstvecd", "Sstvecd", "Trap Vector Mode", "sup"),
174    ("ssu64xl", "Ssu64xl", "U-mode 64-bit", "sup"),
175    // Machine (Sm*)
176    ("smaia", "Smaia", "Adv Interrupt Arch", "mach"),
177    ("smcdeleg", "Smcdeleg", "Counter Delegation", "mach"),
178    ("smcntrpmf", "Smcntrpmf", "Counter PMF", "mach"),
179    ("smcsrind", "Smcsrind", "Indirect CSR Access", "mach"),
180    ("smctr", "Smctr", "Control Transfer Rec", "mach"),
181    ("smdbltrp", "Smdbltrp", "Double Trap", "mach"),
182    ("smepmp", "Smepmp", "Enhanced PMP", "mach"),
183    ("smmpm", "Smmpm", "M-mode Ptr Masking", "mach"),
184    ("smnpm", "Smnpm", "Nesting Ptr Masking", "mach"),
185    ("smrnmi", "Smrnmi", "Resumable NMI", "mach"),
186    ("smstateen", "Smstateen", "State Enable", "mach"),
187    // Hypervisor (Sh*)
188    ("sha", "Sha", "H-mode Ext Subset", "hyp"),
189    ("shcounterenw", "Shcounterenw", "Counter Enables", "hyp"),
190    ("shgatpa", "Shgatpa", "Guest Addr Translation", "hyp"),
191    (
192        "shlcofideleg",
193        "Shlcofideleg",
194        "Lcof Interrupt Deleg",
195        "hyp",
196    ),
197    ("shtvala", "Shtvala", "H-mode Trap Value", "hyp"),
198    ("shvsatpa", "Shvsatpa", "VS-mode Saturation", "hyp"),
199    ("shvstvala", "Shvstvala", "VS-mode Trap Value", "hyp"),
200    ("shvstvecd", "Shvstvecd", "VS-mode Trap Vector", "hyp"),
201    // Debug (Sd*)
202    ("sdext", "Sdext", "External Debug", "debug"),
203    ("sdtrig", "Sdtrig", "Debug Triggers", "debug"),
204    // User (Su*)
205    ("supm", "Supm", "U-mode Ptr Masking", "user"),
206];
207
208/// Category display names for Z-extensions
209pub const Z_CATEGORY_NAMES: &[(&str, &str)] = &[
210    ("base", "Base"),
211    ("hint", "Hints"),
212    ("cache", "Cache"),
213    ("cond", "Conditional"),
214    ("bit", "Bit Manipulation"),
215    ("crypto", "Cryptography"),
216    ("fp", "Floating Point"),
217    ("comp", "Compressed"),
218    ("atomic", "Atomics"),
219    ("mem", "Memory Model"),
220    ("mul", "Multiply"),
221    ("vec", "Vector"),
222    ("vcrypto", "Vector Crypto"),
223    ("other", "Other"),
224];
225
226/// Category display names for S-extensions
227pub const S_CATEGORY_NAMES: &[(&str, &str)] = &[
228    ("vm", "Virtual Memory"),
229    ("sup", "Supervisor"),
230    ("mach", "Machine"),
231    ("hyp", "Hypervisor"),
232    ("debug", "Debug"),
233    ("user", "User"),
234];
235
236#[cfg(test)]
237mod tests {
238    use super::*;
239
240    #[test]
241    fn test_extension_counts() {
242        assert_eq!(Z_EXTENSIONS.len(), 103);
243        assert_eq!(S_EXTENSIONS.len(), 48);
244    }
245
246    #[test]
247    fn test_ratified_2026_09_extensions_lookup() {
248        assert!(Z_EXTENSIONS.iter().any(|&(p, n, d, c)| p == "ziccid"
249            && n == "Ziccid"
250            && d == "Inst/Data Coherence"
251            && c == "mem"));
252        assert!(Z_EXTENSIONS.iter().any(|&(p, n, d, c)| p == "zicfilp"
253            && n == "Zicfilp"
254            && d == "CFI Landing Pads"
255            && c == "other"));
256        assert!(Z_EXTENSIONS.iter().any(|&(p, n, d, c)| p == "zicfiss"
257            && n == "Zicfiss"
258            && d == "CFI Shadow Stack"
259            && c == "other"));
260        assert!(S_EXTENSIONS.iter().any(|&(p, n, d, c)| p == "sspmp"
261            && n == "Sspmp"
262            && d == "S-mode Phys Mem Protection"
263            && c == "sup"));
264    }
265}
riscfetch_core/extensions.rs

riscfetch_core/
extensions.rs
