risc0_circuit_rv32im/zirgen/poly_ext.rs
1// Copyright 2025 RISC Zero, Inc.
2//
3// Licensed under the Apache License, Version 2.0 (the "License");
4// you may not use this file except in compliance with the License.
5// You may obtain a copy of the License at
6//
7// http://www.apache.org/licenses/LICENSE-2.0
8//
9// Unless required by applicable law or agreed to in writing, software
10// distributed under the License is distributed on an "AS IS" BASIS,
11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12// See the License for the specific language governing permissions and
13// limitations under the License.
14
15// This code is automatically generated
16
17use risc0_zkp::{
18 adapter::{MixState, PolyExt, PolyExtStep, PolyExtStepDef},
19 field::baby_bear::{BabyBear, BabyBearElem, BabyBearExtElem},
20};
21
22use super::CircuitImpl;
23
24#[allow(missing_docs)]
25#[rustfmt::skip]
26pub const DEF: PolyExtStepDef = PolyExtStepDef {
27 block: &[PolyExtStep::Const(0), // loc(unknown)
28PolyExtStep::Const(1), // loc(unknown)
29PolyExtStep::Const(7), // loc(unknown)
30PolyExtStep::Const(6), // loc(unknown)
31PolyExtStep::Const(5), // loc(unknown)
32PolyExtStep::Const(4), // loc(unknown)
33PolyExtStep::Const(3), // loc(unknown)
34PolyExtStep::Const(2), // loc(unknown)
35PolyExtStep::Const(12), // loc(unknown)
36PolyExtStep::Const(11), // loc(unknown)
37PolyExtStep::Const(10), // loc(unknown)
38PolyExtStep::Const(9), // loc(unknown)
39PolyExtStep::Const(8), // loc(unknown)
40PolyExtStep::Const(48), // loc(unknown)
41PolyExtStep::Const(16384), // loc(unknown)
42PolyExtStep::Const(49151), // loc(unknown)
43PolyExtStep::Const(65535), // loc(unknown)
44PolyExtStep::Const(2013265920), // loc(unknown)
45PolyExtStep::Const(61440), // loc(unknown)
46PolyExtStep::Const(64), // loc(unknown)
47PolyExtStep::Const(256), // loc(unknown)
48PolyExtStep::Const(1024), // loc(unknown)
49PolyExtStep::Const(4096), // loc(unknown)
50PolyExtStep::Const(16), // loc(unknown)
51PolyExtStep::Const(32), // loc(unknown)
52PolyExtStep::Const(128), // loc(unknown)
53PolyExtStep::Const(512), // loc(unknown)
54PolyExtStep::Const(2048), // loc(unknown)
55PolyExtStep::Const(8192), // loc(unknown)
56PolyExtStep::Const(32768), // loc(unknown)
57PolyExtStep::Const(1073725440), // loc(unknown)
58PolyExtStep::Const(1073725472), // loc(unknown)
59PolyExtStep::Const(51), // loc(unknown)
60PolyExtStep::Const(65536), // loc(unknown)
61PolyExtStep::Const(13), // loc(unknown)
62PolyExtStep::Const(14), // loc(unknown)
63PolyExtStep::Const(15), // loc(unknown)
64PolyExtStep::Const(1006632961), // loc(unknown)
65PolyExtStep::Const(19), // loc(unknown)
66PolyExtStep::Const(99), // loc(unknown)
67PolyExtStep::Const(65520), // loc(unknown)
68PolyExtStep::Const(111), // loc(unknown)
69PolyExtStep::Const(103), // loc(unknown)
70PolyExtStep::Const(55), // loc(unknown)
71PolyExtStep::Const(23), // loc(unknown)
72PolyExtStep::Const(115), // loc(unknown)
73PolyExtStep::Const(131070), // loc(unknown)
74PolyExtStep::Const(131072), // loc(unknown)
75PolyExtStep::Const(16777216), // loc(unknown)
76PolyExtStep::Const(2013235201), // loc(unknown)
77PolyExtStep::Const(65280), // loc(unknown)
78PolyExtStep::Const(35), // loc(unknown)
79PolyExtStep::Const(1073725457), // loc(unknown)
80PolyExtStep::Const(40), // loc(unknown)
81PolyExtStep::Const(1140850688), // loc(unknown)
82PolyExtStep::Const(1073741824), // loc(unknown)
83PolyExtStep::Const(1342177281), // loc(unknown)
84PolyExtStep::Const(22), // loc(unknown)
85PolyExtStep::ConstExt(0,0,0,0), // loc(unknown)
86PolyExtStep::Const(17), // loc(unknown)
87PolyExtStep::Const(18), // loc(unknown)
88PolyExtStep::Const(21), // loc(unknown)
89PolyExtStep::Const(1073725450), // loc(unknown)
90PolyExtStep::Const(1509949441), // loc(unknown)
91PolyExtStep::Const(1073725451), // loc(unknown)
92PolyExtStep::Const(1073725452), // loc(unknown)
93PolyExtStep::Const(1073725453), // loc(unknown)
94PolyExtStep::ConstExt(1,0,0,0), // loc(unknown)
95PolyExtStep::Const(24), // loc(unknown)
96PolyExtStep::Const(30719), // loc(unknown)
97PolyExtStep::Const(30720), // loc(unknown)
98PolyExtStep::Const(1761607681), // loc(unknown)
99PolyExtStep::Const(4194304), // loc(unknown)
100PolyExtStep::Const(25), // loc(unknown)
101PolyExtStep::Const(262278199), // loc(unknown)
102PolyExtStep::Const(127253399), // loc(unknown)
103PolyExtStep::Const(314968988), // loc(unknown)
104PolyExtStep::Const(246143118), // loc(unknown)
105PolyExtStep::Const(157582794), // loc(unknown)
106PolyExtStep::Const(118043943), // loc(unknown)
107PolyExtStep::Const(454905424), // loc(unknown)
108PolyExtStep::Const(815798990), // loc(unknown)
109PolyExtStep::Const(1004040026), // loc(unknown)
110PolyExtStep::Const(1773108264), // loc(unknown)
111PolyExtStep::Const(1066694495), // loc(unknown)
112PolyExtStep::Const(1930780904), // loc(unknown)
113PolyExtStep::Const(1180307149), // loc(unknown)
114PolyExtStep::Const(1464793095), // loc(unknown)
115PolyExtStep::Const(1660766320), // loc(unknown)
116PolyExtStep::Const(1389166148), // loc(unknown)
117PolyExtStep::Const(343354132), // loc(unknown)
118PolyExtStep::Const(1307439985), // loc(unknown)
119PolyExtStep::Const(638242172), // loc(unknown)
120PolyExtStep::Const(525458520), // loc(unknown)
121PolyExtStep::Const(1964135730), // loc(unknown)
122PolyExtStep::Const(1751797115), // loc(unknown)
123PolyExtStep::Const(1421525369), // loc(unknown)
124PolyExtStep::Const(831813382), // loc(unknown)
125PolyExtStep::Const(989176635), // loc(unknown)
126PolyExtStep::Const(241306552), // loc(unknown)
127PolyExtStep::Const(1507936940), // loc(unknown)
128PolyExtStep::Const(1687379185), // loc(unknown)
129PolyExtStep::Const(1150912935), // loc(unknown)
130PolyExtStep::Const(1917549072), // loc(unknown)
131PolyExtStep::Const(1201063290), // loc(unknown)
132PolyExtStep::Const(395622276), // loc(unknown)
133PolyExtStep::Const(1997503974), // loc(unknown)
134PolyExtStep::Const(716894289), // loc(unknown)
135PolyExtStep::Const(897025192), // loc(unknown)
136PolyExtStep::Const(1282239129), // loc(unknown)
137PolyExtStep::Const(1737016378), // loc(unknown)
138PolyExtStep::Const(686842369), // loc(unknown)
139PolyExtStep::Const(622609176), // loc(unknown)
140PolyExtStep::Const(1339793538), // loc(unknown)
141PolyExtStep::Const(1518763784), // loc(unknown)
142PolyExtStep::Const(1989924532), // loc(unknown)
143PolyExtStep::Const(1170029417), // loc(unknown)
144PolyExtStep::Const(1917861751), // loc(unknown)
145PolyExtStep::Const(1333667262), // loc(unknown)
146PolyExtStep::Const(540703332), // loc(unknown)
147PolyExtStep::Const(1845603984), // loc(unknown)
148PolyExtStep::Const(695835963), // loc(unknown)
149PolyExtStep::Const(862495875), // loc(unknown)
150PolyExtStep::Const(447555988), // loc(unknown)
151PolyExtStep::Const(1910423126), // loc(unknown)
152PolyExtStep::Const(1099252725), // loc(unknown)
153PolyExtStep::Const(1584033957), // loc(unknown)
154PolyExtStep::Const(1079030649), // loc(unknown)
155PolyExtStep::Const(1622328571), // loc(unknown)
156PolyExtStep::Const(1908416316), // loc(unknown)
157PolyExtStep::Const(1549062383), // loc(unknown)
158PolyExtStep::Const(623051854), // loc(unknown)
159PolyExtStep::Const(162510541), // loc(unknown)
160PolyExtStep::Const(1608853840), // loc(unknown)
161PolyExtStep::Const(538103555), // loc(unknown)
162PolyExtStep::Const(1424297384), // loc(unknown)
163PolyExtStep::Const(552696906), // loc(unknown)
164PolyExtStep::Const(946500736), // loc(unknown)
165PolyExtStep::Const(1215259350), // loc(unknown)
166PolyExtStep::Const(855276054), // loc(unknown)
167PolyExtStep::Const(1664590951), // loc(unknown)
168PolyExtStep::Const(217046702), // loc(unknown)
169PolyExtStep::Const(142102402), // loc(unknown)
170PolyExtStep::Const(1257820264), // loc(unknown)
171PolyExtStep::Const(27129487), // loc(unknown)
172PolyExtStep::Const(1147522062), // loc(unknown)
173PolyExtStep::Const(1291790245), // loc(unknown)
174PolyExtStep::Const(1781980094), // loc(unknown)
175PolyExtStep::Const(273790406), // loc(unknown)
176PolyExtStep::Const(1239734761), // loc(unknown)
177PolyExtStep::Const(1221257987), // loc(unknown)
178PolyExtStep::Const(51256176), // loc(unknown)
179PolyExtStep::Const(172614232), // loc(unknown)
180PolyExtStep::Const(306391314), // loc(unknown)
181PolyExtStep::Const(1647670797), // loc(unknown)
182PolyExtStep::Const(53007114), // loc(unknown)
183PolyExtStep::Const(1269493554), // loc(unknown)
184PolyExtStep::Const(1338899225), // loc(unknown)
185PolyExtStep::Const(1740472809), // loc(unknown)
186PolyExtStep::Const(1454563174), // loc(unknown)
187PolyExtStep::Const(204228775), // loc(unknown)
188PolyExtStep::Const(588764636), // loc(unknown)
189PolyExtStep::Const(1718628547), // loc(unknown)
190PolyExtStep::Const(427731030), // loc(unknown)
191PolyExtStep::Const(825405577), // loc(unknown)
192PolyExtStep::Const(342857858), // loc(unknown)
193PolyExtStep::Const(1290028279), // loc(unknown)
194PolyExtStep::Const(608401422), // loc(unknown)
195PolyExtStep::Const(1587822577), // loc(unknown)
196PolyExtStep::Const(128479034), // loc(unknown)
197PolyExtStep::Const(1040977421), // loc(unknown)
198PolyExtStep::Const(1792450386), // loc(unknown)
199PolyExtStep::Const(1470845646), // loc(unknown)
200PolyExtStep::Const(1363837384), // loc(unknown)
201PolyExtStep::Const(1878280202), // loc(unknown)
202PolyExtStep::Const(434078361), // loc(unknown)
203PolyExtStep::Const(1946596189), // loc(unknown)
204PolyExtStep::Const(875839332), // loc(unknown)
205PolyExtStep::Const(463976218), // loc(unknown)
206PolyExtStep::Const(976057819), // loc(unknown)
207PolyExtStep::Const(48375137), // loc(unknown)
208PolyExtStep::Const(1549779579), // loc(unknown)
209PolyExtStep::Const(1679178250), // loc(unknown)
210PolyExtStep::Const(530151394), // loc(unknown)
211PolyExtStep::Const(1629316321), // loc(unknown)
212PolyExtStep::Const(1854174607), // loc(unknown)
213PolyExtStep::Const(720724951), // loc(unknown)
214PolyExtStep::Const(14387587), // loc(unknown)
215PolyExtStep::Const(1883820770), // loc(unknown)
216PolyExtStep::Const(205609311), // loc(unknown)
217PolyExtStep::Const(1136469704), // loc(unknown)
218PolyExtStep::Const(1439947916), // loc(unknown)
219PolyExtStep::Const(723038058), // loc(unknown)
220PolyExtStep::Const(53041581), // loc(unknown)
221PolyExtStep::Const(150307788), // loc(unknown)
222PolyExtStep::Const(755691969), // loc(unknown)
223PolyExtStep::Const(1715719711), // loc(unknown)
224PolyExtStep::Const(1545325389), // loc(unknown)
225PolyExtStep::Const(989618631), // loc(unknown)
226PolyExtStep::Const(1401020792), // loc(unknown)
227PolyExtStep::Const(930036496), // loc(unknown)
228PolyExtStep::Const(238616145), // loc(unknown)
229PolyExtStep::Const(1006235079), // loc(unknown)
230PolyExtStep::Const(942439428), // loc(unknown)
231PolyExtStep::Const(1649953458), // loc(unknown)
232PolyExtStep::Const(1647665372), // loc(unknown)
233PolyExtStep::Const(708123747), // loc(unknown)
234PolyExtStep::Const(925018226), // loc(unknown)
235PolyExtStep::Const(78845751), // loc(unknown)
236PolyExtStep::Const(1889603648), // loc(unknown)
237PolyExtStep::Const(993455846), // loc(unknown)
238PolyExtStep::Const(140621810), // loc(unknown)
239PolyExtStep::Const(117294666), // loc(unknown)
240PolyExtStep::Const(790726260), // loc(unknown)
241PolyExtStep::Const(1213686459), // loc(unknown)
242PolyExtStep::Const(390340387), // loc(unknown)
243PolyExtStep::Const(714957516), // loc(unknown)
244PolyExtStep::Const(1209164052), // loc(unknown)
245PolyExtStep::Const(1827572010), // loc(unknown)
246PolyExtStep::Const(1507649755), // loc(unknown)
247PolyExtStep::Const(1042892522), // loc(unknown)
248PolyExtStep::Const(760115692), // loc(unknown)
249PolyExtStep::Const(1841795381), // loc(unknown)
250PolyExtStep::Const(457372011), // loc(unknown)
251PolyExtStep::Const(1748789933), // loc(unknown)
252PolyExtStep::Const(1478577620), // loc(unknown)
253PolyExtStep::Const(76770019), // loc(unknown)
254PolyExtStep::Const(1293938517), // loc(unknown)
255PolyExtStep::Const(1150410028), // loc(unknown)
256PolyExtStep::Const(1065075039), // loc(unknown)
257PolyExtStep::Const(1198261138), // loc(unknown)
258PolyExtStep::Const(59510015), // loc(unknown)
259PolyExtStep::Const(1402624179), // loc(unknown)
260PolyExtStep::Const(158646617), // loc(unknown)
261PolyExtStep::Const(890243564), // loc(unknown)
262PolyExtStep::Const(1463323727), // loc(unknown)
263PolyExtStep::Const(1080533265), // loc(unknown)
264PolyExtStep::Const(192082241), // loc(unknown)
265PolyExtStep::Const(1891637550), // loc(unknown)
266PolyExtStep::Const(1950429111), // loc(unknown)
267PolyExtStep::Const(1663353317), // loc(unknown)
268PolyExtStep::Const(1567618575), // loc(unknown)
269PolyExtStep::Const(1380248020), // loc(unknown)
270PolyExtStep::Const(1608891156), // loc(unknown)
271PolyExtStep::Const(1672219447), // loc(unknown)
272PolyExtStep::Const(1262312258), // loc(unknown)
273PolyExtStep::Const(162506101), // loc(unknown)
274PolyExtStep::Const(809508074), // loc(unknown)
275PolyExtStep::Const(1303271640), // loc(unknown)
276PolyExtStep::Const(1393671120), // loc(unknown)
277PolyExtStep::Const(641665156), // loc(unknown)
278PolyExtStep::Const(1090783436), // loc(unknown)
279PolyExtStep::Const(1111203133), // loc(unknown)
280PolyExtStep::Const(1296144415), // loc(unknown)
281PolyExtStep::Const(202271745), // loc(unknown)
282PolyExtStep::Const(459826664), // loc(unknown)
283PolyExtStep::Const(781141772), // loc(unknown)
284PolyExtStep::Const(1832911930), // loc(unknown)
285PolyExtStep::Const(228520958), // loc(unknown)
286PolyExtStep::Const(813674331), // loc(unknown)
287PolyExtStep::Const(1889898), // loc(unknown)
288PolyExtStep::Const(1124078057), // loc(unknown)
289PolyExtStep::Const(738091882), // loc(unknown)
290PolyExtStep::Const(1003792297), // loc(unknown)
291PolyExtStep::Const(1896271507), // loc(unknown)
292PolyExtStep::Const(1206940496), // loc(unknown)
293PolyExtStep::Const(497520322), // loc(unknown)
294PolyExtStep::Const(1930103076), // loc(unknown)
295PolyExtStep::Const(1052077299), // loc(unknown)
296PolyExtStep::Const(1540960371), // loc(unknown)
297PolyExtStep::Const(924863639), // loc(unknown)
298PolyExtStep::Const(1365519753), // loc(unknown)
299PolyExtStep::Const(1726563304), // loc(unknown)
300PolyExtStep::Const(440300254), // loc(unknown)
301PolyExtStep::Const(1891545577), // loc(unknown)
302PolyExtStep::Const(822033215), // loc(unknown)
303PolyExtStep::Const(1111544260), // loc(unknown)
304PolyExtStep::Const(308575117), // loc(unknown)
305PolyExtStep::Const(1708681573), // loc(unknown)
306PolyExtStep::Const(1240419708), // loc(unknown)
307PolyExtStep::Const(1199068823), // loc(unknown)
308PolyExtStep::Const(1186174623), // loc(unknown)
309PolyExtStep::Const(1551596046), // loc(unknown)
310PolyExtStep::Const(1886977120), // loc(unknown)
311PolyExtStep::Const(1327682690), // loc(unknown)
312PolyExtStep::Const(1210751726), // loc(unknown)
313PolyExtStep::Const(1810596765), // loc(unknown)
314PolyExtStep::Const(1083257840), // loc(unknown)
315PolyExtStep::Const(375892129), // loc(unknown)
316PolyExtStep::Const(111593398), // loc(unknown)
317PolyExtStep::Const(1867716110), // loc(unknown)
318PolyExtStep::Const(658182609), // loc(unknown)
319PolyExtStep::Const(51866717), // loc(unknown)
320PolyExtStep::Const(1928969209), // loc(unknown)
321PolyExtStep::Const(1942928017), // loc(unknown)
322PolyExtStep::Const(1558116381), // loc(unknown)
323PolyExtStep::Const(20525701), // loc(unknown)
324PolyExtStep::Const(1188752902), // loc(unknown)
325PolyExtStep::Const(106789798), // loc(unknown)
326PolyExtStep::Const(1389833583), // loc(unknown)
327PolyExtStep::Const(98371040), // loc(unknown)
328PolyExtStep::Const(1001081699), // loc(unknown)
329PolyExtStep::Const(1792686146), // loc(unknown)
330PolyExtStep::Const(801504236), // loc(unknown)
331PolyExtStep::Const(1997365680), // loc(unknown)
332PolyExtStep::Const(1461037801), // loc(unknown)
333PolyExtStep::Const(65998480), // loc(unknown)
334PolyExtStep::Const(1974912880), // loc(unknown)
335PolyExtStep::Const(606789471), // loc(unknown)
336PolyExtStep::Const(13683276), // loc(unknown)
337PolyExtStep::Const(918610824), // loc(unknown)
338PolyExtStep::Const(1073725454), // loc(unknown)
339PolyExtStep::Const(33), // loc(unknown)
340PolyExtStep::Const(34), // loc(unknown)
341PolyExtStep::Const(47), // loc(unknown)
342PolyExtStep::Const(36), // loc(unknown)
343PolyExtStep::Const(1073725445), // loc(unknown)
344PolyExtStep::Const(1073725447), // loc(unknown)
345PolyExtStep::Const(41), // loc(unknown)
346PolyExtStep::ConstExt(128,0,0,0), // loc(unknown)
347PolyExtStep::ConstExt(16384,0,0,0), // loc(unknown)
348PolyExtStep::ConstExt(256,0,0,0), // loc(unknown)
349PolyExtStep::Const(1140850680), // loc(unknown)
350PolyExtStep::Const(1073725592), // loc(unknown)
351PolyExtStep::Const(1073725593), // loc(unknown)
352PolyExtStep::Const(1073725594), // loc(unknown)
353PolyExtStep::Const(1073725595), // loc(unknown)
354PolyExtStep::Const(1073725596), // loc(unknown)
355PolyExtStep::Const(1073725597), // loc(unknown)
356PolyExtStep::Const(1073725598), // loc(unknown)
357PolyExtStep::Const(1073725599), // loc(unknown)
358PolyExtStep::Const(1073726464), // loc(unknown)
359PolyExtStep::Const(1073725568), // loc(unknown)
360PolyExtStep::Const(12320), // loc(unknown)
361PolyExtStep::Const(1073725584), // loc(unknown)
362PolyExtStep::Const(1073725585), // loc(unknown)
363PolyExtStep::Const(1073725586), // loc(unknown)
364PolyExtStep::Const(1073725587), // loc(unknown)
365PolyExtStep::Const(1073725588), // loc(unknown)
366PolyExtStep::Const(1073725589), // loc(unknown)
367PolyExtStep::Const(1073725590), // loc(unknown)
368PolyExtStep::Const(1073725591), // loc(unknown)
369PolyExtStep::Const(1140850681), // loc(unknown)
370PolyExtStep::Const(1140850682), // loc(unknown)
371PolyExtStep::Const(1140850683), // loc(unknown)
372PolyExtStep::Const(1140850684), // loc(unknown)
373PolyExtStep::Const(1140850685), // loc(unknown)
374PolyExtStep::Const(1140850686), // loc(unknown)
375PolyExtStep::Const(1140850687), // loc(unknown)
376PolyExtStep::Const(1073725504), // loc(unknown)
377PolyExtStep::Const(1073725505), // loc(unknown)
378PolyExtStep::Const(1073725506), // loc(unknown)
379PolyExtStep::Const(1073725507), // loc(unknown)
380PolyExtStep::Const(1073725572), // loc(unknown)
381PolyExtStep::Const(1073725573), // loc(unknown)
382PolyExtStep::Const(1875997790), // loc(unknown)
383PolyExtStep::ConstExt(0,1,0,0), // loc(unknown)
384PolyExtStep::True, // All Constraints
385PolyExtStep::Get(143), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :47:34) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
386PolyExtStep::Sub(1, 357), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :47:34) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
387PolyExtStep::Mul(357, 358), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :47:34) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
388PolyExtStep::AndEqz(0, 359), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :47:34) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
389PolyExtStep::Get(140), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :50:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
390PolyExtStep::Sub(360, 2), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :50:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
391PolyExtStep::AndEqz(0, 361), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :50:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
392PolyExtStep::Get(120), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :51:9) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
393PolyExtStep::Sub(0, 362), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :51:9) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
394PolyExtStep::AndEqz(2, 363), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :51:9) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
395PolyExtStep::AndCond(1, 357, 3), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :49:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
396PolyExtStep::Get(121), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :53:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
397PolyExtStep::Add(364, 1), // loc(callsite( builtin Add at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :53:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
398PolyExtStep::Sub(365, 362), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :53:9) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
399PolyExtStep::AndEqz(0, 366), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :53:9) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
400PolyExtStep::AndCond(4, 358, 5), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :49:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
401PolyExtStep::Get(136), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :56:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
402PolyExtStep::Mul(358, 367), // loc(callsite( builtin Mul at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :56:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
403PolyExtStep::Get(138), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :57:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
404PolyExtStep::Mul(358, 369), // loc(callsite( builtin Mul at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :57:34) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
405PolyExtStep::Mul(358, 360), // loc(callsite( builtin Mul at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :60:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
406PolyExtStep::Get(142), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :62:60) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
407PolyExtStep::Mul(358, 372), // loc(callsite( builtin Mul at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :62:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
408PolyExtStep::Add(373, 357), // loc(callsite( builtin Add at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :62:61) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
409PolyExtStep::Get(144), // loc(callsite( builtin NondetReg at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :66:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
410PolyExtStep::Get(145), // loc(callsite( builtin NondetReg at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :67:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
411PolyExtStep::Get(146), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
412PolyExtStep::Sub(1, 377), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
413PolyExtStep::Mul(377, 378), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
414PolyExtStep::AndEqz(6, 379), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
415PolyExtStep::Get(147), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
416PolyExtStep::Sub(1, 380), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
417PolyExtStep::Mul(380, 381), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
418PolyExtStep::AndEqz(7, 382), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
419PolyExtStep::Get(148), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
420PolyExtStep::Sub(1, 383), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
421PolyExtStep::Mul(383, 384), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
422PolyExtStep::AndEqz(8, 385), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
423PolyExtStep::Get(149), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
424PolyExtStep::Sub(1, 386), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
425PolyExtStep::Mul(386, 387), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
426PolyExtStep::AndEqz(9, 388), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
427PolyExtStep::Get(150), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
428PolyExtStep::Sub(1, 389), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
429PolyExtStep::Mul(389, 390), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
430PolyExtStep::AndEqz(10, 391), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
431PolyExtStep::Get(151), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
432PolyExtStep::Sub(1, 392), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
433PolyExtStep::Mul(392, 393), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
434PolyExtStep::AndEqz(11, 394), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
435PolyExtStep::Get(152), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
436PolyExtStep::Sub(1, 395), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
437PolyExtStep::Mul(395, 396), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
438PolyExtStep::AndEqz(12, 397), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
439PolyExtStep::Get(153), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
440PolyExtStep::Sub(1, 398), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
441PolyExtStep::Mul(398, 399), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
442PolyExtStep::AndEqz(13, 400), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
443PolyExtStep::Add(377, 380), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
444PolyExtStep::Add(401, 383), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
445PolyExtStep::Add(402, 386), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
446PolyExtStep::Add(403, 389), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
447PolyExtStep::Add(404, 392), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
448PolyExtStep::Add(405, 395), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
449PolyExtStep::Add(406, 398), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
450PolyExtStep::Sub(407, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
451PolyExtStep::AndEqz(14, 408), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
452PolyExtStep::Mul(383, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
453PolyExtStep::Mul(386, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
454PolyExtStep::Mul(389, 5), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
455PolyExtStep::Mul(392, 4), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
456PolyExtStep::Mul(395, 3), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
457PolyExtStep::Mul(398, 2), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
458PolyExtStep::Add(380, 409), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
459PolyExtStep::Add(415, 410), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
460PolyExtStep::Add(416, 411), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
461PolyExtStep::Add(417, 412), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
462PolyExtStep::Add(418, 413), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
463PolyExtStep::Add(419, 414), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
464PolyExtStep::Sub(420, 376), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
465PolyExtStep::AndEqz(15, 421), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
466PolyExtStep::Get(122), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
467PolyExtStep::Sub(1, 422), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
468PolyExtStep::Mul(422, 423), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
469PolyExtStep::AndEqz(16, 424), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
470PolyExtStep::Get(123), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
471PolyExtStep::Sub(1, 425), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
472PolyExtStep::Mul(425, 426), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
473PolyExtStep::AndEqz(17, 427), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
474PolyExtStep::Get(124), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
475PolyExtStep::Sub(1, 428), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
476PolyExtStep::Mul(428, 429), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
477PolyExtStep::AndEqz(18, 430), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
478PolyExtStep::Get(125), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
479PolyExtStep::Sub(1, 431), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
480PolyExtStep::Mul(431, 432), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
481PolyExtStep::AndEqz(19, 433), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
482PolyExtStep::Get(126), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
483PolyExtStep::Sub(1, 434), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
484PolyExtStep::Mul(434, 435), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
485PolyExtStep::AndEqz(20, 436), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
486PolyExtStep::Get(127), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
487PolyExtStep::Sub(1, 437), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
488PolyExtStep::Mul(437, 438), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
489PolyExtStep::AndEqz(21, 439), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
490PolyExtStep::Get(128), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
491PolyExtStep::Sub(1, 440), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
492PolyExtStep::Mul(440, 441), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
493PolyExtStep::AndEqz(22, 442), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
494PolyExtStep::Get(129), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
495PolyExtStep::Sub(1, 443), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
496PolyExtStep::Mul(443, 444), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
497PolyExtStep::AndEqz(23, 445), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
498PolyExtStep::Get(130), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
499PolyExtStep::Sub(1, 446), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
500PolyExtStep::Mul(446, 447), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
501PolyExtStep::AndEqz(24, 448), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
502PolyExtStep::Get(131), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
503PolyExtStep::Sub(1, 449), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
504PolyExtStep::Mul(449, 450), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
505PolyExtStep::AndEqz(25, 451), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
506PolyExtStep::Get(132), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
507PolyExtStep::Sub(1, 452), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
508PolyExtStep::Mul(452, 453), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
509PolyExtStep::AndEqz(26, 454), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
510PolyExtStep::Get(133), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
511PolyExtStep::Sub(1, 455), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
512PolyExtStep::Mul(455, 456), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
513PolyExtStep::AndEqz(27, 457), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
514PolyExtStep::Get(134), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
515PolyExtStep::Sub(1, 458), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
516PolyExtStep::Mul(458, 459), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
517PolyExtStep::AndEqz(28, 460), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
518PolyExtStep::Add(422, 425), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
519PolyExtStep::Add(461, 428), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
520PolyExtStep::Add(462, 431), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
521PolyExtStep::Add(463, 434), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
522PolyExtStep::Add(464, 437), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
523PolyExtStep::Add(465, 440), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
524PolyExtStep::Add(466, 443), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
525PolyExtStep::Add(467, 446), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
526PolyExtStep::Add(468, 449), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
527PolyExtStep::Add(469, 452), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
528PolyExtStep::Add(470, 455), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
529PolyExtStep::Add(471, 458), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
530PolyExtStep::Sub(472, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
531PolyExtStep::AndEqz(29, 473), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
532PolyExtStep::Mul(428, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
533PolyExtStep::Mul(431, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
534PolyExtStep::Mul(434, 5), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
535PolyExtStep::Mul(437, 4), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
536PolyExtStep::Mul(440, 3), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
537PolyExtStep::Mul(443, 2), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
538PolyExtStep::Mul(446, 12), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
539PolyExtStep::Mul(449, 11), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
540PolyExtStep::Mul(452, 10), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
541PolyExtStep::Mul(455, 9), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
542PolyExtStep::Mul(458, 8), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
543PolyExtStep::Add(425, 474), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
544PolyExtStep::Add(485, 475), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
545PolyExtStep::Add(486, 476), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
546PolyExtStep::Add(487, 477), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
547PolyExtStep::Add(488, 478), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
548PolyExtStep::Add(489, 479), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
549PolyExtStep::Add(490, 480), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
550PolyExtStep::Add(491, 481), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
551PolyExtStep::Add(492, 482), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
552PolyExtStep::Add(493, 483), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
553PolyExtStep::Add(494, 484), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
554PolyExtStep::Sub(495, 375), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
555PolyExtStep::AndEqz(30, 496), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
556PolyExtStep::Sub(371, 13), // loc(callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :7:21) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
557PolyExtStep::Mul(374, 16), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
558PolyExtStep::Sub(1, 374), // loc(callsite( builtin Sub at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:41) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
559PolyExtStep::Mul(499, 15), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:49) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
560PolyExtStep::Add(498, 500), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:31) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
561PolyExtStep::Sub(501, 370), // loc(callsite( builtin Sub at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:53) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
562PolyExtStep::Mul(370, 14), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :73:12) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
563PolyExtStep::Mul(374, 30), // loc(callsite( builtin Mul at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:22) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
564PolyExtStep::Mul(499, 31), // loc(callsite( builtin Mul at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:63) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
565PolyExtStep::Add(504, 505), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:44) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
566PolyExtStep::Add(368, 5), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( SimpleOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :78:20) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :91:12) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :33:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
567PolyExtStep::Mul(507, 377), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
568PolyExtStep::Mul(507, 380), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
569PolyExtStep::Mul(507, 383), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
570PolyExtStep::Mul(507, 386), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
571PolyExtStep::Mul(507, 389), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
572PolyExtStep::Mul(507, 392), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
573PolyExtStep::Mul(507, 395), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
574PolyExtStep::Mul(507, 398), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
575PolyExtStep::Add(508, 509), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
576PolyExtStep::Add(516, 510), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
577PolyExtStep::Add(517, 511), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
578PolyExtStep::Add(518, 512), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
579PolyExtStep::Add(519, 513), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
580PolyExtStep::Add(520, 514), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
581PolyExtStep::Add(521, 515), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
582PolyExtStep::Mul(370, 377), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
583PolyExtStep::Mul(370, 380), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
584PolyExtStep::Mul(370, 383), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
585PolyExtStep::Mul(370, 386), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
586PolyExtStep::Mul(370, 389), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
587PolyExtStep::Mul(370, 392), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
588PolyExtStep::Mul(370, 395), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
589PolyExtStep::Mul(370, 398), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
590PolyExtStep::Add(523, 524), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
591PolyExtStep::Add(531, 525), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
592PolyExtStep::Add(532, 526), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
593PolyExtStep::Add(533, 527), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
594PolyExtStep::Add(534, 528), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
595PolyExtStep::Add(535, 529), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
596PolyExtStep::Add(536, 530), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
597PolyExtStep::Get(347), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :19:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
598PolyExtStep::Get(359), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :20:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
599PolyExtStep::Mul(362, 7), // loc(callsite( builtin Mul at callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:17) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
600PolyExtStep::Sub(538, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
601PolyExtStep::AndEqz(0, 541), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
602PolyExtStep::Add(540, 1), // loc(callsite( builtin Add at callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:19) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
603PolyExtStep::Sub(539, 542), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
604PolyExtStep::AndEqz(32, 543), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
605PolyExtStep::AndEqz(33, 497), // loc(callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :7:21) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
606PolyExtStep::Get(461), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
607PolyExtStep::Sub(1, 544), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
608PolyExtStep::Mul(544, 545), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
609PolyExtStep::Sub(7, 544), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
610PolyExtStep::Mul(546, 547), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
611PolyExtStep::Sub(6, 544), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
612PolyExtStep::Mul(548, 549), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
613PolyExtStep::AndEqz(34, 550), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
614PolyExtStep::Get(467), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
615PolyExtStep::Get(473), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
616PolyExtStep::Sub(551, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
617PolyExtStep::AndEqz(35, 553), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
618PolyExtStep::Sub(552, 502), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
619PolyExtStep::AndEqz(36, 554), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
620PolyExtStep::Get(479), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :8:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
621PolyExtStep::Get(485), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :11:20) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
622PolyExtStep::Sub(1, 555), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
623PolyExtStep::Mul(555, 557), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
624PolyExtStep::AndEqz(37, 558), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
625PolyExtStep::Mul(370, 556), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
626PolyExtStep::Sub(559, 557), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
627PolyExtStep::AndEqz(38, 560), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
628PolyExtStep::Mul(555, 370), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
629PolyExtStep::AndEqz(39, 561), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
630PolyExtStep::Mul(555, 556), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
631PolyExtStep::AndEqz(40, 562), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
632PolyExtStep::AndEqz(41, 555), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:19) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
633PolyExtStep::Get(491), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
634PolyExtStep::Get(497), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
635PolyExtStep::Sub(563, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
636PolyExtStep::AndEqz(42, 565), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
637PolyExtStep::Mul(564, 5), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:4) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
638PolyExtStep::Add(566, 544), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:12) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
639PolyExtStep::Sub(567, 368), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
640PolyExtStep::AndEqz(43, 568), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
641PolyExtStep::Add(503, 564), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :73:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
642PolyExtStep::AndEqz(44, 544), // loc(callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :29:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
643PolyExtStep::Get(509), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
644PolyExtStep::Get(503), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :26:28) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
645PolyExtStep::Get(515), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
646PolyExtStep::Get(521), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
647PolyExtStep::Get(527), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
648PolyExtStep::Get(533), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
649PolyExtStep::Get(539), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
650PolyExtStep::Get(545), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
651PolyExtStep::Get(551), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
652PolyExtStep::Sub(570, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
653PolyExtStep::AndEqz(45, 579), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
654PolyExtStep::Sub(575, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
655PolyExtStep::AndEqz(46, 580), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
656PolyExtStep::Sub(576, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
657PolyExtStep::AndEqz(47, 581), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
658PolyExtStep::AndEqz(48, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
659PolyExtStep::Sub(571, 569), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
660PolyExtStep::AndEqz(49, 582), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
661PolyExtStep::Sub(573, 577), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
662PolyExtStep::AndEqz(50, 583), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
663PolyExtStep::Sub(574, 578), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
664PolyExtStep::AndEqz(51, 584), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
665PolyExtStep::Sub(576, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
666PolyExtStep::Sub(585, 572), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
667PolyExtStep::Get(556), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :54:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
668PolyExtStep::Get(561), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
669PolyExtStep::Sub(587, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
670PolyExtStep::AndEqz(52, 589), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
671PolyExtStep::Sub(588, 586), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
672PolyExtStep::AndEqz(53, 590), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
673PolyExtStep::Get(365), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
674PolyExtStep::Sub(1, 591), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
675PolyExtStep::Mul(591, 592), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
676PolyExtStep::AndEqz(54, 593), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
677PolyExtStep::Get(371), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
678PolyExtStep::Sub(1, 594), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
679PolyExtStep::Mul(594, 595), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
680PolyExtStep::Sub(7, 594), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
681PolyExtStep::Mul(596, 597), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
682PolyExtStep::Sub(6, 594), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
683PolyExtStep::Mul(598, 599), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
684PolyExtStep::AndEqz(55, 600), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
685PolyExtStep::Get(377), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
686PolyExtStep::Sub(1, 601), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
687PolyExtStep::Mul(601, 602), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
688PolyExtStep::Sub(7, 601), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
689PolyExtStep::Mul(603, 604), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
690PolyExtStep::Sub(6, 601), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
691PolyExtStep::Mul(605, 606), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
692PolyExtStep::AndEqz(56, 607), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
693PolyExtStep::Get(383), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
694PolyExtStep::Sub(1, 608), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
695PolyExtStep::Mul(608, 609), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
696PolyExtStep::Sub(7, 608), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
697PolyExtStep::Mul(610, 611), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
698PolyExtStep::Sub(6, 608), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
699PolyExtStep::Mul(612, 613), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
700PolyExtStep::AndEqz(57, 614), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
701PolyExtStep::Get(389), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
702PolyExtStep::Sub(1, 615), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
703PolyExtStep::Mul(615, 616), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
704PolyExtStep::Sub(7, 615), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
705PolyExtStep::Mul(617, 618), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
706PolyExtStep::Sub(6, 615), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
707PolyExtStep::Mul(619, 620), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
708PolyExtStep::AndEqz(58, 621), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
709PolyExtStep::Get(395), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
710PolyExtStep::Sub(1, 622), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
711PolyExtStep::Mul(622, 623), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
712PolyExtStep::Sub(7, 622), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
713PolyExtStep::Mul(624, 625), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
714PolyExtStep::Sub(6, 622), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
715PolyExtStep::Mul(626, 627), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
716PolyExtStep::AndEqz(59, 628), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
717PolyExtStep::Get(401), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
718PolyExtStep::Sub(1, 629), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
719PolyExtStep::Mul(629, 630), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
720PolyExtStep::AndEqz(60, 631), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
721PolyExtStep::Get(407), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
722PolyExtStep::Sub(1, 632), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
723PolyExtStep::Mul(632, 633), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
724PolyExtStep::Sub(7, 632), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
725PolyExtStep::Mul(634, 635), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
726PolyExtStep::Sub(6, 632), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
727PolyExtStep::Mul(636, 637), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
728PolyExtStep::AndEqz(61, 638), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
729PolyExtStep::Get(413), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
730PolyExtStep::Sub(1, 639), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
731PolyExtStep::Mul(639, 640), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
732PolyExtStep::Sub(7, 639), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
733PolyExtStep::Mul(641, 642), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
734PolyExtStep::Sub(6, 639), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
735PolyExtStep::Mul(643, 644), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
736PolyExtStep::AndEqz(62, 645), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
737PolyExtStep::Get(419), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
738PolyExtStep::Sub(1, 646), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
739PolyExtStep::Mul(646, 647), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
740PolyExtStep::AndEqz(63, 648), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
741PolyExtStep::Get(425), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
742PolyExtStep::Sub(1, 649), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
743PolyExtStep::Mul(649, 650), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
744PolyExtStep::AndEqz(64, 651), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
745PolyExtStep::Get(431), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
746PolyExtStep::Sub(1, 652), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
747PolyExtStep::Mul(652, 653), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
748PolyExtStep::Sub(7, 652), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
749PolyExtStep::Mul(654, 655), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
750PolyExtStep::Sub(6, 652), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
751PolyExtStep::Mul(656, 657), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
752PolyExtStep::AndEqz(65, 658), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
753PolyExtStep::Get(437), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
754PolyExtStep::Sub(1, 659), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
755PolyExtStep::Mul(659, 660), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
756PolyExtStep::Sub(7, 659), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
757PolyExtStep::Mul(661, 662), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
758PolyExtStep::Sub(6, 659), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
759PolyExtStep::Mul(663, 664), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
760PolyExtStep::AndEqz(66, 665), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
761PolyExtStep::Get(443), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
762PolyExtStep::Sub(1, 666), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
763PolyExtStep::Mul(666, 667), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
764PolyExtStep::Sub(7, 666), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
765PolyExtStep::Mul(668, 669), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
766PolyExtStep::Sub(6, 666), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
767PolyExtStep::Mul(670, 671), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
768PolyExtStep::AndEqz(67, 672), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
769PolyExtStep::Get(449), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
770PolyExtStep::Sub(1, 673), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
771PolyExtStep::Mul(673, 674), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
772PolyExtStep::AndEqz(68, 675), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
773PolyExtStep::Get(455), // loc(callsite( builtin NondetReg at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :34:30) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
774PolyExtStep::Mul(591, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
775PolyExtStep::Mul(594, 28), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
776PolyExtStep::Add(677, 678), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
777PolyExtStep::Mul(601, 27), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
778PolyExtStep::Add(679, 680), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
779PolyExtStep::Mul(608, 26), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
780PolyExtStep::Add(681, 682), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
781PolyExtStep::Mul(615, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
782PolyExtStep::Add(683, 684), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
783PolyExtStep::Mul(622, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
784PolyExtStep::Add(685, 686), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
785PolyExtStep::Mul(629, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
786PolyExtStep::Add(687, 688), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
787PolyExtStep::Mul(632, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
788PolyExtStep::Add(689, 690), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
789PolyExtStep::Add(691, 639), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
790PolyExtStep::Sub(578, 692), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
791PolyExtStep::AndEqz(69, 693), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
792PolyExtStep::Mul(646, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
793PolyExtStep::Mul(649, 14), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
794PolyExtStep::Add(694, 695), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
795PolyExtStep::Mul(652, 22), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
796PolyExtStep::Add(696, 697), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
797PolyExtStep::Mul(659, 21), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
798PolyExtStep::Add(698, 699), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
799PolyExtStep::Mul(666, 20), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
800PolyExtStep::Add(700, 701), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
801PolyExtStep::Mul(673, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
802PolyExtStep::Add(702, 703), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
803PolyExtStep::Add(704, 676), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
804PolyExtStep::Sub(577, 705), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
805PolyExtStep::AndEqz(70, 706), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
806PolyExtStep::Mul(632, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
807PolyExtStep::Mul(639, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
808PolyExtStep::Add(707, 708), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
809PolyExtStep::Add(709, 646), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
810PolyExtStep::Mul(615, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
811PolyExtStep::Mul(622, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
812PolyExtStep::Add(711, 712), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
813PolyExtStep::Add(713, 629), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
814PolyExtStep::Mul(659, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:17) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
815PolyExtStep::Mul(666, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:30) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
816PolyExtStep::Add(715, 716), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
817PolyExtStep::Add(717, 673), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:39) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
818PolyExtStep::Mul(594, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
819PolyExtStep::Mul(601, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:38) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
820PolyExtStep::Add(719, 720), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
821PolyExtStep::Add(721, 608), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:47) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
822PolyExtStep::Mul(591, 19), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
823PolyExtStep::Add(723, 722), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
824PolyExtStep::Mul(649, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
825PolyExtStep::Add(725, 652), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
826PolyExtStep::Mul(591, 18), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
827PolyExtStep::Mul(724, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:45) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
828PolyExtStep::Add(727, 728), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:36) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
829PolyExtStep::Add(729, 714), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:53) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
830PolyExtStep::Mul(591, 16), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:63) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
831PolyExtStep::Get(676), // loc(callsite( builtin NondetReg at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :47:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
832PolyExtStep::Sub(1, 732), // loc(callsite( builtin Sub at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :49:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
833PolyExtStep::Mul(732, 733), // loc(callsite( builtin Mul at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :49:4) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
834PolyExtStep::AndEqz(71, 734), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :49:36) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
835PolyExtStep::Sub(710, 714), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :52:18) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
836PolyExtStep::Add(506, 710), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
837PolyExtStep::AndEqz(0, 735), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :52:18) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
838PolyExtStep::Get(681), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
839PolyExtStep::Sub(736, 737), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
840PolyExtStep::AndEqz(73, 738), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
841PolyExtStep::Get(566), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
842PolyExtStep::Get(571), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :26:28) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
843PolyExtStep::Get(576), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
844PolyExtStep::Get(581), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
845PolyExtStep::Get(586), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
846PolyExtStep::Get(591), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
847PolyExtStep::Get(596), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
848PolyExtStep::Get(601), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
849PolyExtStep::Get(606), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
850PolyExtStep::Sub(739, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
851PolyExtStep::AndEqz(74, 748), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
852PolyExtStep::Sub(744, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
853PolyExtStep::AndEqz(75, 749), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
854PolyExtStep::Sub(745, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
855PolyExtStep::AndEqz(76, 750), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
856PolyExtStep::AndEqz(77, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
857PolyExtStep::Sub(740, 737), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
858PolyExtStep::AndEqz(78, 751), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
859PolyExtStep::Sub(742, 746), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
860PolyExtStep::AndEqz(79, 752), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
861PolyExtStep::Sub(743, 747), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
862PolyExtStep::AndEqz(80, 753), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
863PolyExtStep::Sub(745, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
864PolyExtStep::Sub(754, 741), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
865PolyExtStep::Get(656), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :54:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
866PolyExtStep::Get(661), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
867PolyExtStep::Sub(756, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
868PolyExtStep::AndEqz(81, 758), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
869PolyExtStep::Sub(757, 755), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
870PolyExtStep::AndEqz(82, 759), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
871PolyExtStep::Get(611), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
872PolyExtStep::AndEqz(83, 760), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
873PolyExtStep::Get(636), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
874PolyExtStep::AndEqz(84, 761), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
875PolyExtStep::Get(666), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
876PolyExtStep::AndEqz(85, 762), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
877PolyExtStep::AndCond(72, 732, 86), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
878PolyExtStep::Add(506, 714), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
879PolyExtStep::AndEqz(0, 738), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
880PolyExtStep::AndEqz(88, 748), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
881PolyExtStep::AndEqz(89, 749), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
882PolyExtStep::AndEqz(90, 750), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
883PolyExtStep::AndEqz(91, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
884PolyExtStep::AndEqz(92, 751), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
885PolyExtStep::AndEqz(93, 752), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
886PolyExtStep::AndEqz(94, 753), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
887PolyExtStep::AndEqz(95, 758), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
888PolyExtStep::AndEqz(96, 759), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
889PolyExtStep::Get(686), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
890PolyExtStep::Sub(763, 764), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
891PolyExtStep::AndEqz(97, 765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
892PolyExtStep::Get(616), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :26:28) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
893PolyExtStep::Get(621), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
894PolyExtStep::Get(626), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
895PolyExtStep::Get(631), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
896PolyExtStep::Get(641), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
897PolyExtStep::Get(646), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
898PolyExtStep::Get(651), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
899PolyExtStep::Sub(760, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
900PolyExtStep::AndEqz(98, 773), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
901PolyExtStep::Sub(761, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
902PolyExtStep::AndEqz(99, 774), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
903PolyExtStep::Sub(770, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
904PolyExtStep::AndEqz(100, 775), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
905PolyExtStep::AndEqz(101, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
906PolyExtStep::Sub(766, 764), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
907PolyExtStep::AndEqz(102, 776), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
908PolyExtStep::Sub(768, 771), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
909PolyExtStep::AndEqz(103, 777), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
910PolyExtStep::Sub(769, 772), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
911PolyExtStep::AndEqz(104, 778), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
912PolyExtStep::Sub(770, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
913PolyExtStep::Sub(779, 767), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
914PolyExtStep::Get(671), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
915PolyExtStep::Sub(762, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
916PolyExtStep::AndEqz(105, 782), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
917PolyExtStep::Sub(781, 780), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
918PolyExtStep::AndEqz(106, 783), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
919PolyExtStep::AndCond(87, 733, 107), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
920PolyExtStep::Get(601), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
921PolyExtStep::Mul(784, 732), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
922PolyExtStep::Mul(784, 733), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
923PolyExtStep::Add(785, 786), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
924PolyExtStep::Get(606), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
925PolyExtStep::Mul(788, 732), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
926PolyExtStep::Mul(788, 733), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
927PolyExtStep::Add(789, 790), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
928PolyExtStep::Get(646), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
929PolyExtStep::Mul(792, 733), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
930PolyExtStep::Add(785, 793), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
931PolyExtStep::Get(651), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
932PolyExtStep::Mul(795, 733), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
933PolyExtStep::Add(789, 796), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
934PolyExtStep::Get(691), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
935PolyExtStep::Sub(787, 798), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
936PolyExtStep::AndEqz(108, 799), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
937PolyExtStep::Get(696), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :63:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
938PolyExtStep::Sub(791, 800), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :63:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
939PolyExtStep::AndEqz(109, 801), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :63:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
940PolyExtStep::Get(701), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :64:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
941PolyExtStep::Sub(794, 802), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :64:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
942PolyExtStep::AndEqz(110, 803), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :64:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
943PolyExtStep::Get(706), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :65:18) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
944PolyExtStep::Sub(797, 804), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :65:18) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
945PolyExtStep::AndEqz(111, 805), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :65:18) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
946PolyExtStep::Sub(676, 32), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :90:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :33:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
947PolyExtStep::AndEqz(0, 806), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :90:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :33:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
948PolyExtStep::AndEqz(113, 726), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :90:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :33:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
949PolyExtStep::AndEqz(114, 724), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :90:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :33:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
950PolyExtStep::Get(154), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
951PolyExtStep::AndEqz(115, 807), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
952PolyExtStep::Get(158), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
953PolyExtStep::AndEqz(116, 808), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
954PolyExtStep::Get(162), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
955PolyExtStep::AndEqz(117, 809), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
956PolyExtStep::Get(166), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
957PolyExtStep::AndEqz(118, 810), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
958PolyExtStep::Get(173), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
959PolyExtStep::AndEqz(119, 811), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
960PolyExtStep::AndCond(112, 377, 120), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
961PolyExtStep::Sub(724, 24), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSUB ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :95:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
962PolyExtStep::AndEqz(114, 812), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSUB ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :95:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
963PolyExtStep::AndEqz(122, 807), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
964PolyExtStep::AndEqz(123, 808), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
965PolyExtStep::AndEqz(124, 809), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
966PolyExtStep::AndEqz(125, 810), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
967PolyExtStep::AndEqz(126, 811), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
968PolyExtStep::AndCond(121, 380, 127), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
969PolyExtStep::Sub(726, 5), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
970PolyExtStep::AndEqz(113, 813), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
971PolyExtStep::AndEqz(129, 724), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
972PolyExtStep::Get(711), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
973PolyExtStep::Sub(1, 814), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
974PolyExtStep::Mul(814, 815), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
975PolyExtStep::AndEqz(130, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
976PolyExtStep::Get(712), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
977PolyExtStep::Sub(1, 817), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
978PolyExtStep::Mul(817, 818), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
979PolyExtStep::AndEqz(131, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
980PolyExtStep::Get(713), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
981PolyExtStep::Sub(1, 820), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
982PolyExtStep::Mul(820, 821), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
983PolyExtStep::AndEqz(132, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
984PolyExtStep::Get(714), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
985PolyExtStep::Sub(1, 823), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
986PolyExtStep::Mul(823, 824), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
987PolyExtStep::AndEqz(133, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
988PolyExtStep::Get(715), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
989PolyExtStep::Sub(1, 826), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
990PolyExtStep::Mul(826, 827), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
991PolyExtStep::AndEqz(134, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
992PolyExtStep::Get(716), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
993PolyExtStep::Sub(1, 829), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
994PolyExtStep::Mul(829, 830), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
995PolyExtStep::AndEqz(135, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
996PolyExtStep::Get(717), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
997PolyExtStep::Sub(1, 832), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
998PolyExtStep::Mul(832, 833), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
999PolyExtStep::AndEqz(136, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1000PolyExtStep::Get(718), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1001PolyExtStep::Sub(1, 835), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1002PolyExtStep::Mul(835, 836), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1003PolyExtStep::AndEqz(137, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1004PolyExtStep::Get(719), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1005PolyExtStep::Sub(1, 838), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1006PolyExtStep::Mul(838, 839), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1007PolyExtStep::AndEqz(138, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1008PolyExtStep::Get(720), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1009PolyExtStep::Sub(1, 841), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1010PolyExtStep::Mul(841, 842), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1011PolyExtStep::AndEqz(139, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1012PolyExtStep::Get(721), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1013PolyExtStep::Sub(1, 844), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1014PolyExtStep::Mul(844, 845), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1015PolyExtStep::AndEqz(140, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1016PolyExtStep::Get(722), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1017PolyExtStep::Sub(1, 847), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1018PolyExtStep::Mul(847, 848), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1019PolyExtStep::AndEqz(141, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1020PolyExtStep::Get(723), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1021PolyExtStep::Sub(1, 850), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1022PolyExtStep::Mul(850, 851), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1023PolyExtStep::AndEqz(142, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1024PolyExtStep::Get(724), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1025PolyExtStep::Sub(1, 853), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1026PolyExtStep::Mul(853, 854), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1027PolyExtStep::AndEqz(143, 855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1028PolyExtStep::Get(725), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1029PolyExtStep::Sub(1, 856), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1030PolyExtStep::Mul(856, 857), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1031PolyExtStep::AndEqz(144, 858), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1032PolyExtStep::Get(726), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1033PolyExtStep::Sub(1, 859), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1034PolyExtStep::Mul(859, 860), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1035PolyExtStep::AndEqz(145, 861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1036PolyExtStep::Mul(817, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1037PolyExtStep::Mul(820, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1038PolyExtStep::Mul(823, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1039PolyExtStep::Mul(826, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1040PolyExtStep::Mul(829, 24), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1041PolyExtStep::Mul(832, 19), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1042PolyExtStep::Mul(835, 25), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1043PolyExtStep::Mul(838, 20), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1044PolyExtStep::Mul(841, 26), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1045PolyExtStep::Mul(844, 21), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1046PolyExtStep::Mul(847, 27), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1047PolyExtStep::Mul(850, 22), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1048PolyExtStep::Mul(853, 28), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1049PolyExtStep::Mul(856, 14), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1050PolyExtStep::Mul(859, 29), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1051PolyExtStep::Add(814, 862), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1052PolyExtStep::Add(877, 863), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1053PolyExtStep::Add(878, 864), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1054PolyExtStep::Add(879, 865), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1055PolyExtStep::Add(880, 866), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1056PolyExtStep::Add(881, 867), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1057PolyExtStep::Add(882, 868), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1058PolyExtStep::Add(883, 869), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1059PolyExtStep::Add(884, 870), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1060PolyExtStep::Add(885, 871), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1061PolyExtStep::Add(886, 872), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1062PolyExtStep::Add(887, 873), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1063PolyExtStep::Add(888, 874), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1064PolyExtStep::Add(889, 875), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1065PolyExtStep::Add(890, 876), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1066PolyExtStep::Sub(798, 891), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1067PolyExtStep::AndEqz(146, 892), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1068PolyExtStep::Get(727), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1069PolyExtStep::Sub(1, 893), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1070PolyExtStep::Mul(893, 894), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1071PolyExtStep::AndEqz(147, 895), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1072PolyExtStep::Get(728), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1073PolyExtStep::Sub(1, 896), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1074PolyExtStep::Mul(896, 897), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1075PolyExtStep::AndEqz(148, 898), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1076PolyExtStep::Get(729), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1077PolyExtStep::Sub(1, 899), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1078PolyExtStep::Mul(899, 900), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1079PolyExtStep::AndEqz(149, 901), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1080PolyExtStep::Get(730), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1081PolyExtStep::Sub(1, 902), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1082PolyExtStep::Mul(902, 903), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1083PolyExtStep::AndEqz(150, 904), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1084PolyExtStep::Get(731), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1085PolyExtStep::Sub(1, 905), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1086PolyExtStep::Mul(905, 906), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1087PolyExtStep::AndEqz(151, 907), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1088PolyExtStep::Get(732), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1089PolyExtStep::Sub(1, 908), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1090PolyExtStep::Mul(908, 909), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1091PolyExtStep::AndEqz(152, 910), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1092PolyExtStep::Get(733), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1093PolyExtStep::Sub(1, 911), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1094PolyExtStep::Mul(911, 912), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1095PolyExtStep::AndEqz(153, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1096PolyExtStep::Get(734), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1097PolyExtStep::Sub(1, 914), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1098PolyExtStep::Mul(914, 915), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1099PolyExtStep::AndEqz(154, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1100PolyExtStep::Get(735), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1101PolyExtStep::Sub(1, 917), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1102PolyExtStep::Mul(917, 918), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1103PolyExtStep::AndEqz(155, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1104PolyExtStep::Get(736), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1105PolyExtStep::Sub(1, 920), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1106PolyExtStep::Mul(920, 921), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1107PolyExtStep::AndEqz(156, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1108PolyExtStep::Get(737), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1109PolyExtStep::Sub(1, 923), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1110PolyExtStep::Mul(923, 924), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1111PolyExtStep::AndEqz(157, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1112PolyExtStep::Get(738), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1113PolyExtStep::Sub(1, 926), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1114PolyExtStep::Mul(926, 927), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1115PolyExtStep::AndEqz(158, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1116PolyExtStep::Get(739), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1117PolyExtStep::Sub(1, 929), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1118PolyExtStep::Mul(929, 930), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1119PolyExtStep::AndEqz(159, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1120PolyExtStep::Get(740), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1121PolyExtStep::Sub(1, 932), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1122PolyExtStep::Mul(932, 933), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1123PolyExtStep::AndEqz(160, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1124PolyExtStep::Get(741), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1125PolyExtStep::Sub(1, 935), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1126PolyExtStep::Mul(935, 936), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1127PolyExtStep::AndEqz(161, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1128PolyExtStep::Get(742), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1129PolyExtStep::Sub(1, 938), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1130PolyExtStep::Mul(938, 939), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1131PolyExtStep::AndEqz(162, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1132PolyExtStep::Mul(896, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1133PolyExtStep::Mul(899, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1134PolyExtStep::Mul(902, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1135PolyExtStep::Mul(905, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1136PolyExtStep::Mul(908, 24), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1137PolyExtStep::Mul(911, 19), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1138PolyExtStep::Mul(914, 25), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1139PolyExtStep::Mul(917, 20), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1140PolyExtStep::Mul(920, 26), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1141PolyExtStep::Mul(923, 21), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1142PolyExtStep::Mul(926, 27), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1143PolyExtStep::Mul(929, 22), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1144PolyExtStep::Mul(932, 28), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1145PolyExtStep::Mul(935, 14), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1146PolyExtStep::Mul(938, 29), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1147PolyExtStep::Add(893, 941), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1148PolyExtStep::Add(956, 942), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1149PolyExtStep::Add(957, 943), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1150PolyExtStep::Add(958, 944), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1151PolyExtStep::Add(959, 945), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1152PolyExtStep::Add(960, 946), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1153PolyExtStep::Add(961, 947), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1154PolyExtStep::Add(962, 948), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1155PolyExtStep::Add(963, 949), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1156PolyExtStep::Add(964, 950), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1157PolyExtStep::Add(965, 951), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1158PolyExtStep::Add(966, 952), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1159PolyExtStep::Add(967, 953), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1160PolyExtStep::Add(968, 954), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1161PolyExtStep::Add(969, 955), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1162PolyExtStep::Sub(802, 970), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1163PolyExtStep::AndEqz(163, 971), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1164PolyExtStep::Get(743), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1165PolyExtStep::Sub(1, 972), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1166PolyExtStep::Mul(972, 973), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1167PolyExtStep::AndEqz(164, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1168PolyExtStep::Get(744), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1169PolyExtStep::Sub(1, 975), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1170PolyExtStep::Mul(975, 976), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1171PolyExtStep::AndEqz(165, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1172PolyExtStep::Get(745), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1173PolyExtStep::Sub(1, 978), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1174PolyExtStep::Mul(978, 979), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1175PolyExtStep::AndEqz(166, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1176PolyExtStep::Get(746), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1177PolyExtStep::Sub(1, 981), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1178PolyExtStep::Mul(981, 982), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1179PolyExtStep::AndEqz(167, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1180PolyExtStep::Get(747), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1181PolyExtStep::Sub(1, 984), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1182PolyExtStep::Mul(984, 985), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1183PolyExtStep::AndEqz(168, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1184PolyExtStep::Get(748), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1185PolyExtStep::Sub(1, 987), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1186PolyExtStep::Mul(987, 988), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1187PolyExtStep::AndEqz(169, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1188PolyExtStep::Get(749), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1189PolyExtStep::Sub(1, 990), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1190PolyExtStep::Mul(990, 991), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1191PolyExtStep::AndEqz(170, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1192PolyExtStep::Get(750), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1193PolyExtStep::Sub(1, 993), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1194PolyExtStep::Mul(993, 994), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1195PolyExtStep::AndEqz(171, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1196PolyExtStep::Get(751), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1197PolyExtStep::Sub(1, 996), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1198PolyExtStep::Mul(996, 997), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1199PolyExtStep::AndEqz(172, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1200PolyExtStep::Get(752), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1201PolyExtStep::Sub(1, 999), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1202PolyExtStep::Mul(999, 1000), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1203PolyExtStep::AndEqz(173, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1204PolyExtStep::Get(753), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1205PolyExtStep::Sub(1, 1002), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1206PolyExtStep::Mul(1002, 1003), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1207PolyExtStep::AndEqz(174, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1208PolyExtStep::Get(754), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1209PolyExtStep::Sub(1, 1005), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1210PolyExtStep::Mul(1005, 1006), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1211PolyExtStep::AndEqz(175, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1212PolyExtStep::Get(755), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1213PolyExtStep::Sub(1, 1008), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1214PolyExtStep::Mul(1008, 1009), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1215PolyExtStep::AndEqz(176, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1216PolyExtStep::Get(756), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1217PolyExtStep::Sub(1, 1011), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1218PolyExtStep::Mul(1011, 1012), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1219PolyExtStep::AndEqz(177, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1220PolyExtStep::Get(757), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1221PolyExtStep::Sub(1, 1014), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1222PolyExtStep::Mul(1014, 1015), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1223PolyExtStep::AndEqz(178, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1224PolyExtStep::Get(758), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1225PolyExtStep::Sub(1, 1017), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1226PolyExtStep::Mul(1017, 1018), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1227PolyExtStep::AndEqz(179, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1228PolyExtStep::Mul(975, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1229PolyExtStep::Mul(978, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1230PolyExtStep::Mul(981, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1231PolyExtStep::Mul(984, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1232PolyExtStep::Mul(987, 24), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1233PolyExtStep::Mul(990, 19), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1234PolyExtStep::Mul(993, 25), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1235PolyExtStep::Mul(996, 20), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1236PolyExtStep::Mul(999, 26), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1237PolyExtStep::Mul(1002, 21), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1238PolyExtStep::Mul(1005, 27), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1239PolyExtStep::Mul(1008, 22), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1240PolyExtStep::Mul(1011, 28), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1241PolyExtStep::Mul(1014, 14), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1242PolyExtStep::Mul(1017, 29), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1243PolyExtStep::Add(972, 1020), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1244PolyExtStep::Add(1035, 1021), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1245PolyExtStep::Add(1036, 1022), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1246PolyExtStep::Add(1037, 1023), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1247PolyExtStep::Add(1038, 1024), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1248PolyExtStep::Add(1039, 1025), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1249PolyExtStep::Add(1040, 1026), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1250PolyExtStep::Add(1041, 1027), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1251PolyExtStep::Add(1042, 1028), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1252PolyExtStep::Add(1043, 1029), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1253PolyExtStep::Add(1044, 1030), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1254PolyExtStep::Add(1045, 1031), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1255PolyExtStep::Add(1046, 1032), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1256PolyExtStep::Add(1047, 1033), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1257PolyExtStep::Add(1048, 1034), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1258PolyExtStep::Sub(800, 1049), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1259PolyExtStep::AndEqz(180, 1050), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1260PolyExtStep::Get(759), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1261PolyExtStep::Sub(1, 1051), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1262PolyExtStep::Mul(1051, 1052), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1263PolyExtStep::AndEqz(181, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1264PolyExtStep::Get(760), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1265PolyExtStep::Sub(1, 1054), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1266PolyExtStep::Mul(1054, 1055), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1267PolyExtStep::AndEqz(182, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1268PolyExtStep::Get(761), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1269PolyExtStep::Sub(1, 1057), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1270PolyExtStep::Mul(1057, 1058), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1271PolyExtStep::AndEqz(183, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1272PolyExtStep::Get(762), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1273PolyExtStep::Sub(1, 1060), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1274PolyExtStep::Mul(1060, 1061), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1275PolyExtStep::AndEqz(184, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1276PolyExtStep::Get(763), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1277PolyExtStep::Sub(1, 1063), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1278PolyExtStep::Mul(1063, 1064), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1279PolyExtStep::AndEqz(185, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1280PolyExtStep::Get(764), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1281PolyExtStep::Sub(1, 1066), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1282PolyExtStep::Mul(1066, 1067), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1283PolyExtStep::AndEqz(186, 1068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1284PolyExtStep::Get(765), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1285PolyExtStep::Sub(1, 1069), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1286PolyExtStep::Mul(1069, 1070), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1287PolyExtStep::AndEqz(187, 1071), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1288PolyExtStep::Get(766), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1289PolyExtStep::Sub(1, 1072), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1290PolyExtStep::Mul(1072, 1073), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1291PolyExtStep::AndEqz(188, 1074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1292PolyExtStep::Get(767), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1293PolyExtStep::Sub(1, 1075), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1294PolyExtStep::Mul(1075, 1076), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1295PolyExtStep::AndEqz(189, 1077), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1296PolyExtStep::Get(768), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1297PolyExtStep::Sub(1, 1078), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1298PolyExtStep::Mul(1078, 1079), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1299PolyExtStep::AndEqz(190, 1080), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1300PolyExtStep::Get(769), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1301PolyExtStep::Sub(1, 1081), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1302PolyExtStep::Mul(1081, 1082), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1303PolyExtStep::AndEqz(191, 1083), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1304PolyExtStep::Get(770), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1305PolyExtStep::Sub(1, 1084), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1306PolyExtStep::Mul(1084, 1085), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1307PolyExtStep::AndEqz(192, 1086), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1308PolyExtStep::Get(771), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1309PolyExtStep::Sub(1, 1087), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1310PolyExtStep::Mul(1087, 1088), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1311PolyExtStep::AndEqz(193, 1089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1312PolyExtStep::Get(772), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1313PolyExtStep::Sub(1, 1090), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1314PolyExtStep::Mul(1090, 1091), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1315PolyExtStep::AndEqz(194, 1092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1316PolyExtStep::Get(773), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1317PolyExtStep::Sub(1, 1093), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1318PolyExtStep::Mul(1093, 1094), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1319PolyExtStep::AndEqz(195, 1095), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1320PolyExtStep::Get(774), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1321PolyExtStep::Sub(1, 1096), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1322PolyExtStep::Mul(1096, 1097), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))))
1323PolyExtStep::AndEqz(196, 1098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1324PolyExtStep::Mul(1054, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1325PolyExtStep::Mul(1057, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1326PolyExtStep::Mul(1060, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1327PolyExtStep::Mul(1063, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1328PolyExtStep::Mul(1066, 24), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1329PolyExtStep::Mul(1069, 19), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1330PolyExtStep::Mul(1072, 25), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1331PolyExtStep::Mul(1075, 20), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1332PolyExtStep::Mul(1078, 26), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1333PolyExtStep::Mul(1081, 21), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1334PolyExtStep::Mul(1084, 27), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1335PolyExtStep::Mul(1087, 22), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1336PolyExtStep::Mul(1090, 28), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1337PolyExtStep::Mul(1093, 14), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1338PolyExtStep::Mul(1096, 29), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1339PolyExtStep::Add(1051, 1099), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1340PolyExtStep::Add(1114, 1100), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1341PolyExtStep::Add(1115, 1101), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1342PolyExtStep::Add(1116, 1102), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1343PolyExtStep::Add(1117, 1103), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1344PolyExtStep::Add(1118, 1104), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1345PolyExtStep::Add(1119, 1105), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1346PolyExtStep::Add(1120, 1106), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1347PolyExtStep::Add(1121, 1107), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1348PolyExtStep::Add(1122, 1108), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1349PolyExtStep::Add(1123, 1109), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1350PolyExtStep::Add(1124, 1110), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1351PolyExtStep::Add(1125, 1111), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1352PolyExtStep::Add(1126, 1112), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1353PolyExtStep::Add(1127, 1113), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1354PolyExtStep::Sub(804, 1128), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1355PolyExtStep::AndEqz(197, 1129), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1356PolyExtStep::AndEqz(198, 807), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1357PolyExtStep::AndEqz(199, 808), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1358PolyExtStep::AndEqz(200, 809), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1359PolyExtStep::AndEqz(201, 810), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1360PolyExtStep::AndEqz(202, 811), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1361PolyExtStep::AndCond(128, 383, 203), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1362PolyExtStep::Sub(726, 3), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1363PolyExtStep::AndEqz(113, 1130), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1364PolyExtStep::AndEqz(205, 724), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1365PolyExtStep::AndEqz(206, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1366PolyExtStep::AndEqz(207, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1367PolyExtStep::AndEqz(208, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1368PolyExtStep::AndEqz(209, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1369PolyExtStep::AndEqz(210, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1370PolyExtStep::AndEqz(211, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1371PolyExtStep::AndEqz(212, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1372PolyExtStep::AndEqz(213, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1373PolyExtStep::AndEqz(214, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1374PolyExtStep::AndEqz(215, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1375PolyExtStep::AndEqz(216, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1376PolyExtStep::AndEqz(217, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1377PolyExtStep::AndEqz(218, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1378PolyExtStep::AndEqz(219, 855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1379PolyExtStep::AndEqz(220, 858), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1380PolyExtStep::AndEqz(221, 861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1381PolyExtStep::AndEqz(222, 892), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1382PolyExtStep::AndEqz(223, 895), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1383PolyExtStep::AndEqz(224, 898), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1384PolyExtStep::AndEqz(225, 901), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1385PolyExtStep::AndEqz(226, 904), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1386PolyExtStep::AndEqz(227, 907), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1387PolyExtStep::AndEqz(228, 910), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1388PolyExtStep::AndEqz(229, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1389PolyExtStep::AndEqz(230, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1390PolyExtStep::AndEqz(231, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1391PolyExtStep::AndEqz(232, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1392PolyExtStep::AndEqz(233, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1393PolyExtStep::AndEqz(234, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1394PolyExtStep::AndEqz(235, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1395PolyExtStep::AndEqz(236, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1396PolyExtStep::AndEqz(237, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1397PolyExtStep::AndEqz(238, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1398PolyExtStep::AndEqz(239, 971), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1399PolyExtStep::AndEqz(240, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1400PolyExtStep::AndEqz(241, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1401PolyExtStep::AndEqz(242, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1402PolyExtStep::AndEqz(243, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1403PolyExtStep::AndEqz(244, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1404PolyExtStep::AndEqz(245, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1405PolyExtStep::AndEqz(246, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1406PolyExtStep::AndEqz(247, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1407PolyExtStep::AndEqz(248, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1408PolyExtStep::AndEqz(249, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1409PolyExtStep::AndEqz(250, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1410PolyExtStep::AndEqz(251, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1411PolyExtStep::AndEqz(252, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1412PolyExtStep::AndEqz(253, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1413PolyExtStep::AndEqz(254, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1414PolyExtStep::AndEqz(255, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1415PolyExtStep::AndEqz(256, 1050), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1416PolyExtStep::AndEqz(257, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1417PolyExtStep::AndEqz(258, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1418PolyExtStep::AndEqz(259, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1419PolyExtStep::AndEqz(260, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1420PolyExtStep::AndEqz(261, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1421PolyExtStep::AndEqz(262, 1068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1422PolyExtStep::AndEqz(263, 1071), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1423PolyExtStep::AndEqz(264, 1074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1424PolyExtStep::AndEqz(265, 1077), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1425PolyExtStep::AndEqz(266, 1080), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1426PolyExtStep::AndEqz(267, 1083), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1427PolyExtStep::AndEqz(268, 1086), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1428PolyExtStep::AndEqz(269, 1089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1429PolyExtStep::AndEqz(270, 1092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1430PolyExtStep::AndEqz(271, 1095), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1431PolyExtStep::AndEqz(272, 1098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1432PolyExtStep::AndEqz(273, 1129), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1433PolyExtStep::AndEqz(274, 807), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1434PolyExtStep::AndEqz(275, 808), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1435PolyExtStep::AndEqz(276, 809), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1436PolyExtStep::AndEqz(277, 810), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1437PolyExtStep::AndEqz(278, 811), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1438PolyExtStep::AndCond(204, 386, 279), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1439PolyExtStep::Sub(726, 2), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1440PolyExtStep::AndEqz(113, 1131), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1441PolyExtStep::AndEqz(281, 724), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1442PolyExtStep::AndEqz(282, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1443PolyExtStep::AndEqz(283, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1444PolyExtStep::AndEqz(284, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1445PolyExtStep::AndEqz(285, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1446PolyExtStep::AndEqz(286, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1447PolyExtStep::AndEqz(287, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1448PolyExtStep::AndEqz(288, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1449PolyExtStep::AndEqz(289, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1450PolyExtStep::AndEqz(290, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1451PolyExtStep::AndEqz(291, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1452PolyExtStep::AndEqz(292, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1453PolyExtStep::AndEqz(293, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1454PolyExtStep::AndEqz(294, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1455PolyExtStep::AndEqz(295, 855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1456PolyExtStep::AndEqz(296, 858), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1457PolyExtStep::AndEqz(297, 861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1458PolyExtStep::AndEqz(298, 892), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1459PolyExtStep::AndEqz(299, 895), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1460PolyExtStep::AndEqz(300, 898), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1461PolyExtStep::AndEqz(301, 901), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1462PolyExtStep::AndEqz(302, 904), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1463PolyExtStep::AndEqz(303, 907), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1464PolyExtStep::AndEqz(304, 910), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1465PolyExtStep::AndEqz(305, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1466PolyExtStep::AndEqz(306, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1467PolyExtStep::AndEqz(307, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1468PolyExtStep::AndEqz(308, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1469PolyExtStep::AndEqz(309, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1470PolyExtStep::AndEqz(310, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1471PolyExtStep::AndEqz(311, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1472PolyExtStep::AndEqz(312, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1473PolyExtStep::AndEqz(313, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1474PolyExtStep::AndEqz(314, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1475PolyExtStep::AndEqz(315, 971), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1476PolyExtStep::AndEqz(316, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1477PolyExtStep::AndEqz(317, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1478PolyExtStep::AndEqz(318, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1479PolyExtStep::AndEqz(319, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1480PolyExtStep::AndEqz(320, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1481PolyExtStep::AndEqz(321, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1482PolyExtStep::AndEqz(322, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1483PolyExtStep::AndEqz(323, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1484PolyExtStep::AndEqz(324, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1485PolyExtStep::AndEqz(325, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1486PolyExtStep::AndEqz(326, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1487PolyExtStep::AndEqz(327, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1488PolyExtStep::AndEqz(328, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1489PolyExtStep::AndEqz(329, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1490PolyExtStep::AndEqz(330, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1491PolyExtStep::AndEqz(331, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1492PolyExtStep::AndEqz(332, 1050), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1493PolyExtStep::AndEqz(333, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1494PolyExtStep::AndEqz(334, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1495PolyExtStep::AndEqz(335, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1496PolyExtStep::AndEqz(336, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1497PolyExtStep::AndEqz(337, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1498PolyExtStep::AndEqz(338, 1068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1499PolyExtStep::AndEqz(339, 1071), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1500PolyExtStep::AndEqz(340, 1074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1501PolyExtStep::AndEqz(341, 1077), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1502PolyExtStep::AndEqz(342, 1080), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1503PolyExtStep::AndEqz(343, 1083), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1504PolyExtStep::AndEqz(344, 1086), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1505PolyExtStep::AndEqz(345, 1089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1506PolyExtStep::AndEqz(346, 1092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1507PolyExtStep::AndEqz(347, 1095), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1508PolyExtStep::AndEqz(348, 1098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1509PolyExtStep::AndEqz(349, 1129), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1510PolyExtStep::AndEqz(350, 807), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1511PolyExtStep::AndEqz(351, 808), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1512PolyExtStep::AndEqz(352, 809), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1513PolyExtStep::AndEqz(353, 810), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1514PolyExtStep::AndEqz(354, 811), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1515PolyExtStep::AndCond(280, 389, 355), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1516PolyExtStep::Sub(726, 7), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1517PolyExtStep::Add(798, 33), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:19) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:31) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1518PolyExtStep::Sub(1133, 802), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:31) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:31) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1519PolyExtStep::Add(800, 16), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:44) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:31) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1520PolyExtStep::Sub(1135, 804), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:55) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:31) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1521PolyExtStep::AndEqz(113, 1132), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1522PolyExtStep::AndEqz(357, 724), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1523PolyExtStep::Get(156), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1524PolyExtStep::Sub(807, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1525PolyExtStep::AndEqz(358, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1526PolyExtStep::AndEqz(359, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1527PolyExtStep::Mul(814, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1528PolyExtStep::Add(1139, 1137), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1529PolyExtStep::Sub(1134, 1140), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1530PolyExtStep::AndEqz(360, 1141), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1531PolyExtStep::Add(1136, 814), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1532PolyExtStep::Get(160), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1533PolyExtStep::Sub(808, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1534PolyExtStep::AndEqz(361, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1535PolyExtStep::AndEqz(362, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1536PolyExtStep::Mul(817, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1537PolyExtStep::Add(1145, 1143), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1538PolyExtStep::Sub(1142, 1146), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1539PolyExtStep::AndEqz(363, 1147), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1540PolyExtStep::AndEqz(364, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1541PolyExtStep::Get(164), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1542PolyExtStep::Sub(809, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1543PolyExtStep::AndEqz(365, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1544PolyExtStep::Mul(820, 29), // loc(callsite( builtin Mul at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:13) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1545PolyExtStep::Mul(1148, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1546PolyExtStep::Add(1150, 1151), // loc(callsite( builtin Add at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:22) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1547PolyExtStep::Sub(800, 1152), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1548PolyExtStep::AndEqz(366, 1153), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1549PolyExtStep::AndEqz(367, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1550PolyExtStep::Get(167), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1551PolyExtStep::Sub(810, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1552PolyExtStep::AndEqz(368, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1553PolyExtStep::Mul(823, 29), // loc(callsite( builtin Mul at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:13) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1554PolyExtStep::Mul(1154, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1555PolyExtStep::Add(1156, 1157), // loc(callsite( builtin Add at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:22) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1556PolyExtStep::Sub(804, 1158), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1557PolyExtStep::AndEqz(369, 1159), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1558PolyExtStep::AndEqz(370, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1559PolyExtStep::Get(179), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1560PolyExtStep::Sub(811, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1561PolyExtStep::AndEqz(371, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1562PolyExtStep::Mul(826, 29), // loc(callsite( builtin Mul at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:13) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1563PolyExtStep::Mul(1160, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1564PolyExtStep::Add(1162, 1163), // loc(callsite( builtin Add at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:22) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1565PolyExtStep::Sub(1143, 1164), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1566PolyExtStep::AndEqz(372, 1165), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1567PolyExtStep::Mul(820, 824), // loc(callsite( builtin Mul at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1568PolyExtStep::Mul(1166, 827), // loc(callsite( builtin Mul at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:32) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1569PolyExtStep::Mul(821, 823), // loc(callsite( builtin Mul at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:54) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1570PolyExtStep::Mul(1168, 826), // loc(callsite( builtin Mul at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:58) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1571PolyExtStep::Add(1167, 1169), // loc(callsite( builtin Add at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:43) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1572PolyExtStep::Sub(1170, 829), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:19) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1573PolyExtStep::AndEqz(373, 1171), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:19) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1574PolyExtStep::Add(829, 826), // loc(callsite( builtin Add at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:31) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1575PolyExtStep::Mul(829, 7), // loc(callsite( builtin Mul at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:47) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1576PolyExtStep::Mul(1173, 826), // loc(callsite( builtin Mul at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:51) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1577PolyExtStep::Sub(1172, 1174), // loc(callsite( builtin Sub at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:42) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1578PolyExtStep::Sub(1175, 832), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:30) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1579PolyExtStep::AndEqz(374, 1176), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:30) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1580PolyExtStep::AndCond(356, 392, 375), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1581PolyExtStep::Sub(726, 6), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :121:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1582PolyExtStep::AndEqz(113, 1177), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :121:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1583PolyExtStep::AndEqz(377, 724), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :121:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1584PolyExtStep::AndEqz(378, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :122:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1585PolyExtStep::AndEqz(379, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :122:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1586PolyExtStep::AndEqz(380, 1141), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :122:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1587PolyExtStep::AndEqz(381, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :122:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1588PolyExtStep::AndEqz(382, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :122:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1589PolyExtStep::AndEqz(383, 1147), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :122:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1590PolyExtStep::AndEqz(384, 809), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1591PolyExtStep::AndEqz(385, 810), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1592PolyExtStep::AndEqz(386, 811), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1593PolyExtStep::AndCond(376, 395, 387), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1594PolyExtStep::Sub(676, 38), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpADDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :127:18) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :40:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1595PolyExtStep::AndEqz(0, 1178), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpADDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :127:18) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :40:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1596PolyExtStep::AndEqz(389, 726), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpADDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :127:18) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :40:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1597PolyExtStep::AndEqz(390, 807), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1598PolyExtStep::AndEqz(391, 808), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1599PolyExtStep::AndEqz(392, 809), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1600PolyExtStep::AndEqz(393, 810), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1601PolyExtStep::AndEqz(394, 811), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1602PolyExtStep::AndCond(388, 398, 395), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1603PolyExtStep::Add(798, 802), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :91:26) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :33:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1604PolyExtStep::Mul(1179, 377), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1605PolyExtStep::Mul(1134, 380), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1606PolyExtStep::Get(711), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1607PolyExtStep::Get(712), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1608PolyExtStep::Get(713), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1609PolyExtStep::Get(714), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1610PolyExtStep::Get(715), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1611PolyExtStep::Get(716), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1612PolyExtStep::Get(717), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1613PolyExtStep::Get(718), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1614PolyExtStep::Get(719), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1615PolyExtStep::Get(720), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1616PolyExtStep::Get(721), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1617PolyExtStep::Get(722), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1618PolyExtStep::Get(723), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1619PolyExtStep::Get(724), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1620PolyExtStep::Get(725), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1621PolyExtStep::Get(726), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1622PolyExtStep::Get(727), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1623PolyExtStep::Get(728), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1624PolyExtStep::Get(729), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1625PolyExtStep::Get(730), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1626PolyExtStep::Get(731), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1627PolyExtStep::Get(732), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1628PolyExtStep::Get(733), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1629PolyExtStep::Get(734), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1630PolyExtStep::Get(735), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1631PolyExtStep::Get(736), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1632PolyExtStep::Get(737), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1633PolyExtStep::Get(738), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1634PolyExtStep::Get(739), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1635PolyExtStep::Get(740), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1636PolyExtStep::Get(741), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1637PolyExtStep::Get(742), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1638PolyExtStep::Mul(1182, 1198), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1639PolyExtStep::Mul(1183, 1199), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1640PolyExtStep::Mul(1184, 1200), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1641PolyExtStep::Mul(1185, 1201), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1642PolyExtStep::Mul(1186, 1202), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1643PolyExtStep::Mul(1187, 1203), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1644PolyExtStep::Mul(1188, 1204), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1645PolyExtStep::Mul(1189, 1205), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1646PolyExtStep::Mul(1190, 1206), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1647PolyExtStep::Mul(1191, 1207), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1648PolyExtStep::Mul(1192, 1208), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1649PolyExtStep::Mul(1193, 1209), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1650PolyExtStep::Mul(1194, 1210), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1651PolyExtStep::Mul(1195, 1211), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1652PolyExtStep::Mul(1196, 1212), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1653PolyExtStep::Mul(1197, 1213), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1654PolyExtStep::Mul(1215, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1655PolyExtStep::Mul(1216, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1656PolyExtStep::Mul(1217, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1657PolyExtStep::Mul(1218, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1658PolyExtStep::Mul(1219, 24), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1659PolyExtStep::Mul(1220, 19), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1660PolyExtStep::Mul(1221, 25), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1661PolyExtStep::Mul(1222, 20), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1662PolyExtStep::Mul(1223, 26), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1663PolyExtStep::Mul(1224, 21), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1664PolyExtStep::Mul(1225, 27), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1665PolyExtStep::Mul(1226, 22), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1666PolyExtStep::Mul(1227, 28), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1667PolyExtStep::Mul(1228, 14), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1668PolyExtStep::Mul(1229, 29), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1669PolyExtStep::Add(1214, 1230), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1670PolyExtStep::Add(1245, 1231), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1671PolyExtStep::Add(1246, 1232), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1672PolyExtStep::Add(1247, 1233), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1673PolyExtStep::Add(1248, 1234), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1674PolyExtStep::Add(1249, 1235), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1675PolyExtStep::Add(1250, 1236), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1676PolyExtStep::Add(1251, 1237), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1677PolyExtStep::Add(1252, 1238), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1678PolyExtStep::Add(1253, 1239), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1679PolyExtStep::Add(1254, 1240), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1680PolyExtStep::Add(1255, 1241), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1681PolyExtStep::Add(1256, 1242), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1682PolyExtStep::Add(1257, 1243), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1683PolyExtStep::Add(1258, 1244), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1684PolyExtStep::Mul(1259, 7), // loc(callsite( builtin Mul at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :165:27) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1685PolyExtStep::Sub(1179, 1260), // loc(callsite( builtin Sub at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :165:21) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1686PolyExtStep::Mul(1261, 383), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1687PolyExtStep::Sub(1179, 1259), // loc(callsite( builtin Sub at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :160:21) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1688PolyExtStep::Mul(1263, 386), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1689PolyExtStep::Mul(1259, 389), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1690PolyExtStep::Mul(1188, 392), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1691PolyExtStep::Sub(1, 1183), // loc(callsite( builtin Sub at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :120:27) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :122:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1692PolyExtStep::Mul(1267, 395), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1693PolyExtStep::Add(798, 730), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( OpADDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :128:26) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :40:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1694PolyExtStep::Mul(1269, 398), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1695PolyExtStep::Add(1180, 1181), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1696PolyExtStep::Add(1271, 1262), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1697PolyExtStep::Add(1272, 1264), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1698PolyExtStep::Add(1273, 1265), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1699PolyExtStep::Add(1274, 1266), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1700PolyExtStep::Add(1275, 1268), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1701PolyExtStep::Add(1276, 1270), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1702PolyExtStep::Add(800, 804), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :91:26) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :33:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1703PolyExtStep::Mul(1278, 377), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1704PolyExtStep::Mul(1136, 380), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1705PolyExtStep::Get(743), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1706PolyExtStep::Get(744), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1707PolyExtStep::Get(745), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1708PolyExtStep::Get(746), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1709PolyExtStep::Get(747), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1710PolyExtStep::Get(748), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1711PolyExtStep::Get(749), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1712PolyExtStep::Get(750), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1713PolyExtStep::Get(751), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1714PolyExtStep::Get(752), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1715PolyExtStep::Get(753), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1716PolyExtStep::Get(754), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1717PolyExtStep::Get(755), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1718PolyExtStep::Get(756), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1719PolyExtStep::Get(757), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1720PolyExtStep::Get(758), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1721PolyExtStep::Get(759), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1722PolyExtStep::Get(760), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1723PolyExtStep::Get(761), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1724PolyExtStep::Get(762), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1725PolyExtStep::Get(763), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1726PolyExtStep::Get(764), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1727PolyExtStep::Get(765), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1728PolyExtStep::Get(766), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1729PolyExtStep::Get(767), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1730PolyExtStep::Get(768), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1731PolyExtStep::Get(769), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1732PolyExtStep::Get(770), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1733PolyExtStep::Get(771), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1734PolyExtStep::Get(772), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1735PolyExtStep::Get(773), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1736PolyExtStep::Get(774), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1737PolyExtStep::Mul(1281, 1297), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1738PolyExtStep::Mul(1282, 1298), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1739PolyExtStep::Mul(1283, 1299), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1740PolyExtStep::Mul(1284, 1300), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1741PolyExtStep::Mul(1285, 1301), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1742PolyExtStep::Mul(1286, 1302), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1743PolyExtStep::Mul(1287, 1303), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1744PolyExtStep::Mul(1288, 1304), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1745PolyExtStep::Mul(1289, 1305), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1746PolyExtStep::Mul(1290, 1306), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1747PolyExtStep::Mul(1291, 1307), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1748PolyExtStep::Mul(1292, 1308), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1749PolyExtStep::Mul(1293, 1309), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1750PolyExtStep::Mul(1294, 1310), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1751PolyExtStep::Mul(1295, 1311), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1752PolyExtStep::Mul(1296, 1312), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1753PolyExtStep::Mul(1314, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1754PolyExtStep::Mul(1315, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1755PolyExtStep::Mul(1316, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1756PolyExtStep::Mul(1317, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1757PolyExtStep::Mul(1318, 24), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1758PolyExtStep::Mul(1319, 19), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1759PolyExtStep::Mul(1320, 25), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1760PolyExtStep::Mul(1321, 20), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1761PolyExtStep::Mul(1322, 26), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1762PolyExtStep::Mul(1323, 21), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1763PolyExtStep::Mul(1324, 27), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1764PolyExtStep::Mul(1325, 22), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1765PolyExtStep::Mul(1326, 28), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1766PolyExtStep::Mul(1327, 14), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1767PolyExtStep::Mul(1328, 29), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1768PolyExtStep::Add(1313, 1329), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1769PolyExtStep::Add(1344, 1330), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1770PolyExtStep::Add(1345, 1331), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1771PolyExtStep::Add(1346, 1332), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1772PolyExtStep::Add(1347, 1333), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1773PolyExtStep::Add(1348, 1334), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1774PolyExtStep::Add(1349, 1335), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1775PolyExtStep::Add(1350, 1336), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1776PolyExtStep::Add(1351, 1337), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1777PolyExtStep::Add(1352, 1338), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1778PolyExtStep::Add(1353, 1339), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1779PolyExtStep::Add(1354, 1340), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1780PolyExtStep::Add(1355, 1341), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1781PolyExtStep::Add(1356, 1342), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1782PolyExtStep::Add(1357, 1343), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1783PolyExtStep::Mul(1358, 7), // loc(callsite( builtin Mul at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :165:59) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1784PolyExtStep::Sub(1278, 1359), // loc(callsite( builtin Sub at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :165:52) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1785PolyExtStep::Mul(1360, 383), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1786PolyExtStep::Sub(1278, 1358), // loc(callsite( builtin Sub at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :160:50) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1787PolyExtStep::Mul(1362, 386), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1788PolyExtStep::Mul(1358, 389), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1789PolyExtStep::Add(800, 731), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( OpADDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :128:26) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :40:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1790PolyExtStep::Mul(1365, 398), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1791PolyExtStep::Add(1279, 1280), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1792PolyExtStep::Add(1367, 1361), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1793PolyExtStep::Add(1368, 1363), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1794PolyExtStep::Add(1369, 1364), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1795PolyExtStep::Add(1370, 1366), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1796PolyExtStep::Get(185), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1797PolyExtStep::Get(191), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1798PolyExtStep::Sub(1372, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1799PolyExtStep::AndEqz(396, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1800PolyExtStep::Get(197), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1801PolyExtStep::Sub(1, 1375), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1802PolyExtStep::Mul(1375, 1376), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1803PolyExtStep::AndEqz(397, 1377), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1804PolyExtStep::Mul(1375, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1805PolyExtStep::Add(1378, 1373), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1806PolyExtStep::Sub(1277, 1379), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1807PolyExtStep::AndEqz(398, 1380), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1808PolyExtStep::Add(1371, 1375), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1809PolyExtStep::Get(203), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1810PolyExtStep::Get(209), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1811PolyExtStep::Sub(1382, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1812PolyExtStep::AndEqz(399, 1384), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1813PolyExtStep::Get(215), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1814PolyExtStep::Sub(1, 1385), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1815PolyExtStep::Mul(1385, 1386), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1816PolyExtStep::AndEqz(400, 1387), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1817PolyExtStep::Mul(1385, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1818PolyExtStep::Add(1388, 1383), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1819PolyExtStep::Sub(1381, 1389), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1820PolyExtStep::AndEqz(401, 1390), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1821PolyExtStep::Get(221), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1822PolyExtStep::Get(227), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1823PolyExtStep::Sub(1391, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1824PolyExtStep::AndEqz(402, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1825PolyExtStep::Get(233), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1826PolyExtStep::Sub(1, 1394), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1827PolyExtStep::Mul(1394, 1395), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1828PolyExtStep::AndEqz(403, 1396), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1829PolyExtStep::Mul(1394, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1830PolyExtStep::Add(1397, 1392), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1831PolyExtStep::Sub(522, 1398), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1832PolyExtStep::AndEqz(404, 1399), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1833PolyExtStep::Add(537, 1394), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1834PolyExtStep::Get(239), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1835PolyExtStep::Get(245), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1836PolyExtStep::Sub(1401, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1837PolyExtStep::AndEqz(405, 1403), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1838PolyExtStep::Get(251), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1839PolyExtStep::Sub(1, 1404), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1840PolyExtStep::Mul(1404, 1405), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1841PolyExtStep::AndEqz(406, 1406), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1842PolyExtStep::Mul(1404, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1843PolyExtStep::Add(1407, 1402), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1844PolyExtStep::Sub(1400, 1408), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1845PolyExtStep::AndEqz(407, 1409), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1846PolyExtStep::Get(257), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :8:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1847PolyExtStep::Get(263), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :11:20) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1848PolyExtStep::Sub(1, 1410), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1849PolyExtStep::Mul(1410, 1412), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1850PolyExtStep::AndEqz(408, 1413), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1851PolyExtStep::Mul(718, 1411), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1852PolyExtStep::Sub(1414, 1412), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1853PolyExtStep::AndEqz(409, 1415), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1854PolyExtStep::Mul(1410, 718), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1855PolyExtStep::AndEqz(410, 1416), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1856PolyExtStep::Mul(1410, 1411), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1857PolyExtStep::AndEqz(411, 1417), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1858PolyExtStep::Mul(1412, 407), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :72:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1859PolyExtStep::Mul(1418, 718), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:11) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1860PolyExtStep::Sub(1, 1418), // loc(callsite( builtin Sub at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:90) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1861PolyExtStep::Mul(1420, 19), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:102) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1862PolyExtStep::Add(506, 1421), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:85) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1863PolyExtStep::Add(1422, 1419), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:106) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1864PolyExtStep::Get(269), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1865PolyExtStep::Sub(1423, 1424), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1866PolyExtStep::AndEqz(412, 1425), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1867PolyExtStep::Get(281), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1868PolyExtStep::Get(275), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :26:28) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1869PolyExtStep::Get(287), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1870PolyExtStep::Get(305), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1871PolyExtStep::Get(311), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1872PolyExtStep::Get(317), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1873PolyExtStep::Get(323), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
1874PolyExtStep::Sub(1426, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1875PolyExtStep::AndEqz(413, 1433), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1876PolyExtStep::Sub(1429, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1877PolyExtStep::AndEqz(414, 1434), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1878PolyExtStep::Sub(1430, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1879PolyExtStep::AndEqz(415, 1435), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1880PolyExtStep::AndEqz(416, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1881PolyExtStep::Sub(1427, 1424), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1882PolyExtStep::AndEqz(417, 1436), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1883PolyExtStep::Sub(1430, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1884PolyExtStep::Sub(1437, 1428), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1885PolyExtStep::Get(329), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :54:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1886PolyExtStep::Get(335), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1887PolyExtStep::Sub(1439, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1888PolyExtStep::AndEqz(418, 1441), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1889PolyExtStep::Sub(1440, 1438), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1890PolyExtStep::AndEqz(419, 1442), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
1891PolyExtStep::Sub(1431, 1373), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1892PolyExtStep::AndEqz(420, 1443), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1893PolyExtStep::Sub(1432, 1383), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1894PolyExtStep::AndEqz(421, 1444), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
1895PolyExtStep::AndCond(31, 422, 422), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
1896PolyExtStep::Mul(673, 27), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :68:45) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1897PolyExtStep::Add(727, 1445), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :68:36) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1898PolyExtStep::Mul(722, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :68:61) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1899PolyExtStep::Add(1446, 1447), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :68:53) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1900PolyExtStep::Add(1448, 715), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :68:72) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1901PolyExtStep::Add(1449, 716), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :68:86) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1902PolyExtStep::AndEqz(389, 813), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1903PolyExtStep::AndEqz(424, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1904PolyExtStep::AndEqz(425, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1905PolyExtStep::AndEqz(426, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1906PolyExtStep::AndEqz(427, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1907PolyExtStep::AndEqz(428, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1908PolyExtStep::AndEqz(429, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1909PolyExtStep::AndEqz(430, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1910PolyExtStep::AndEqz(431, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1911PolyExtStep::AndEqz(432, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1912PolyExtStep::AndEqz(433, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1913PolyExtStep::AndEqz(434, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1914PolyExtStep::AndEqz(435, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1915PolyExtStep::AndEqz(436, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1916PolyExtStep::AndEqz(437, 855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1917PolyExtStep::AndEqz(438, 858), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1918PolyExtStep::AndEqz(439, 861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1919PolyExtStep::AndEqz(440, 892), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1920PolyExtStep::AndEqz(441, 895), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1921PolyExtStep::AndEqz(442, 898), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1922PolyExtStep::AndEqz(443, 901), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1923PolyExtStep::AndEqz(444, 904), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1924PolyExtStep::AndEqz(445, 907), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1925PolyExtStep::AndEqz(446, 910), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1926PolyExtStep::AndEqz(447, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1927PolyExtStep::AndEqz(448, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1928PolyExtStep::AndEqz(449, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1929PolyExtStep::AndEqz(450, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1930PolyExtStep::AndEqz(451, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1931PolyExtStep::AndEqz(452, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1932PolyExtStep::AndEqz(453, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1933PolyExtStep::AndEqz(454, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1934PolyExtStep::AndEqz(455, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1935PolyExtStep::AndEqz(456, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1936PolyExtStep::Sub(730, 970), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1937PolyExtStep::AndEqz(457, 1451), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1938PolyExtStep::AndEqz(458, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1939PolyExtStep::AndEqz(459, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1940PolyExtStep::AndEqz(460, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1941PolyExtStep::AndEqz(461, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1942PolyExtStep::AndEqz(462, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1943PolyExtStep::AndEqz(463, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1944PolyExtStep::AndEqz(464, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1945PolyExtStep::AndEqz(465, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1946PolyExtStep::AndEqz(466, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1947PolyExtStep::AndEqz(467, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1948PolyExtStep::AndEqz(468, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1949PolyExtStep::AndEqz(469, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1950PolyExtStep::AndEqz(470, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1951PolyExtStep::AndEqz(471, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1952PolyExtStep::AndEqz(472, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1953PolyExtStep::AndEqz(473, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1954PolyExtStep::AndEqz(474, 1050), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1955PolyExtStep::AndEqz(475, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1956PolyExtStep::AndEqz(476, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1957PolyExtStep::AndEqz(477, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1958PolyExtStep::AndEqz(478, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1959PolyExtStep::AndEqz(479, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1960PolyExtStep::AndEqz(480, 1068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1961PolyExtStep::AndEqz(481, 1071), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1962PolyExtStep::AndEqz(482, 1074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1963PolyExtStep::AndEqz(483, 1077), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1964PolyExtStep::AndEqz(484, 1080), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1965PolyExtStep::AndEqz(485, 1083), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1966PolyExtStep::AndEqz(486, 1086), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1967PolyExtStep::AndEqz(487, 1089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1968PolyExtStep::AndEqz(488, 1092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1969PolyExtStep::AndEqz(489, 1095), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1970PolyExtStep::AndEqz(490, 1098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1971PolyExtStep::Sub(731, 1128), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1972PolyExtStep::AndEqz(491, 1452), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1973PolyExtStep::AndEqz(492, 807), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1974PolyExtStep::AndEqz(493, 808), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1975PolyExtStep::AndEqz(494, 809), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1976PolyExtStep::AndEqz(495, 810), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1977PolyExtStep::AndEqz(496, 811), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1978PolyExtStep::AndCond(112, 377, 497), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
1979PolyExtStep::AndEqz(389, 1130), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
1980PolyExtStep::AndEqz(499, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1981PolyExtStep::AndEqz(500, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1982PolyExtStep::AndEqz(501, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1983PolyExtStep::AndEqz(502, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1984PolyExtStep::AndEqz(503, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1985PolyExtStep::AndEqz(504, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1986PolyExtStep::AndEqz(505, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1987PolyExtStep::AndEqz(506, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1988PolyExtStep::AndEqz(507, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1989PolyExtStep::AndEqz(508, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1990PolyExtStep::AndEqz(509, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1991PolyExtStep::AndEqz(510, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1992PolyExtStep::AndEqz(511, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1993PolyExtStep::AndEqz(512, 855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1994PolyExtStep::AndEqz(513, 858), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1995PolyExtStep::AndEqz(514, 861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1996PolyExtStep::AndEqz(515, 892), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
1997PolyExtStep::AndEqz(516, 895), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1998PolyExtStep::AndEqz(517, 898), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
1999PolyExtStep::AndEqz(518, 901), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2000PolyExtStep::AndEqz(519, 904), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2001PolyExtStep::AndEqz(520, 907), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2002PolyExtStep::AndEqz(521, 910), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2003PolyExtStep::AndEqz(522, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2004PolyExtStep::AndEqz(523, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2005PolyExtStep::AndEqz(524, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2006PolyExtStep::AndEqz(525, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2007PolyExtStep::AndEqz(526, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2008PolyExtStep::AndEqz(527, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2009PolyExtStep::AndEqz(528, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2010PolyExtStep::AndEqz(529, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2011PolyExtStep::AndEqz(530, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2012PolyExtStep::AndEqz(531, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2013PolyExtStep::AndEqz(532, 1451), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2014PolyExtStep::AndEqz(533, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2015PolyExtStep::AndEqz(534, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2016PolyExtStep::AndEqz(535, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2017PolyExtStep::AndEqz(536, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2018PolyExtStep::AndEqz(537, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2019PolyExtStep::AndEqz(538, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2020PolyExtStep::AndEqz(539, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2021PolyExtStep::AndEqz(540, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2022PolyExtStep::AndEqz(541, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2023PolyExtStep::AndEqz(542, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2024PolyExtStep::AndEqz(543, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2025PolyExtStep::AndEqz(544, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2026PolyExtStep::AndEqz(545, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2027PolyExtStep::AndEqz(546, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2028PolyExtStep::AndEqz(547, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2029PolyExtStep::AndEqz(548, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2030PolyExtStep::AndEqz(549, 1050), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2031PolyExtStep::AndEqz(550, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2032PolyExtStep::AndEqz(551, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2033PolyExtStep::AndEqz(552, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2034PolyExtStep::AndEqz(553, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2035PolyExtStep::AndEqz(554, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2036PolyExtStep::AndEqz(555, 1068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2037PolyExtStep::AndEqz(556, 1071), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2038PolyExtStep::AndEqz(557, 1074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2039PolyExtStep::AndEqz(558, 1077), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2040PolyExtStep::AndEqz(559, 1080), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2041PolyExtStep::AndEqz(560, 1083), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2042PolyExtStep::AndEqz(561, 1086), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2043PolyExtStep::AndEqz(562, 1089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2044PolyExtStep::AndEqz(563, 1092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2045PolyExtStep::AndEqz(564, 1095), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2046PolyExtStep::AndEqz(565, 1098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2047PolyExtStep::AndEqz(566, 1452), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2048PolyExtStep::AndEqz(567, 807), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2049PolyExtStep::AndEqz(568, 808), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2050PolyExtStep::AndEqz(569, 809), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2051PolyExtStep::AndEqz(570, 810), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2052PolyExtStep::AndEqz(571, 811), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2053PolyExtStep::AndCond(498, 380, 572), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2054PolyExtStep::AndEqz(389, 1131), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2055PolyExtStep::AndEqz(574, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2056PolyExtStep::AndEqz(575, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2057PolyExtStep::AndEqz(576, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2058PolyExtStep::AndEqz(577, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2059PolyExtStep::AndEqz(578, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2060PolyExtStep::AndEqz(579, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2061PolyExtStep::AndEqz(580, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2062PolyExtStep::AndEqz(581, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2063PolyExtStep::AndEqz(582, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2064PolyExtStep::AndEqz(583, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2065PolyExtStep::AndEqz(584, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2066PolyExtStep::AndEqz(585, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2067PolyExtStep::AndEqz(586, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2068PolyExtStep::AndEqz(587, 855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2069PolyExtStep::AndEqz(588, 858), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2070PolyExtStep::AndEqz(589, 861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2071PolyExtStep::AndEqz(590, 892), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2072PolyExtStep::AndEqz(591, 895), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2073PolyExtStep::AndEqz(592, 898), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2074PolyExtStep::AndEqz(593, 901), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2075PolyExtStep::AndEqz(594, 904), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2076PolyExtStep::AndEqz(595, 907), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2077PolyExtStep::AndEqz(596, 910), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2078PolyExtStep::AndEqz(597, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2079PolyExtStep::AndEqz(598, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2080PolyExtStep::AndEqz(599, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2081PolyExtStep::AndEqz(600, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2082PolyExtStep::AndEqz(601, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2083PolyExtStep::AndEqz(602, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2084PolyExtStep::AndEqz(603, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2085PolyExtStep::AndEqz(604, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2086PolyExtStep::AndEqz(605, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2087PolyExtStep::AndEqz(606, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2088PolyExtStep::AndEqz(607, 1451), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2089PolyExtStep::AndEqz(608, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2090PolyExtStep::AndEqz(609, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2091PolyExtStep::AndEqz(610, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2092PolyExtStep::AndEqz(611, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2093PolyExtStep::AndEqz(612, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2094PolyExtStep::AndEqz(613, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2095PolyExtStep::AndEqz(614, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2096PolyExtStep::AndEqz(615, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2097PolyExtStep::AndEqz(616, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2098PolyExtStep::AndEqz(617, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2099PolyExtStep::AndEqz(618, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2100PolyExtStep::AndEqz(619, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2101PolyExtStep::AndEqz(620, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2102PolyExtStep::AndEqz(621, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2103PolyExtStep::AndEqz(622, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2104PolyExtStep::AndEqz(623, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2105PolyExtStep::AndEqz(624, 1050), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2106PolyExtStep::AndEqz(625, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2107PolyExtStep::AndEqz(626, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2108PolyExtStep::AndEqz(627, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2109PolyExtStep::AndEqz(628, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2110PolyExtStep::AndEqz(629, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2111PolyExtStep::AndEqz(630, 1068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2112PolyExtStep::AndEqz(631, 1071), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2113PolyExtStep::AndEqz(632, 1074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2114PolyExtStep::AndEqz(633, 1077), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2115PolyExtStep::AndEqz(634, 1080), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2116PolyExtStep::AndEqz(635, 1083), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2117PolyExtStep::AndEqz(636, 1086), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2118PolyExtStep::AndEqz(637, 1089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2119PolyExtStep::AndEqz(638, 1092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2120PolyExtStep::AndEqz(639, 1095), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2121PolyExtStep::AndEqz(640, 1098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2122PolyExtStep::AndEqz(641, 1452), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2123PolyExtStep::AndEqz(642, 807), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2124PolyExtStep::AndEqz(643, 808), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2125PolyExtStep::AndEqz(644, 809), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2126PolyExtStep::AndEqz(645, 810), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2127PolyExtStep::AndEqz(646, 811), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2128PolyExtStep::AndCond(573, 383, 647), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2129PolyExtStep::Sub(1133, 730), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:31) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:31) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2130PolyExtStep::Sub(1135, 731), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:55) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:31) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2131PolyExtStep::AndEqz(389, 1132), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2132PolyExtStep::AndEqz(649, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2133PolyExtStep::AndEqz(650, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2134PolyExtStep::Sub(1453, 1140), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2135PolyExtStep::AndEqz(651, 1455), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2136PolyExtStep::Add(1454, 814), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2137PolyExtStep::AndEqz(652, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2138PolyExtStep::AndEqz(653, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2139PolyExtStep::Sub(1456, 1146), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2140PolyExtStep::AndEqz(654, 1457), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2141PolyExtStep::AndEqz(655, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2142PolyExtStep::AndEqz(656, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2143PolyExtStep::AndEqz(657, 1153), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2144PolyExtStep::AndEqz(658, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2145PolyExtStep::AndEqz(659, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2146PolyExtStep::Sub(731, 1158), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2147PolyExtStep::AndEqz(660, 1458), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2148PolyExtStep::AndEqz(661, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2149PolyExtStep::AndEqz(662, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2150PolyExtStep::AndEqz(663, 1165), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2151PolyExtStep::AndEqz(664, 1171), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:19) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2152PolyExtStep::AndEqz(665, 1176), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:30) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2153PolyExtStep::AndCond(648, 386, 666), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2154PolyExtStep::AndEqz(389, 1177), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :153:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2155PolyExtStep::AndEqz(668, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :154:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2156PolyExtStep::AndEqz(669, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :154:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2157PolyExtStep::AndEqz(670, 1455), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :154:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2158PolyExtStep::AndEqz(671, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :154:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2159PolyExtStep::AndEqz(672, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :154:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2160PolyExtStep::AndEqz(673, 1457), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :154:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2161PolyExtStep::AndEqz(674, 809), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2162PolyExtStep::AndEqz(675, 810), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2163PolyExtStep::AndEqz(676, 811), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2164PolyExtStep::AndCond(667, 389, 677), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2165PolyExtStep::Sub(676, 39), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2166PolyExtStep::Sub(798, 802), // loc(callsite( builtin Sub at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:25) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2167PolyExtStep::Sub(800, 804), // loc(callsite( builtin Sub at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2168PolyExtStep::AndEqz(0, 1459), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2169PolyExtStep::AndEqz(679, 726), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2170PolyExtStep::AndEqz(680, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2171PolyExtStep::Mul(1460, 817), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2172PolyExtStep::Sub(1462, 815), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2173PolyExtStep::AndEqz(681, 1463), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2174PolyExtStep::Mul(814, 1460), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2175PolyExtStep::AndEqz(682, 1464), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2176PolyExtStep::Mul(814, 817), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2177PolyExtStep::AndEqz(683, 1465), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2178PolyExtStep::AndEqz(684, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2179PolyExtStep::Mul(1461, 823), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2180PolyExtStep::Sub(1466, 821), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2181PolyExtStep::AndEqz(685, 1467), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2182PolyExtStep::Mul(820, 1461), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2183PolyExtStep::AndEqz(686, 1468), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2184PolyExtStep::Mul(820, 823), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2185PolyExtStep::AndEqz(687, 1469), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2186PolyExtStep::Mul(814, 820), // loc(callsite( builtin Mul at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :114:27) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2187PolyExtStep::Sub(1470, 826), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :114:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2188PolyExtStep::AndEqz(688, 1471), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :114:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2189PolyExtStep::AndEqz(689, 807), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2190PolyExtStep::AndEqz(690, 808), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2191PolyExtStep::AndEqz(691, 809), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2192PolyExtStep::AndEqz(692, 810), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2193PolyExtStep::AndEqz(693, 811), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2194PolyExtStep::AndCond(678, 392, 694), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2195PolyExtStep::Sub(726, 1), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :165:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2196PolyExtStep::AndEqz(679, 1472), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :165:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2197PolyExtStep::AndEqz(696, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2198PolyExtStep::AndEqz(697, 1463), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2199PolyExtStep::AndEqz(698, 1464), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2200PolyExtStep::AndEqz(699, 1465), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2201PolyExtStep::AndEqz(700, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2202PolyExtStep::AndEqz(701, 1467), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2203PolyExtStep::AndEqz(702, 1468), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2204PolyExtStep::AndEqz(703, 1469), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2205PolyExtStep::AndEqz(704, 1471), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :114:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2206PolyExtStep::AndEqz(705, 807), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2207PolyExtStep::AndEqz(706, 808), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2208PolyExtStep::AndEqz(707, 809), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2209PolyExtStep::AndEqz(708, 810), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2210PolyExtStep::AndEqz(709, 811), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2211PolyExtStep::AndCond(695, 395, 710), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2212PolyExtStep::AndEqz(679, 813), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :171:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2213PolyExtStep::AndEqz(712, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2214PolyExtStep::AndEqz(713, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2215PolyExtStep::AndEqz(714, 1141), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2216PolyExtStep::AndEqz(715, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2217PolyExtStep::AndEqz(716, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2218PolyExtStep::AndEqz(717, 1147), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2219PolyExtStep::AndEqz(718, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2220PolyExtStep::AndEqz(719, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2221PolyExtStep::AndEqz(720, 1153), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2222PolyExtStep::AndEqz(721, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2223PolyExtStep::AndEqz(722, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2224PolyExtStep::AndEqz(723, 1159), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2225PolyExtStep::AndEqz(724, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2226PolyExtStep::AndEqz(725, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2227PolyExtStep::AndEqz(726, 1165), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2228PolyExtStep::AndEqz(727, 1171), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:19) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2229PolyExtStep::AndEqz(728, 1176), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:30) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2230PolyExtStep::AndCond(711, 398, 729), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2231PolyExtStep::Sub(1269, 1260), // loc(callsite( builtin Sub at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :165:21) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2232PolyExtStep::Mul(1473, 377), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2233PolyExtStep::Sub(1269, 1259), // loc(callsite( builtin Sub at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :160:21) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2234PolyExtStep::Mul(1475, 380), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2235PolyExtStep::Mul(1259, 383), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2236PolyExtStep::Mul(1188, 386), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2237PolyExtStep::Mul(1267, 389), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2238PolyExtStep::Add(1474, 1476), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2239PolyExtStep::Add(1480, 1477), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2240PolyExtStep::Add(1481, 1478), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2241PolyExtStep::Add(1482, 1479), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2242PolyExtStep::Sub(1365, 1359), // loc(callsite( builtin Sub at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :165:52) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2243PolyExtStep::Mul(1484, 377), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2244PolyExtStep::Sub(1365, 1358), // loc(callsite( builtin Sub at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :160:50) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2245PolyExtStep::Mul(1486, 380), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2246PolyExtStep::Mul(1358, 383), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2247PolyExtStep::Add(1485, 1487), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2248PolyExtStep::Add(1489, 1488), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2249PolyExtStep::Add(368, 1450), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :84:12) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :161:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2250PolyExtStep::Mul(1186, 1491), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :161:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2251PolyExtStep::Sub(1, 1186), // loc(callsite( builtin Sub at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:24) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :161:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2252PolyExtStep::Mul(1493, 507), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:32) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :161:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2253PolyExtStep::Add(1492, 1494), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :161:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2254PolyExtStep::Mul(1495, 392), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2255PolyExtStep::Mul(1493, 1491), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :167:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2256PolyExtStep::Sub(1, 1493), // loc(callsite( builtin Sub at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:24) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :167:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2257PolyExtStep::Mul(1498, 507), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:32) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :167:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2258PolyExtStep::Add(1497, 1499), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :167:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2259PolyExtStep::Mul(1500, 395), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2260PolyExtStep::Mul(1188, 1491), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :173:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2261PolyExtStep::Sub(1, 1188), // loc(callsite( builtin Sub at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:24) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :173:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2262PolyExtStep::Mul(1503, 507), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:32) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :173:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2263PolyExtStep::Add(1502, 1504), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :173:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2264PolyExtStep::Mul(1505, 398), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2265PolyExtStep::Add(519, 1496), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2266PolyExtStep::Add(1507, 1501), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2267PolyExtStep::Add(1508, 1506), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2268PolyExtStep::Add(370, 731), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :84:12) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :161:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2269PolyExtStep::Mul(1186, 1510), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :161:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2270PolyExtStep::Mul(1493, 370), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:33) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :161:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2271PolyExtStep::Add(1511, 1512), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :161:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2272PolyExtStep::Mul(1513, 392), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2273PolyExtStep::Mul(1493, 1510), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :167:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2274PolyExtStep::Mul(1498, 370), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:33) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :167:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2275PolyExtStep::Add(1515, 1516), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :167:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2276PolyExtStep::Mul(1517, 395), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2277PolyExtStep::Mul(1188, 1510), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :173:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2278PolyExtStep::Mul(1503, 370), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:33) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :173:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2279PolyExtStep::Add(1519, 1520), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :173:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2280PolyExtStep::Mul(1521, 398), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2281PolyExtStep::Add(534, 1514), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2282PolyExtStep::Add(1523, 1518), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2283PolyExtStep::Add(1524, 1522), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2284PolyExtStep::AndEqz(730, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2285PolyExtStep::AndEqz(731, 1377), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2286PolyExtStep::Sub(1483, 1379), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2287PolyExtStep::AndEqz(732, 1526), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2288PolyExtStep::Add(1490, 1375), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2289PolyExtStep::AndEqz(733, 1384), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2290PolyExtStep::AndEqz(734, 1387), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2291PolyExtStep::Sub(1527, 1389), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2292PolyExtStep::AndEqz(735, 1528), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2293PolyExtStep::AndEqz(736, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2294PolyExtStep::AndEqz(737, 1396), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2295PolyExtStep::Sub(1509, 1398), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2296PolyExtStep::AndEqz(738, 1529), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2297PolyExtStep::Add(1525, 1394), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2298PolyExtStep::AndEqz(739, 1403), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2299PolyExtStep::AndEqz(740, 1406), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2300PolyExtStep::Sub(1530, 1408), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2301PolyExtStep::AndEqz(741, 1531), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2302PolyExtStep::AndEqz(742, 1413), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2303PolyExtStep::AndEqz(743, 1415), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2304PolyExtStep::AndEqz(744, 1416), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2305PolyExtStep::AndEqz(745, 1417), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2306PolyExtStep::Mul(1412, 404), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :72:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2307PolyExtStep::Mul(1532, 718), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:11) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2308PolyExtStep::Sub(1, 1532), // loc(callsite( builtin Sub at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:90) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2309PolyExtStep::Mul(1534, 19), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:102) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2310PolyExtStep::Add(506, 1535), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:85) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2311PolyExtStep::Add(1536, 1533), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:106) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2312PolyExtStep::Sub(1537, 1424), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2313PolyExtStep::AndEqz(746, 1538), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2314PolyExtStep::AndEqz(747, 1433), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2315PolyExtStep::AndEqz(748, 1434), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2316PolyExtStep::AndEqz(749, 1435), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2317PolyExtStep::AndEqz(750, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2318PolyExtStep::AndEqz(751, 1436), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2319PolyExtStep::AndEqz(752, 1441), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2320PolyExtStep::AndEqz(753, 1442), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2321PolyExtStep::AndEqz(754, 1443), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2322PolyExtStep::AndEqz(755, 1444), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2323PolyExtStep::AndCond(423, 425, 756), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
2324PolyExtStep::Add(386, 389), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2325PolyExtStep::Add(1539, 392), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2326PolyExtStep::Add(1540, 395), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2327PolyExtStep::Add(511, 512), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2328PolyExtStep::Add(526, 527), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2329PolyExtStep::Mul(368, 398), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2330PolyExtStep::Mul(726, 22), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2331PolyExtStep::Add(694, 1545), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2332PolyExtStep::Mul(629, 27), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2333PolyExtStep::Add(1546, 1547), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:33) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2334PolyExtStep::Add(1548, 1447), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:51) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2335PolyExtStep::Add(1549, 711), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:70) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2336PolyExtStep::Add(1550, 712), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:85) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2337PolyExtStep::Mul(591, 40), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :72:7) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2338PolyExtStep::Add(1552, 690), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :72:17) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2339PolyExtStep::Add(1553, 639), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :72:36) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2340PolyExtStep::Sub(726, 4), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2341PolyExtStep::AndEqz(679, 1555), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2342PolyExtStep::AndEqz(758, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2343PolyExtStep::AndEqz(759, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2344PolyExtStep::AndEqz(760, 1141), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2345PolyExtStep::AndEqz(761, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2346PolyExtStep::AndEqz(762, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2347PolyExtStep::AndEqz(763, 1147), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2348PolyExtStep::AndEqz(764, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2349PolyExtStep::AndEqz(765, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2350PolyExtStep::AndEqz(766, 1153), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2351PolyExtStep::AndEqz(767, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2352PolyExtStep::AndEqz(768, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2353PolyExtStep::AndEqz(769, 1159), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2354PolyExtStep::AndEqz(770, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2355PolyExtStep::AndEqz(771, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2356PolyExtStep::AndEqz(772, 1165), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2357PolyExtStep::AndEqz(773, 1171), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:19) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2358PolyExtStep::AndEqz(774, 1176), // loc(callsite( Reg ( <preamble> :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:30) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2359PolyExtStep::AndCond(112, 377, 775), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2360PolyExtStep::AndEqz(679, 1130), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :183:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2361PolyExtStep::AndEqz(777, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :184:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2362PolyExtStep::AndEqz(778, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :184:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2363PolyExtStep::AndEqz(779, 1141), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :184:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2364PolyExtStep::AndEqz(780, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :184:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2365PolyExtStep::AndEqz(781, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :184:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2366PolyExtStep::AndEqz(782, 1147), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :184:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2367PolyExtStep::AndEqz(783, 809), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2368PolyExtStep::AndEqz(784, 810), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2369PolyExtStep::AndEqz(785, 811), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2370PolyExtStep::AndCond(776, 380, 786), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2371PolyExtStep::AndEqz(679, 1131), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :189:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2372PolyExtStep::AndEqz(788, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :190:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2373PolyExtStep::AndEqz(789, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :190:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2374PolyExtStep::AndEqz(790, 1141), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :190:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2375PolyExtStep::AndEqz(791, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :190:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2376PolyExtStep::AndEqz(792, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :190:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2377PolyExtStep::AndEqz(793, 1147), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :190:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2378PolyExtStep::AndEqz(794, 809), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2379PolyExtStep::AndEqz(795, 810), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2380PolyExtStep::AndEqz(796, 811), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2381PolyExtStep::AndCond(787, 383, 797), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2382PolyExtStep::Sub(676, 41), // loc(callsite( VerifyOpcode ( zirgen/circuit/rv32im/v2/dsl/inst.zir :91:19) at callsite( OpJAL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :195:16) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :68:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2383PolyExtStep::AndEqz(0, 1556), // loc(callsite( VerifyOpcode ( zirgen/circuit/rv32im/v2/dsl/inst.zir :91:19) at callsite( OpJAL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :195:16) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :68:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2384PolyExtStep::AndEqz(799, 807), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2385PolyExtStep::AndEqz(800, 808), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2386PolyExtStep::AndEqz(801, 809), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2387PolyExtStep::AndEqz(802, 810), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2388PolyExtStep::AndEqz(803, 811), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2389PolyExtStep::AndCond(798, 386, 804), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2390PolyExtStep::Sub(676, 42), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpJALR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :202:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :69:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2391PolyExtStep::AndEqz(0, 1557), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpJALR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :202:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :69:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2392PolyExtStep::AndEqz(806, 726), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpJALR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :202:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :69:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2393PolyExtStep::AndEqz(807, 807), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2394PolyExtStep::AndEqz(808, 808), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2395PolyExtStep::AndEqz(809, 809), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2396PolyExtStep::AndEqz(810, 810), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2397PolyExtStep::AndEqz(811, 811), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2398PolyExtStep::AndCond(805, 389, 812), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2399PolyExtStep::Sub(676, 43), // loc(callsite( VerifyOpcode ( zirgen/circuit/rv32im/v2/dsl/inst.zir :91:19) at callsite( OpLUI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :209:16) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :70:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2400PolyExtStep::AndEqz(0, 1558), // loc(callsite( VerifyOpcode ( zirgen/circuit/rv32im/v2/dsl/inst.zir :91:19) at callsite( OpLUI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :209:16) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :70:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2401PolyExtStep::AndEqz(814, 807), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2402PolyExtStep::AndEqz(815, 808), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2403PolyExtStep::AndEqz(816, 809), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2404PolyExtStep::AndEqz(817, 810), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2405PolyExtStep::AndEqz(818, 811), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2406PolyExtStep::AndCond(813, 392, 819), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2407PolyExtStep::Sub(676, 44), // loc(callsite( VerifyOpcode ( zirgen/circuit/rv32im/v2/dsl/inst.zir :91:19) at callsite( OpAUIPC ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :214:16) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2408PolyExtStep::AndEqz(0, 1559), // loc(callsite( VerifyOpcode ( zirgen/circuit/rv32im/v2/dsl/inst.zir :91:19) at callsite( OpAUIPC ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :214:16) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2409PolyExtStep::AndEqz(821, 807), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2410PolyExtStep::AndEqz(822, 808), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2411PolyExtStep::AndEqz(823, 809), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2412PolyExtStep::AndEqz(824, 810), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2413PolyExtStep::AndEqz(825, 811), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2414PolyExtStep::AndCond(820, 395, 826), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2415PolyExtStep::Sub(676, 45), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpECALL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :220:20) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2416PolyExtStep::AndEqz(0, 1560), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpECALL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :220:20) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2417PolyExtStep::AndEqz(828, 726), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpECALL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :220:20) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2418PolyExtStep::AndEqz(829, 724), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpECALL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :220:20) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2419PolyExtStep::AndEqz(830, 807), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2420PolyExtStep::AndEqz(831, 808), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2421PolyExtStep::AndEqz(832, 809), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2422PolyExtStep::AndEqz(833, 810), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2423PolyExtStep::AndEqz(834, 811), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2424PolyExtStep::AndCond(827, 398, 835), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2425PolyExtStep::Mul(698, 392), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2426PolyExtStep::Add(368, 698), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( OpAUIPC ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :215:26) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2427PolyExtStep::Mul(1562, 395), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2428PolyExtStep::Add(1542, 1561), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2429PolyExtStep::Add(1564, 1563), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2430PolyExtStep::Mul(578, 392), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2431PolyExtStep::Add(370, 578), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( OpAUIPC ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :215:26) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2432PolyExtStep::Mul(1567, 395), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2433PolyExtStep::Add(1543, 1566), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2434PolyExtStep::Add(1569, 1568), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2435PolyExtStep::Mul(1503, 1491), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :179:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2436PolyExtStep::Sub(1, 1503), // loc(callsite( builtin Sub at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:24) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :179:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2437PolyExtStep::Mul(1572, 507), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:32) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :179:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2438PolyExtStep::Add(1571, 1573), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :179:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2439PolyExtStep::Mul(1574, 377), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2440PolyExtStep::Mul(1267, 1491), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :185:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2441PolyExtStep::Sub(1, 1267), // loc(callsite( builtin Sub at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:24) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :185:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2442PolyExtStep::Mul(1577, 507), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:32) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :185:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2443PolyExtStep::Add(1576, 1578), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :185:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2444PolyExtStep::Mul(1579, 380), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2445PolyExtStep::Mul(1577, 1491), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :191:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2446PolyExtStep::Sub(1, 1577), // loc(callsite( builtin Sub at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:24) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :191:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2447PolyExtStep::Mul(1582, 507), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:32) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :191:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2448PolyExtStep::Add(1581, 1583), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :191:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2449PolyExtStep::Mul(1584, 383), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2450PolyExtStep::Add(368, 1551), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( OpJAL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :198:12) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :68:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2451PolyExtStep::Mul(1586, 386), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2452PolyExtStep::Mul(1269, 389), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2453PolyExtStep::Add(1575, 1580), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2454PolyExtStep::Add(1589, 1585), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2455PolyExtStep::Add(1590, 1587), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2456PolyExtStep::Add(1591, 1588), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2457PolyExtStep::Add(1592, 513), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2458PolyExtStep::Add(1593, 514), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2459PolyExtStep::Add(1594, 1544), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2460PolyExtStep::Mul(1503, 1510), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :179:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2461PolyExtStep::Mul(1572, 370), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:33) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :179:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2462PolyExtStep::Add(1596, 1597), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :179:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2463PolyExtStep::Mul(1598, 377), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2464PolyExtStep::Mul(1267, 1510), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :185:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2465PolyExtStep::Mul(1577, 370), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:33) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :185:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2466PolyExtStep::Add(1600, 1601), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :185:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2467PolyExtStep::Mul(1602, 380), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2468PolyExtStep::Mul(1577, 1510), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :191:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2469PolyExtStep::Mul(1582, 370), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:33) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :191:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2470PolyExtStep::Add(1604, 1605), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :191:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2471PolyExtStep::Mul(1606, 383), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2472PolyExtStep::Add(370, 1554), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( OpJAL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :198:12) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :68:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2473PolyExtStep::Mul(1608, 386), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2474PolyExtStep::Mul(1365, 389), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2475PolyExtStep::Add(1599, 1603), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2476PolyExtStep::Add(1611, 1607), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2477PolyExtStep::Add(1612, 1609), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2478PolyExtStep::Add(1613, 1610), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2479PolyExtStep::Add(1614, 528), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2480PolyExtStep::Add(1615, 529), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2481PolyExtStep::Add(1616, 530), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2482PolyExtStep::AndEqz(836, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2483PolyExtStep::AndEqz(837, 1377), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2484PolyExtStep::Sub(1565, 1379), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2485PolyExtStep::AndEqz(838, 1618), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2486PolyExtStep::Add(1570, 1375), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2487PolyExtStep::AndEqz(839, 1384), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2488PolyExtStep::AndEqz(840, 1387), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2489PolyExtStep::Sub(1619, 1389), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2490PolyExtStep::AndEqz(841, 1620), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2491PolyExtStep::AndEqz(842, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2492PolyExtStep::AndEqz(843, 1396), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2493PolyExtStep::Sub(1595, 1398), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2494PolyExtStep::AndEqz(844, 1621), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2495PolyExtStep::Add(1617, 1394), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2496PolyExtStep::AndEqz(845, 1403), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2497PolyExtStep::AndEqz(846, 1406), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2498PolyExtStep::Sub(1622, 1408), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2499PolyExtStep::AndEqz(847, 1623), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2500PolyExtStep::AndEqz(848, 1413), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2501PolyExtStep::AndEqz(849, 1415), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2502PolyExtStep::AndEqz(850, 1416), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2503PolyExtStep::AndEqz(851, 1417), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2504PolyExtStep::Mul(1412, 1541), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :72:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2505PolyExtStep::Mul(1624, 718), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:11) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2506PolyExtStep::Sub(1, 1624), // loc(callsite( builtin Sub at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:90) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2507PolyExtStep::Mul(1626, 19), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:102) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2508PolyExtStep::Add(506, 1627), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:85) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2509PolyExtStep::Add(1628, 1625), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:106) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2510PolyExtStep::Sub(1629, 1424), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2511PolyExtStep::AndEqz(852, 1630), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2512PolyExtStep::AndEqz(853, 1433), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2513PolyExtStep::AndEqz(854, 1434), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2514PolyExtStep::AndEqz(855, 1435), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2515PolyExtStep::AndEqz(856, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2516PolyExtStep::AndEqz(857, 1436), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2517PolyExtStep::AndEqz(858, 1441), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2518PolyExtStep::AndEqz(859, 1442), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2519PolyExtStep::AndEqz(860, 1443), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2520PolyExtStep::AndEqz(861, 1444), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2521PolyExtStep::AndCond(757, 428, 862), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
2522PolyExtStep::Sub(539, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
2523PolyExtStep::AndEqz(0, 1631), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
2524PolyExtStep::Sub(594, 542), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
2525PolyExtStep::AndEqz(864, 1632), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
2526PolyExtStep::AndEqz(865, 497), // loc(callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :8:21) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
2527PolyExtStep::Sub(1, 552), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2528PolyExtStep::Mul(552, 1633), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2529PolyExtStep::Sub(7, 552), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2530PolyExtStep::Mul(1634, 1635), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2531PolyExtStep::Sub(6, 552), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2532PolyExtStep::Mul(1636, 1637), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2533PolyExtStep::AndEqz(866, 1638), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2534PolyExtStep::Sub(555, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2535PolyExtStep::AndEqz(867, 1639), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2536PolyExtStep::Sub(556, 502), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2537PolyExtStep::AndEqz(868, 1640), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2538PolyExtStep::Sub(1, 563), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2539PolyExtStep::Mul(563, 1641), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2540PolyExtStep::AndEqz(869, 1642), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2541PolyExtStep::Mul(370, 564), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2542PolyExtStep::Sub(1643, 1641), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2543PolyExtStep::AndEqz(870, 1644), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2544PolyExtStep::Mul(563, 370), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2545PolyExtStep::AndEqz(871, 1645), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2546PolyExtStep::Mul(563, 564), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2547PolyExtStep::AndEqz(872, 1646), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2548PolyExtStep::AndEqz(873, 563), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:19) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2549PolyExtStep::Sub(571, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2550PolyExtStep::AndEqz(874, 1647), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2551PolyExtStep::Mul(570, 5), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:4) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2552PolyExtStep::Add(1648, 552), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:12) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2553PolyExtStep::Sub(1649, 368), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2554PolyExtStep::AndEqz(875, 1650), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2555PolyExtStep::Add(503, 570), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :73:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2556PolyExtStep::AndEqz(876, 552), // loc(callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :29:17) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2557PolyExtStep::Sub(573, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2558PolyExtStep::AndEqz(877, 1652), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2559PolyExtStep::Sub(577, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2560PolyExtStep::AndEqz(878, 1653), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2561PolyExtStep::Sub(578, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2562PolyExtStep::AndEqz(879, 1654), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2563PolyExtStep::AndEqz(880, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2564PolyExtStep::Sub(572, 1651), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2565PolyExtStep::AndEqz(881, 1655), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2566PolyExtStep::Sub(575, 587), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2567PolyExtStep::AndEqz(882, 1656), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2568PolyExtStep::Sub(576, 588), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2569PolyExtStep::AndEqz(883, 1657), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2570PolyExtStep::Sub(578, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2571PolyExtStep::Sub(1658, 574), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2572PolyExtStep::Sub(739, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2573PolyExtStep::AndEqz(884, 1660), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2574PolyExtStep::Sub(740, 1659), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2575PolyExtStep::AndEqz(885, 1661), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2576PolyExtStep::AndEqz(886, 603), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2577PolyExtStep::AndEqz(887, 614), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2578PolyExtStep::AndEqz(888, 621), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2579PolyExtStep::AndEqz(889, 628), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2580PolyExtStep::Sub(7, 629), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2581PolyExtStep::Mul(631, 1662), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2582PolyExtStep::Sub(6, 629), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2583PolyExtStep::Mul(1663, 1664), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2584PolyExtStep::AndEqz(890, 1665), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2585PolyExtStep::AndEqz(891, 638), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2586PolyExtStep::AndEqz(892, 641), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2587PolyExtStep::Sub(7, 646), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2588PolyExtStep::Mul(648, 1666), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2589PolyExtStep::Sub(6, 646), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2590PolyExtStep::Mul(1667, 1668), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2591PolyExtStep::AndEqz(893, 1669), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2592PolyExtStep::Sub(7, 649), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2593PolyExtStep::Mul(651, 1670), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2594PolyExtStep::Sub(6, 649), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2595PolyExtStep::Mul(1671, 1672), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2596PolyExtStep::AndEqz(894, 1673), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2597PolyExtStep::AndEqz(895, 654), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2598PolyExtStep::AndEqz(896, 661), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2599PolyExtStep::AndEqz(897, 672), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2600PolyExtStep::Sub(7, 673), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2601PolyExtStep::Mul(675, 1674), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2602PolyExtStep::Sub(6, 673), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2603PolyExtStep::Mul(1675, 1676), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2604PolyExtStep::AndEqz(898, 1677), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2605PolyExtStep::Sub(1, 676), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2606PolyExtStep::Mul(676, 1678), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2607PolyExtStep::Sub(7, 676), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2608PolyExtStep::Mul(1679, 1680), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2609PolyExtStep::Sub(6, 676), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2610PolyExtStep::Mul(1681, 1682), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2611PolyExtStep::AndEqz(899, 1683), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2612PolyExtStep::AndEqz(900, 546), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2613PolyExtStep::Mul(601, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2614PolyExtStep::Mul(608, 28), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2615PolyExtStep::Add(1684, 1685), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2616PolyExtStep::Mul(615, 27), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2617PolyExtStep::Add(1686, 1687), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2618PolyExtStep::Mul(622, 26), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2619PolyExtStep::Add(1688, 1689), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2620PolyExtStep::Mul(629, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2621PolyExtStep::Add(1690, 1691), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2622PolyExtStep::Mul(632, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2623PolyExtStep::Add(1692, 1693), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2624PolyExtStep::Mul(639, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2625PolyExtStep::Add(1694, 1695), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2626PolyExtStep::Mul(646, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2627PolyExtStep::Add(1696, 1697), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2628PolyExtStep::Add(1698, 649), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2629PolyExtStep::Sub(588, 1699), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2630PolyExtStep::AndEqz(901, 1700), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2631PolyExtStep::Mul(652, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2632PolyExtStep::Mul(659, 14), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2633PolyExtStep::Add(1701, 1702), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2634PolyExtStep::Mul(666, 22), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2635PolyExtStep::Add(1703, 1704), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2636PolyExtStep::Mul(673, 21), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2637PolyExtStep::Add(1705, 1706), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2638PolyExtStep::Mul(676, 20), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2639PolyExtStep::Add(1707, 1708), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2640PolyExtStep::Mul(544, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2641PolyExtStep::Add(1709, 1710), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2642PolyExtStep::Add(1711, 551), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2643PolyExtStep::Sub(587, 1712), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2644PolyExtStep::AndEqz(902, 1713), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2645PolyExtStep::Mul(646, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2646PolyExtStep::Mul(649, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2647PolyExtStep::Add(1714, 1715), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2648PolyExtStep::Add(1716, 652), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2649PolyExtStep::Mul(629, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2650PolyExtStep::Mul(632, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2651PolyExtStep::Add(1718, 1719), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2652PolyExtStep::Add(1720, 639), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2653PolyExtStep::Mul(673, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:17) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2654PolyExtStep::Mul(676, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:30) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2655PolyExtStep::Add(1722, 1723), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2656PolyExtStep::Add(1724, 544), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:39) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2657PolyExtStep::Mul(608, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2658PolyExtStep::Mul(615, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:38) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2659PolyExtStep::Add(1726, 1727), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2660PolyExtStep::Add(1728, 622), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:47) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2661PolyExtStep::Mul(601, 19), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2662PolyExtStep::Add(1730, 1729), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2663PolyExtStep::Mul(659, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2664PolyExtStep::Add(1732, 666), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2665PolyExtStep::Sub(1, 764), // loc(callsite( builtin Sub at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :49:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2666PolyExtStep::Mul(764, 1734), // loc(callsite( builtin Mul at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :49:4) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2667PolyExtStep::AndEqz(903, 1735), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :49:36) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2668PolyExtStep::Sub(1717, 1721), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :52:18) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2669PolyExtStep::Add(506, 1717), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2670PolyExtStep::AndEqz(0, 1736), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :52:18) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2671PolyExtStep::Sub(1737, 798), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2672PolyExtStep::AndEqz(905, 1738), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2673PolyExtStep::Sub(741, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2674PolyExtStep::AndEqz(906, 1739), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2675PolyExtStep::Sub(746, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2676PolyExtStep::AndEqz(907, 1740), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2677PolyExtStep::Sub(747, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2678PolyExtStep::AndEqz(908, 1741), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2679PolyExtStep::AndEqz(909, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2680PolyExtStep::Sub(742, 798), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2681PolyExtStep::AndEqz(910, 1742), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2682PolyExtStep::Sub(744, 760), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2683PolyExtStep::AndEqz(911, 1743), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2684PolyExtStep::Sub(745, 766), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2685PolyExtStep::AndEqz(912, 1744), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2686PolyExtStep::Sub(747, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2687PolyExtStep::Sub(1745, 743), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2688PolyExtStep::AndEqz(913, 782), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2689PolyExtStep::Sub(781, 1746), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2690PolyExtStep::AndEqz(914, 1747), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2691PolyExtStep::AndEqz(915, 767), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2692PolyExtStep::AndEqz(916, 771), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2693PolyExtStep::AndEqz(917, 732), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2694PolyExtStep::AndCond(904, 764, 918), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2695PolyExtStep::Add(506, 1721), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2696PolyExtStep::AndEqz(0, 1738), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2697PolyExtStep::AndEqz(920, 1739), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2698PolyExtStep::AndEqz(921, 1740), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2699PolyExtStep::AndEqz(922, 1741), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2700PolyExtStep::AndEqz(923, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2701PolyExtStep::AndEqz(924, 1742), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2702PolyExtStep::AndEqz(925, 1743), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2703PolyExtStep::AndEqz(926, 1744), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2704PolyExtStep::AndEqz(927, 782), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2705PolyExtStep::AndEqz(928, 1747), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2706PolyExtStep::Sub(1748, 800), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2707PolyExtStep::AndEqz(929, 1749), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2708PolyExtStep::Sub(767, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2709PolyExtStep::AndEqz(930, 1750), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2710PolyExtStep::Sub(771, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2711PolyExtStep::AndEqz(931, 1751), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2712PolyExtStep::Sub(772, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2713PolyExtStep::AndEqz(932, 1752), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2714PolyExtStep::AndEqz(933, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2715PolyExtStep::Sub(768, 800), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2716PolyExtStep::AndEqz(934, 1753), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2717PolyExtStep::Sub(761, 756), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2718PolyExtStep::AndEqz(935, 1754), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2719PolyExtStep::Sub(770, 757), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2720PolyExtStep::AndEqz(936, 1755), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2721PolyExtStep::Sub(772, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2722PolyExtStep::Sub(1756, 769), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2723PolyExtStep::Sub(732, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2724PolyExtStep::AndEqz(937, 1758), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2725PolyExtStep::Sub(737, 1757), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2726PolyExtStep::AndEqz(938, 1759), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2727PolyExtStep::AndCond(919, 1734, 939), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2728PolyExtStep::Get(611), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2729PolyExtStep::Mul(1760, 764), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2730PolyExtStep::Mul(1760, 1734), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2731PolyExtStep::Add(1761, 1762), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2732PolyExtStep::Get(616), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2733PolyExtStep::Mul(1764, 764), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2734PolyExtStep::Mul(1764, 1734), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2735PolyExtStep::Add(1765, 1766), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2736PolyExtStep::Get(656), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2737PolyExtStep::Mul(1768, 1734), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2738PolyExtStep::Add(1761, 1769), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2739PolyExtStep::Get(661), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2740PolyExtStep::Mul(1771, 1734), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2741PolyExtStep::Add(1765, 1772), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2742PolyExtStep::Sub(1763, 802), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:17) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2743PolyExtStep::AndEqz(940, 1774), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:17) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2744PolyExtStep::Sub(1767, 804), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :63:17) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2745PolyExtStep::AndEqz(941, 1775), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :63:17) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2746PolyExtStep::Sub(1770, 814), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :64:17) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2747PolyExtStep::AndEqz(942, 1776), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :64:17) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2748PolyExtStep::Sub(1773, 817), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :65:18) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2749PolyExtStep::AndEqz(943, 1777), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :65:18) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2750PolyExtStep::Sub(551, 32), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2751PolyExtStep::Sub(1733, 1), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2752PolyExtStep::AndEqz(0, 1778), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2753PolyExtStep::AndEqz(945, 1779), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2754PolyExtStep::AndEqz(946, 1731), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2755PolyExtStep::AndEqz(947, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2756PolyExtStep::AndEqz(948, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2757PolyExtStep::AndEqz(949, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2758PolyExtStep::AndEqz(950, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2759PolyExtStep::AndEqz(951, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2760PolyExtStep::Mul(823, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2761PolyExtStep::Mul(826, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2762PolyExtStep::Mul(829, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2763PolyExtStep::Mul(832, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2764PolyExtStep::Add(820, 1780), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2765PolyExtStep::Add(1784, 1781), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2766PolyExtStep::Add(1785, 1782), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2767PolyExtStep::Add(1786, 1783), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2768PolyExtStep::AndEqz(952, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :40:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2769PolyExtStep::Mul(1137, 24), // loc(callsite( builtin Mul at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:4) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2770PolyExtStep::Add(1788, 1787), // loc(callsite( builtin Add at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:16) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2771PolyExtStep::Sub(1789, 814), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2772PolyExtStep::AndEqz(953, 1790), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2773PolyExtStep::Mul(820, 7), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :42:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2774PolyExtStep::Add(1791, 821), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :42:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2775PolyExtStep::Mul(823, 1792), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2776PolyExtStep::Mul(1793, 5), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2777PolyExtStep::Mul(824, 1792), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2778PolyExtStep::Add(1794, 1795), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2779PolyExtStep::Mul(826, 1796), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2780PolyExtStep::Mul(1797, 23), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2781PolyExtStep::Mul(827, 1796), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2782PolyExtStep::Add(1798, 1799), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2783PolyExtStep::Sub(1800, 835), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2784PolyExtStep::AndEqz(954, 1801), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2785PolyExtStep::Mul(829, 835), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2786PolyExtStep::Mul(1802, 20), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2787PolyExtStep::Mul(830, 835), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2788PolyExtStep::Add(1803, 1804), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2789PolyExtStep::Mul(833, 1805), // loc(callsite( builtin Mul at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2790PolyExtStep::Sub(1806, 838), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2791PolyExtStep::AndEqz(955, 1807), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2792PolyExtStep::Mul(832, 1805), // loc(callsite( builtin Mul at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:22) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2793PolyExtStep::Sub(1808, 841), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2794PolyExtStep::AndEqz(956, 1809), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2795PolyExtStep::Sub(1375, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2796PolyExtStep::AndEqz(957, 1810), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2797PolyExtStep::Sub(1383, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2798PolyExtStep::AndEqz(958, 1811), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2799PolyExtStep::AndEqz(959, 1393), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2800PolyExtStep::Sub(1394, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2801PolyExtStep::AndEqz(960, 1812), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2802PolyExtStep::Sub(1402, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2803PolyExtStep::AndEqz(961, 1813), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2804PolyExtStep::AndEqz(962, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2805PolyExtStep::Mul(1385, 20), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:17) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2806PolyExtStep::Add(1382, 1814), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:12) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2807PolyExtStep::Sub(802, 1815), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2808PolyExtStep::AndEqz(963, 1816), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2809PolyExtStep::Mul(1404, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:18) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2810PolyExtStep::Add(1392, 1817), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2811PolyExtStep::Mul(844, 29), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:40) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2812PolyExtStep::Add(1818, 1819), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2813PolyExtStep::Sub(804, 1820), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2814PolyExtStep::AndEqz(964, 1821), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2815PolyExtStep::Mul(1404, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:9) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2816PolyExtStep::Mul(844, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2817PolyExtStep::Add(1822, 1823), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2818PolyExtStep::Sub(1401, 1824), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2819PolyExtStep::AndEqz(965, 1825), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2820PolyExtStep::Sub(1410, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2821PolyExtStep::AndEqz(966, 1826), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2822PolyExtStep::Sub(1424, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2823PolyExtStep::AndEqz(967, 1827), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2824PolyExtStep::Sub(1426, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2825PolyExtStep::AndEqz(968, 1828), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2826PolyExtStep::Get(293), // loc(callsite( builtin NondetReg at callsite( ArgU8 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :9:29) at callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :18:16) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2827PolyExtStep::Get(299), // loc(callsite( builtin NondetReg at callsite( ArgU8 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :10:27) at callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :18:16) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2828PolyExtStep::Sub(1829, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2829PolyExtStep::AndEqz(969, 1831), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2830PolyExtStep::AndEqz(970, 1434), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2831PolyExtStep::AndEqz(971, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2832PolyExtStep::Mul(1427, 20), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:17) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2833PolyExtStep::Add(1411, 1832), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:12) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2834PolyExtStep::Sub(838, 1833), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2835PolyExtStep::AndEqz(972, 1834), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2836PolyExtStep::Mul(1430, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:18) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2837PolyExtStep::Add(1428, 1835), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2838PolyExtStep::Mul(847, 29), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:40) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2839PolyExtStep::Add(1836, 1837), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2840PolyExtStep::Sub(841, 1838), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2841PolyExtStep::AndEqz(973, 1839), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2842PolyExtStep::Mul(1430, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:9) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2843PolyExtStep::Mul(847, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2844PolyExtStep::Add(1840, 1841), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2845PolyExtStep::Sub(1830, 1842), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2846PolyExtStep::AndEqz(974, 1843), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2847PolyExtStep::AndEqz(975, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2848PolyExtStep::AndEqz(976, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2849PolyExtStep::Mul(850, 29), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:13) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2850PolyExtStep::Mul(1143, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:30) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2851PolyExtStep::Add(1844, 1845), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:21) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2852PolyExtStep::Sub(0, 1846), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2853PolyExtStep::AndEqz(977, 1847), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2854PolyExtStep::Mul(1382, 1411), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :128:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2855PolyExtStep::Mul(1382, 1427), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2856PolyExtStep::Mul(1385, 1411), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:36) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2857PolyExtStep::Add(1849, 1850), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2858PolyExtStep::Mul(1851, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:8) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2859PolyExtStep::Add(1848, 1852), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :128:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2860PolyExtStep::AndEqz(978, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2861PolyExtStep::Sub(1431, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2862PolyExtStep::AndEqz(979, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2863PolyExtStep::AndEqz(980, 855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2864PolyExtStep::AndEqz(981, 858), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2865PolyExtStep::Mul(856, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2866PolyExtStep::Add(1855, 853), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2867PolyExtStep::Mul(1856, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2868PolyExtStep::Mul(1432, 33), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2869PolyExtStep::Add(1857, 1858), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2870PolyExtStep::Add(1859, 1148), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2871PolyExtStep::Sub(1853, 1860), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2872PolyExtStep::AndEqz(982, 1861), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2873PolyExtStep::Mul(1856, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2874PolyExtStep::Add(1862, 1432), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2875PolyExtStep::Mul(1382, 1428), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2876PolyExtStep::Add(1863, 1864), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :134:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2877PolyExtStep::Mul(1385, 1427), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:27) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2878PolyExtStep::Add(1865, 1866), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2879PolyExtStep::Mul(1392, 1411), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:43) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2880PolyExtStep::Add(1867, 1868), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:35) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2881PolyExtStep::Mul(1382, 1830), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2882PolyExtStep::Mul(1385, 1428), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:36) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2883PolyExtStep::Add(1870, 1871), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2884PolyExtStep::Mul(1392, 1427), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:52) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2885PolyExtStep::Add(1872, 1873), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:44) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2886PolyExtStep::Mul(1401, 1411), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:68) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2887PolyExtStep::Add(1874, 1875), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:60) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2888PolyExtStep::Mul(1876, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:8) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2889PolyExtStep::Add(1869, 1877), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:51) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2890PolyExtStep::AndEqz(983, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2891PolyExtStep::AndEqz(984, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2892PolyExtStep::AndEqz(985, 861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2893PolyExtStep::AndEqz(986, 895), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2894PolyExtStep::Mul(893, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2895PolyExtStep::Add(1879, 859), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2896PolyExtStep::Mul(1880, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2897PolyExtStep::Mul(1440, 33), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2898PolyExtStep::Add(1881, 1882), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2899PolyExtStep::Add(1883, 1154), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2900PolyExtStep::Sub(1878, 1884), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2901PolyExtStep::AndEqz(987, 1885), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2902PolyExtStep::Mul(1880, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2903PolyExtStep::Add(1886, 1440), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2904PolyExtStep::Add(1887, 47), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:42) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2905PolyExtStep::Mul(1385, 1830), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2906PolyExtStep::Add(1888, 1889), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2907PolyExtStep::Mul(1392, 1428), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:27) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2908PolyExtStep::Add(1890, 1891), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2909PolyExtStep::Mul(1401, 1427), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:43) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2910PolyExtStep::Add(1892, 1893), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2911PolyExtStep::Mul(1392, 1830), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2912PolyExtStep::Mul(1401, 1428), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:36) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2913PolyExtStep::Add(1895, 1896), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2914PolyExtStep::Mul(1897, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:8) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2915PolyExtStep::Add(1894, 1898), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2916PolyExtStep::AndEqz(988, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2917PolyExtStep::Get(341), // loc(callsite( builtin NondetReg at callsite( ArgU8 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :9:29) at callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :18:16) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2918PolyExtStep::Sub(1900, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2919PolyExtStep::AndEqz(989, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2920PolyExtStep::AndEqz(990, 898), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2921PolyExtStep::AndEqz(991, 901), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2922PolyExtStep::Mul(899, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2923PolyExtStep::Add(1902, 896), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2924PolyExtStep::Mul(1903, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2925PolyExtStep::Mul(538, 33), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2926PolyExtStep::Add(1904, 1905), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2927PolyExtStep::Add(1906, 1160), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2928PolyExtStep::Sub(1899, 1907), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2929PolyExtStep::AndEqz(992, 1908), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2930PolyExtStep::Mul(1903, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2931PolyExtStep::Add(1909, 538), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2932PolyExtStep::Add(1910, 46), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :151:42) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2933PolyExtStep::Mul(1401, 1830), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :153:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2934PolyExtStep::Add(1911, 1912), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2935PolyExtStep::AndEqz(993, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2936PolyExtStep::Sub(1913, 1373), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2937PolyExtStep::Mul(1914, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2938PolyExtStep::AndEqz(994, 904), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2939PolyExtStep::AndEqz(995, 907), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2940PolyExtStep::Mul(905, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2941PolyExtStep::Add(1916, 902), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2942PolyExtStep::Sub(1915, 1917), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2943PolyExtStep::AndEqz(996, 1918), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2944PolyExtStep::AndCond(944, 377, 997), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
2945PolyExtStep::Sub(551, 38), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :56:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2946PolyExtStep::AndEqz(0, 1919), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :56:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2947PolyExtStep::AndEqz(999, 1779), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :56:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2948PolyExtStep::AndEqz(1000, 1731), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :56:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2949PolyExtStep::AndEqz(1001, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2950PolyExtStep::AndEqz(1002, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2951PolyExtStep::AndEqz(1003, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2952PolyExtStep::AndEqz(1004, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2953PolyExtStep::AndEqz(1005, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2954PolyExtStep::AndEqz(1006, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :40:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2955PolyExtStep::Sub(1789, 1721), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2956PolyExtStep::AndEqz(1007, 1920), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
2957PolyExtStep::AndEqz(1008, 1801), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2958PolyExtStep::AndEqz(1009, 1807), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2959PolyExtStep::AndEqz(1010, 1809), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2960PolyExtStep::AndEqz(1011, 1810), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2961PolyExtStep::AndEqz(1012, 1811), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2962PolyExtStep::AndEqz(1013, 1393), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2963PolyExtStep::AndEqz(1014, 1812), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2964PolyExtStep::AndEqz(1015, 1813), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2965PolyExtStep::AndEqz(1016, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2966PolyExtStep::AndEqz(1017, 1816), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2967PolyExtStep::AndEqz(1018, 1821), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2968PolyExtStep::AndEqz(1019, 1825), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2969PolyExtStep::AndEqz(1020, 1826), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2970PolyExtStep::AndEqz(1021, 1827), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2971PolyExtStep::AndEqz(1022, 1828), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2972PolyExtStep::AndEqz(1023, 1831), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2973PolyExtStep::AndEqz(1024, 1434), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2974PolyExtStep::AndEqz(1025, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
2975PolyExtStep::AndEqz(1026, 1834), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2976PolyExtStep::AndEqz(1027, 1839), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2977PolyExtStep::AndEqz(1028, 1843), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2978PolyExtStep::AndEqz(1029, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2979PolyExtStep::AndEqz(1030, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2980PolyExtStep::AndEqz(1031, 1847), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
2981PolyExtStep::AndEqz(1032, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2982PolyExtStep::AndEqz(1033, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2983PolyExtStep::AndEqz(1034, 855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2984PolyExtStep::AndEqz(1035, 858), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2985PolyExtStep::AndEqz(1036, 1861), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2986PolyExtStep::AndEqz(1037, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2987PolyExtStep::AndEqz(1038, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2988PolyExtStep::AndEqz(1039, 861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2989PolyExtStep::AndEqz(1040, 895), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2990PolyExtStep::AndEqz(1041, 1885), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2991PolyExtStep::AndEqz(1042, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2992PolyExtStep::AndEqz(1043, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
2993PolyExtStep::AndEqz(1044, 898), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2994PolyExtStep::AndEqz(1045, 901), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2995PolyExtStep::AndEqz(1046, 1908), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2996PolyExtStep::AndEqz(1047, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
2997PolyExtStep::AndEqz(1048, 904), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2998PolyExtStep::AndEqz(1049, 907), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
2999PolyExtStep::AndEqz(1050, 1918), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3000PolyExtStep::AndCond(998, 380, 1051), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3001PolyExtStep::Sub(1731, 1), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3002PolyExtStep::AndEqz(945, 1733), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3003PolyExtStep::AndEqz(1053, 1921), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3004PolyExtStep::AndEqz(1054, 1810), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3005PolyExtStep::AndEqz(1055, 1811), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3006PolyExtStep::AndEqz(1056, 1393), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3007PolyExtStep::AndEqz(1057, 1812), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3008PolyExtStep::AndEqz(1058, 1813), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3009PolyExtStep::AndEqz(1059, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3010PolyExtStep::AndEqz(1060, 1816), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3011PolyExtStep::Add(1818, 1150), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3012PolyExtStep::Sub(804, 1922), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3013PolyExtStep::AndEqz(1061, 1923), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3014PolyExtStep::Mul(820, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3015PolyExtStep::Add(1822, 1924), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3016PolyExtStep::Sub(1401, 1925), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3017PolyExtStep::AndEqz(1062, 1926), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3018PolyExtStep::AndEqz(1063, 1826), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3019PolyExtStep::AndEqz(1064, 1827), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3020PolyExtStep::AndEqz(1065, 1828), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3021PolyExtStep::AndEqz(1066, 1831), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3022PolyExtStep::AndEqz(1067, 1434), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3023PolyExtStep::AndEqz(1068, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3024PolyExtStep::Sub(814, 1833), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3025PolyExtStep::AndEqz(1069, 1927), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3026PolyExtStep::Add(1836, 1156), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3027PolyExtStep::Sub(817, 1928), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3028PolyExtStep::AndEqz(1070, 1929), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3029PolyExtStep::Mul(823, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3030PolyExtStep::Add(1840, 1930), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3031PolyExtStep::Sub(1830, 1931), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3032PolyExtStep::AndEqz(1071, 1932), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3033PolyExtStep::AndEqz(1072, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3034PolyExtStep::AndEqz(1073, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3035PolyExtStep::Mul(1137, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:30) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3036PolyExtStep::Add(1162, 1933), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:21) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3037PolyExtStep::Sub(0, 1934), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3038PolyExtStep::AndEqz(1074, 1935), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3039PolyExtStep::AndEqz(1075, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3040PolyExtStep::AndEqz(1076, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3041PolyExtStep::AndEqz(1077, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3042PolyExtStep::AndEqz(1078, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3043PolyExtStep::Mul(832, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3044PolyExtStep::Add(1936, 829), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3045PolyExtStep::Mul(1937, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3046PolyExtStep::Add(1938, 1858), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3047PolyExtStep::Add(1939, 1143), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3048PolyExtStep::Sub(1853, 1940), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3049PolyExtStep::AndEqz(1079, 1941), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3050PolyExtStep::Mul(1937, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3051PolyExtStep::Add(1942, 1432), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3052PolyExtStep::Add(1943, 1864), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :134:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3053PolyExtStep::Add(1944, 1866), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3054PolyExtStep::Add(1945, 1868), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:35) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3055PolyExtStep::Add(1946, 1877), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:51) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3056PolyExtStep::AndEqz(1080, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3057PolyExtStep::AndEqz(1081, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3058PolyExtStep::AndEqz(1082, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3059PolyExtStep::AndEqz(1083, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3060PolyExtStep::Mul(838, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3061PolyExtStep::Add(1948, 835), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3062PolyExtStep::Mul(1949, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3063PolyExtStep::Add(1950, 1882), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3064PolyExtStep::Add(1951, 1148), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3065PolyExtStep::Sub(1947, 1952), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3066PolyExtStep::AndEqz(1084, 1953), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3067PolyExtStep::Mul(1949, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3068PolyExtStep::Add(1954, 1440), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3069PolyExtStep::Add(1955, 47), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:42) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3070PolyExtStep::Add(1956, 1889), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3071PolyExtStep::Add(1957, 1891), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3072PolyExtStep::Add(1958, 1893), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3073PolyExtStep::Add(1959, 1898), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3074PolyExtStep::AndEqz(1085, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3075PolyExtStep::AndEqz(1086, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3076PolyExtStep::AndEqz(1087, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3077PolyExtStep::AndEqz(1088, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3078PolyExtStep::Mul(844, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3079PolyExtStep::Add(1961, 841), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3080PolyExtStep::Mul(1962, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3081PolyExtStep::Add(1963, 1905), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3082PolyExtStep::Add(1964, 1154), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3083PolyExtStep::Sub(1960, 1965), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3084PolyExtStep::AndEqz(1089, 1966), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3085PolyExtStep::Mul(1962, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3086PolyExtStep::Add(1967, 538), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3087PolyExtStep::Add(1968, 46), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :151:42) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3088PolyExtStep::Add(1969, 1912), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3089PolyExtStep::AndEqz(1090, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3090PolyExtStep::Sub(1970, 1160), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3091PolyExtStep::Mul(1971, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3092PolyExtStep::AndEqz(1091, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3093PolyExtStep::AndEqz(1092, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3094PolyExtStep::Mul(850, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3095PolyExtStep::Add(1973, 847), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3096PolyExtStep::Sub(1972, 1974), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3097PolyExtStep::AndEqz(1093, 1975), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3098PolyExtStep::AndEqz(1094, 1372), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3099PolyExtStep::AndCond(1052, 383, 1095), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3100PolyExtStep::AndEqz(946, 1921), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3101PolyExtStep::AndEqz(1097, 1810), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3102PolyExtStep::AndEqz(1098, 1811), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3103PolyExtStep::AndEqz(1099, 1393), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3104PolyExtStep::AndEqz(1100, 1812), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3105PolyExtStep::AndEqz(1101, 1813), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3106PolyExtStep::AndEqz(1102, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3107PolyExtStep::AndEqz(1103, 1816), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3108PolyExtStep::AndEqz(1104, 1923), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3109PolyExtStep::AndEqz(1105, 1926), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3110PolyExtStep::AndEqz(1106, 1826), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3111PolyExtStep::AndEqz(1107, 1827), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3112PolyExtStep::AndEqz(1108, 1828), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3113PolyExtStep::AndEqz(1109, 1831), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3114PolyExtStep::AndEqz(1110, 1434), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3115PolyExtStep::AndEqz(1111, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3116PolyExtStep::AndEqz(1112, 1927), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3117PolyExtStep::AndEqz(1113, 1929), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3118PolyExtStep::AndEqz(1114, 1932), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3119PolyExtStep::AndEqz(1115, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3120PolyExtStep::AndEqz(1116, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3121PolyExtStep::AndEqz(1117, 1935), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3122PolyExtStep::AndEqz(1118, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3123PolyExtStep::AndEqz(1119, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3124PolyExtStep::AndEqz(1120, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3125PolyExtStep::AndEqz(1121, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3126PolyExtStep::AndEqz(1122, 1941), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3127PolyExtStep::AndEqz(1123, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3128PolyExtStep::AndEqz(1124, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3129PolyExtStep::AndEqz(1125, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3130PolyExtStep::AndEqz(1126, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3131PolyExtStep::AndEqz(1127, 1953), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3132PolyExtStep::Mul(1815, 823), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:40) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3133PolyExtStep::Sub(1956, 1976), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:8) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3134PolyExtStep::Mul(1833, 820), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:75) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3135PolyExtStep::Sub(1977, 1978), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:47) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3136PolyExtStep::Add(1979, 1889), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3137PolyExtStep::Add(1980, 1891), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3138PolyExtStep::Add(1981, 1893), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3139PolyExtStep::Add(1982, 1898), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3140PolyExtStep::AndEqz(1128, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3141PolyExtStep::AndEqz(1129, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3142PolyExtStep::AndEqz(1130, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3143PolyExtStep::AndEqz(1131, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3144PolyExtStep::Sub(1983, 1965), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3145PolyExtStep::AndEqz(1132, 1984), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3146PolyExtStep::Mul(1401, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:30) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3147PolyExtStep::Add(1392, 1985), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:22) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3148PolyExtStep::Mul(1986, 823), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:40) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3149PolyExtStep::Sub(1969, 1987), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:8) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3150PolyExtStep::Mul(1830, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:65) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3151PolyExtStep::Add(1428, 1989), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:57) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3152PolyExtStep::Mul(1990, 820), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:75) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3153PolyExtStep::Sub(1988, 1991), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:47) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3154PolyExtStep::Add(1992, 1912), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3155PolyExtStep::AndEqz(1133, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3156PolyExtStep::Sub(1993, 1160), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3157PolyExtStep::Mul(1994, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3158PolyExtStep::AndEqz(1134, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3159PolyExtStep::AndEqz(1135, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3160PolyExtStep::Sub(1995, 1974), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3161PolyExtStep::AndEqz(1136, 1996), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3162PolyExtStep::AndEqz(1137, 1372), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3163PolyExtStep::AndCond(1096, 386, 1138), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3164PolyExtStep::Sub(1733, 7), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3165PolyExtStep::AndEqz(945, 1997), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3166PolyExtStep::AndEqz(1140, 1921), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3167PolyExtStep::AndEqz(1141, 1810), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3168PolyExtStep::AndEqz(1142, 1811), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3169PolyExtStep::AndEqz(1143, 1393), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3170PolyExtStep::AndEqz(1144, 1812), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3171PolyExtStep::AndEqz(1145, 1813), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3172PolyExtStep::AndEqz(1146, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3173PolyExtStep::AndEqz(1147, 1816), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3174PolyExtStep::AndEqz(1148, 1923), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3175PolyExtStep::AndEqz(1149, 1926), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3176PolyExtStep::AndEqz(1150, 1826), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3177PolyExtStep::AndEqz(1151, 1827), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3178PolyExtStep::AndEqz(1152, 1828), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3179PolyExtStep::AndEqz(1153, 1831), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3180PolyExtStep::AndEqz(1154, 1434), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3181PolyExtStep::AndEqz(1155, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3182PolyExtStep::AndEqz(1156, 1927), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3183PolyExtStep::AndEqz(1157, 1929), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3184PolyExtStep::AndEqz(1158, 1932), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3185PolyExtStep::AndEqz(1159, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3186PolyExtStep::AndEqz(1160, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3187PolyExtStep::AndEqz(1161, 1935), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3188PolyExtStep::AndEqz(1162, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3189PolyExtStep::AndEqz(1163, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3190PolyExtStep::AndEqz(1164, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3191PolyExtStep::AndEqz(1165, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3192PolyExtStep::AndEqz(1166, 1941), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3193PolyExtStep::AndEqz(1167, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3194PolyExtStep::AndEqz(1168, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3195PolyExtStep::AndEqz(1169, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3196PolyExtStep::AndEqz(1170, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3197PolyExtStep::AndEqz(1171, 1953), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3198PolyExtStep::Sub(1956, 1978), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:47) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3199PolyExtStep::Add(1998, 1889), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3200PolyExtStep::Add(1999, 1891), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3201PolyExtStep::Add(2000, 1893), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3202PolyExtStep::Add(2001, 1898), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3203PolyExtStep::AndEqz(1172, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3204PolyExtStep::AndEqz(1173, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3205PolyExtStep::AndEqz(1174, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3206PolyExtStep::AndEqz(1175, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3207PolyExtStep::Sub(2002, 1965), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3208PolyExtStep::AndEqz(1176, 2003), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3209PolyExtStep::Sub(1969, 1991), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:47) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3210PolyExtStep::Add(2004, 1912), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3211PolyExtStep::AndEqz(1177, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3212PolyExtStep::Sub(2005, 1160), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3213PolyExtStep::Mul(2006, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3214PolyExtStep::AndEqz(1178, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3215PolyExtStep::AndEqz(1179, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3216PolyExtStep::Sub(2007, 1974), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3217PolyExtStep::AndEqz(1180, 2008), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3218PolyExtStep::AndEqz(1181, 1372), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3219PolyExtStep::AndCond(1139, 389, 1182), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3220PolyExtStep::Sub(1733, 6), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3221PolyExtStep::AndEqz(945, 2009), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3222PolyExtStep::AndEqz(1184, 1921), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3223PolyExtStep::AndEqz(1185, 1810), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3224PolyExtStep::AndEqz(1186, 1811), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3225PolyExtStep::AndEqz(1187, 1393), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3226PolyExtStep::AndEqz(1188, 1812), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3227PolyExtStep::AndEqz(1189, 1813), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3228PolyExtStep::AndEqz(1190, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3229PolyExtStep::AndEqz(1191, 1816), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3230PolyExtStep::AndEqz(1192, 1923), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3231PolyExtStep::AndEqz(1193, 1926), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3232PolyExtStep::AndEqz(1194, 1826), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3233PolyExtStep::AndEqz(1195, 1827), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3234PolyExtStep::AndEqz(1196, 1828), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3235PolyExtStep::AndEqz(1197, 1831), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3236PolyExtStep::AndEqz(1198, 1434), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3237PolyExtStep::AndEqz(1199, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3238PolyExtStep::AndEqz(1200, 1927), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3239PolyExtStep::AndEqz(1201, 1929), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3240PolyExtStep::AndEqz(1202, 1932), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3241PolyExtStep::AndEqz(1203, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3242PolyExtStep::AndEqz(1204, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3243PolyExtStep::AndEqz(1205, 1935), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3244PolyExtStep::AndEqz(1206, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3245PolyExtStep::AndEqz(1207, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3246PolyExtStep::AndEqz(1208, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3247PolyExtStep::AndEqz(1209, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3248PolyExtStep::AndEqz(1210, 1941), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3249PolyExtStep::AndEqz(1211, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3250PolyExtStep::AndEqz(1212, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3251PolyExtStep::AndEqz(1213, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3252PolyExtStep::AndEqz(1214, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3253PolyExtStep::AndEqz(1215, 1953), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3254PolyExtStep::AndEqz(1216, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3255PolyExtStep::AndEqz(1217, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3256PolyExtStep::AndEqz(1218, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3257PolyExtStep::AndEqz(1219, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3258PolyExtStep::AndEqz(1220, 1966), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3259PolyExtStep::AndEqz(1221, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3260PolyExtStep::AndEqz(1222, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3261PolyExtStep::AndEqz(1223, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3262PolyExtStep::AndEqz(1224, 1975), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3263PolyExtStep::AndEqz(1225, 1372), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3264PolyExtStep::AndCond(1183, 392, 1226), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3265PolyExtStep::AndEqz(0, 17), // loc(callsite( IllegalMulOp ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :18:6) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :32:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3266PolyExtStep::AndEqz(1228, 807), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3267PolyExtStep::AndEqz(1229, 808), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3268PolyExtStep::AndEqz(1230, 809), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3269PolyExtStep::AndEqz(1231, 810), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3270PolyExtStep::AndEqz(1232, 811), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3271PolyExtStep::AndEqz(1233, 1372), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3272PolyExtStep::AndEqz(1234, 1375), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3273PolyExtStep::AndEqz(1235, 1383), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3274PolyExtStep::AndEqz(1236, 1391), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3275PolyExtStep::AndEqz(1237, 1394), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3276PolyExtStep::AndEqz(1238, 1402), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3277PolyExtStep::AndEqz(1239, 1410), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3278PolyExtStep::AndEqz(1240, 1424), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3279PolyExtStep::AndEqz(1241, 1426), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3280PolyExtStep::AndEqz(1242, 1829), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3281PolyExtStep::AndEqz(1243, 1429), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3282PolyExtStep::AndEqz(1244, 1431), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3283PolyExtStep::AndEqz(1245, 1439), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3284PolyExtStep::AndEqz(1246, 1900), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3285PolyExtStep::AndCond(1227, 395, 1247), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3286PolyExtStep::AndCond(1248, 398, 1247), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3287PolyExtStep::Get(164), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3288PolyExtStep::Mul(2010, 377), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3289PolyExtStep::Mul(2010, 380), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3290PolyExtStep::Get(160), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3291PolyExtStep::Mul(2013, 383), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3292PolyExtStep::Get(167), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3293PolyExtStep::Mul(2015, 386), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3294PolyExtStep::Mul(2015, 389), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3295PolyExtStep::Mul(2015, 392), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3296PolyExtStep::Add(2011, 2012), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3297PolyExtStep::Add(2019, 2014), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3298PolyExtStep::Add(2020, 2016), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3299PolyExtStep::Add(2021, 2017), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3300PolyExtStep::Add(2022, 2018), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3301PolyExtStep::Mul(2015, 377), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3302PolyExtStep::Mul(2015, 380), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3303PolyExtStep::Mul(2010, 383), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3304PolyExtStep::Get(179), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3305PolyExtStep::Mul(2027, 386), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3306PolyExtStep::Mul(2027, 389), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3307PolyExtStep::Mul(2027, 392), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3308PolyExtStep::Add(2024, 2025), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3309PolyExtStep::Add(2031, 2026), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3310PolyExtStep::Add(2032, 2028), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3311PolyExtStep::Add(2033, 2029), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3312PolyExtStep::Add(2034, 2030), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3313PolyExtStep::AndEqz(1249, 910), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3314PolyExtStep::Mul(1725, 911), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3315PolyExtStep::Sub(2036, 909), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3316PolyExtStep::AndEqz(1250, 2037), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3317PolyExtStep::Mul(908, 1725), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3318PolyExtStep::AndEqz(1251, 2038), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3319PolyExtStep::Mul(908, 911), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3320PolyExtStep::AndEqz(1252, 2039), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3321PolyExtStep::Mul(909, 1725), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:11) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3322PolyExtStep::Sub(1, 909), // loc(callsite( builtin Sub at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:90) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3323PolyExtStep::Mul(2041, 19), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:102) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3324PolyExtStep::Add(506, 2042), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:85) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3325PolyExtStep::Add(2043, 2040), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:106) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3326PolyExtStep::Sub(2044, 914), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3327PolyExtStep::AndEqz(1253, 2045), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3328PolyExtStep::Sub(920, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3329PolyExtStep::AndEqz(1254, 2046), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3330PolyExtStep::Sub(932, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3331PolyExtStep::AndEqz(1255, 2047), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3332PolyExtStep::Sub(935, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3333PolyExtStep::AndEqz(1256, 2048), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3334PolyExtStep::AndEqz(1257, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3335PolyExtStep::Sub(917, 914), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3336PolyExtStep::AndEqz(1258, 2049), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3337PolyExtStep::Sub(935, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3338PolyExtStep::Sub(2050, 923), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3339PolyExtStep::Sub(975, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3340PolyExtStep::AndEqz(1259, 2052), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3341PolyExtStep::Sub(978, 2051), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3342PolyExtStep::AndEqz(1260, 2053), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3343PolyExtStep::Sub(938, 2023), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3344PolyExtStep::AndEqz(1261, 2054), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3345PolyExtStep::Sub(972, 2035), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3346PolyExtStep::AndEqz(1262, 2055), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3347PolyExtStep::Sub(981, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3348PolyExtStep::AndEqz(1263, 2056), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3349PolyExtStep::AndEqz(1264, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3350PolyExtStep::Mul(987, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3351PolyExtStep::Add(2057, 984), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3352PolyExtStep::Sub(507, 2058), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3353PolyExtStep::AndEqz(1265, 2059), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3354PolyExtStep::Add(370, 987), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3355PolyExtStep::Sub(990, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3356PolyExtStep::AndEqz(1266, 2061), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3357PolyExtStep::AndEqz(1267, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3358PolyExtStep::Mul(996, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3359PolyExtStep::Add(2062, 993), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3360PolyExtStep::Sub(2060, 2063), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3361PolyExtStep::AndEqz(1268, 2064), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3362PolyExtStep::AndCond(863, 431, 1269), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
3363PolyExtStep::Sub(555, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3364PolyExtStep::AndEqz(0, 2065), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3365PolyExtStep::Sub(563, 542), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3366PolyExtStep::AndEqz(1271, 2066), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3367PolyExtStep::AndEqz(1272, 497), // loc(callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :8:21) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
3368PolyExtStep::Sub(1, 743), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3369PolyExtStep::Mul(743, 2067), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3370PolyExtStep::Sub(7, 743), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3371PolyExtStep::Mul(2068, 2069), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3372PolyExtStep::Sub(6, 743), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3373PolyExtStep::Mul(2070, 2071), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3374PolyExtStep::AndEqz(1273, 2072), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3375PolyExtStep::AndEqz(1274, 749), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3376PolyExtStep::Sub(745, 502), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3377PolyExtStep::AndEqz(1275, 2073), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3378PolyExtStep::Sub(1, 746), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3379PolyExtStep::Mul(746, 2074), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3380PolyExtStep::AndEqz(1276, 2075), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3381PolyExtStep::Mul(370, 747), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3382PolyExtStep::Sub(2076, 2074), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3383PolyExtStep::AndEqz(1277, 2077), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3384PolyExtStep::Mul(746, 370), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3385PolyExtStep::AndEqz(1278, 2078), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3386PolyExtStep::Mul(746, 747), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3387PolyExtStep::AndEqz(1279, 2079), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3388PolyExtStep::AndEqz(1280, 746), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:19) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3389PolyExtStep::Sub(760, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3390PolyExtStep::AndEqz(1281, 2080), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3391PolyExtStep::Mul(766, 5), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:4) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3392PolyExtStep::Add(2081, 743), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:12) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3393PolyExtStep::Sub(2082, 368), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3394PolyExtStep::AndEqz(1282, 2083), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3395PolyExtStep::Add(503, 766), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :73:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3396PolyExtStep::AndEqz(1283, 743), // loc(callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :29:17) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3397PolyExtStep::Sub(768, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3398PolyExtStep::AndEqz(1284, 2085), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3399PolyExtStep::AndEqz(1285, 1751), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3400PolyExtStep::AndEqz(1286, 1752), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3401PolyExtStep::AndEqz(1287, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3402PolyExtStep::Sub(767, 2084), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3403PolyExtStep::AndEqz(1288, 2086), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3404PolyExtStep::AndEqz(1289, 1754), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3405PolyExtStep::AndEqz(1290, 1755), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3406PolyExtStep::AndEqz(1291, 782), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3407PolyExtStep::Sub(781, 1757), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3408PolyExtStep::AndEqz(1292, 2087), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3409PolyExtStep::Sub(1, 564), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3410PolyExtStep::Mul(564, 2088), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3411PolyExtStep::AndEqz(1293, 2089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3412PolyExtStep::Sub(1, 571), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3413PolyExtStep::Mul(571, 2090), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3414PolyExtStep::Sub(7, 571), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3415PolyExtStep::Mul(2091, 2092), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3416PolyExtStep::Sub(6, 571), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3417PolyExtStep::Mul(2093, 2094), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3418PolyExtStep::AndEqz(1294, 2095), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3419PolyExtStep::Sub(1, 570), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3420PolyExtStep::Mul(570, 2096), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3421PolyExtStep::Sub(7, 570), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3422PolyExtStep::Mul(2097, 2098), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3423PolyExtStep::Sub(6, 570), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3424PolyExtStep::Mul(2099, 2100), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3425PolyExtStep::AndEqz(1295, 2101), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3426PolyExtStep::Sub(1, 572), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3427PolyExtStep::Mul(572, 2102), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3428PolyExtStep::Sub(7, 572), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3429PolyExtStep::Mul(2103, 2104), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3430PolyExtStep::Sub(6, 572), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3431PolyExtStep::Mul(2105, 2106), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3432PolyExtStep::AndEqz(1296, 2107), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3433PolyExtStep::Sub(1, 573), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3434PolyExtStep::Mul(573, 2108), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3435PolyExtStep::Sub(7, 573), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3436PolyExtStep::Mul(2109, 2110), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3437PolyExtStep::Sub(6, 573), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3438PolyExtStep::Mul(2111, 2112), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3439PolyExtStep::AndEqz(1297, 2113), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3440PolyExtStep::Sub(1, 574), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3441PolyExtStep::Mul(574, 2114), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3442PolyExtStep::Sub(7, 574), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3443PolyExtStep::Mul(2115, 2116), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3444PolyExtStep::Sub(6, 574), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3445PolyExtStep::Mul(2117, 2118), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3446PolyExtStep::AndEqz(1298, 2119), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3447PolyExtStep::Sub(1, 575), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3448PolyExtStep::Mul(575, 2120), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3449PolyExtStep::AndEqz(1299, 2121), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3450PolyExtStep::Sub(1, 576), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3451PolyExtStep::Mul(576, 2122), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3452PolyExtStep::Sub(7, 576), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3453PolyExtStep::Mul(2123, 2124), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3454PolyExtStep::Sub(6, 576), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3455PolyExtStep::Mul(2125, 2126), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3456PolyExtStep::AndEqz(1300, 2127), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3457PolyExtStep::Sub(1, 577), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3458PolyExtStep::Mul(577, 2128), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3459PolyExtStep::Sub(7, 577), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3460PolyExtStep::Mul(2129, 2130), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3461PolyExtStep::Sub(6, 577), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3462PolyExtStep::Mul(2131, 2132), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3463PolyExtStep::AndEqz(1301, 2133), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3464PolyExtStep::Sub(1, 578), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3465PolyExtStep::Mul(578, 2134), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3466PolyExtStep::AndEqz(1302, 2135), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3467PolyExtStep::Sub(1, 587), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3468PolyExtStep::Mul(587, 2136), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3469PolyExtStep::AndEqz(1303, 2137), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3470PolyExtStep::Sub(1, 588), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3471PolyExtStep::Mul(588, 2138), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3472PolyExtStep::Sub(7, 588), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3473PolyExtStep::Mul(2139, 2140), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3474PolyExtStep::Sub(6, 588), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3475PolyExtStep::Mul(2141, 2142), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3476PolyExtStep::AndEqz(1304, 2143), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3477PolyExtStep::Sub(1, 739), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3478PolyExtStep::Mul(739, 2144), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3479PolyExtStep::Sub(7, 739), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3480PolyExtStep::Mul(2145, 2146), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3481PolyExtStep::Sub(6, 739), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3482PolyExtStep::Mul(2147, 2148), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3483PolyExtStep::AndEqz(1305, 2149), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3484PolyExtStep::Sub(1, 740), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3485PolyExtStep::Mul(740, 2150), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3486PolyExtStep::Sub(7, 740), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3487PolyExtStep::Mul(2151, 2152), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3488PolyExtStep::Sub(6, 740), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3489PolyExtStep::Mul(2153, 2154), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3490PolyExtStep::AndEqz(1306, 2155), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3491PolyExtStep::Sub(1, 741), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3492PolyExtStep::Mul(741, 2156), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3493PolyExtStep::AndEqz(1307, 2157), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3494PolyExtStep::Mul(564, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3495PolyExtStep::Mul(571, 28), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3496PolyExtStep::Add(2158, 2159), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3497PolyExtStep::Mul(570, 27), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3498PolyExtStep::Add(2160, 2161), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3499PolyExtStep::Mul(572, 26), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3500PolyExtStep::Add(2162, 2163), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3501PolyExtStep::Mul(573, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3502PolyExtStep::Add(2164, 2165), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3503PolyExtStep::Mul(574, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3504PolyExtStep::Add(2166, 2167), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3505PolyExtStep::Mul(575, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3506PolyExtStep::Add(2168, 2169), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3507PolyExtStep::Mul(576, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3508PolyExtStep::Add(2170, 2171), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3509PolyExtStep::Add(2172, 577), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3510PolyExtStep::Sub(757, 2173), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3511PolyExtStep::AndEqz(1308, 2174), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3512PolyExtStep::Mul(578, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3513PolyExtStep::Mul(587, 14), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3514PolyExtStep::Add(2175, 2176), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3515PolyExtStep::Mul(588, 22), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3516PolyExtStep::Add(2177, 2178), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3517PolyExtStep::Mul(739, 21), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3518PolyExtStep::Add(2179, 2180), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3519PolyExtStep::Mul(740, 20), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3520PolyExtStep::Add(2181, 2182), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3521PolyExtStep::Mul(741, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3522PolyExtStep::Add(2183, 2184), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3523PolyExtStep::Add(2185, 742), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3524PolyExtStep::Sub(756, 2186), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3525PolyExtStep::AndEqz(1309, 2187), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3526PolyExtStep::Mul(576, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3527PolyExtStep::Mul(577, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3528PolyExtStep::Add(2188, 2189), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3529PolyExtStep::Add(2190, 578), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3530PolyExtStep::Mul(573, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3531PolyExtStep::Mul(574, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3532PolyExtStep::Add(2192, 2193), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3533PolyExtStep::Add(2194, 575), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3534PolyExtStep::Mul(739, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:17) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3535PolyExtStep::Mul(740, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:30) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3536PolyExtStep::Add(2196, 2197), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3537PolyExtStep::Add(2198, 741), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:39) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3538PolyExtStep::Mul(571, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3539PolyExtStep::Add(2200, 1648), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3540PolyExtStep::Add(2201, 572), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:47) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3541PolyExtStep::Mul(564, 19), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3542PolyExtStep::Add(2203, 2202), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3543PolyExtStep::Mul(587, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3544PolyExtStep::Add(2205, 588), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3545PolyExtStep::AndEqz(1310, 861), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :49:36) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3546PolyExtStep::Sub(2191, 2195), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :52:18) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3547PolyExtStep::Add(506, 2191), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3548PolyExtStep::AndEqz(0, 2207), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :52:18) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3549PolyExtStep::Sub(2208, 893), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3550PolyExtStep::AndEqz(1312, 2209), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3551PolyExtStep::Sub(732, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3552PolyExtStep::AndEqz(1313, 2210), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3553PolyExtStep::Sub(802, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3554PolyExtStep::AndEqz(1314, 2211), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3555PolyExtStep::Sub(804, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3556PolyExtStep::AndEqz(1315, 2212), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3557PolyExtStep::AndEqz(1316, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3558PolyExtStep::Sub(737, 893), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3559PolyExtStep::AndEqz(1317, 2213), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3560PolyExtStep::Sub(798, 814), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3561PolyExtStep::AndEqz(1318, 2214), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3562PolyExtStep::Sub(800, 817), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3563PolyExtStep::AndEqz(1319, 2215), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3564PolyExtStep::Sub(804, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3565PolyExtStep::Sub(2216, 764), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3566PolyExtStep::Sub(847, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3567PolyExtStep::AndEqz(1320, 2218), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3568PolyExtStep::Sub(850, 2217), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3569PolyExtStep::AndEqz(1321, 2219), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3570PolyExtStep::AndEqz(1322, 820), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3571PolyExtStep::AndEqz(1323, 835), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3572PolyExtStep::AndEqz(1324, 853), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3573PolyExtStep::AndCond(1311, 859, 1325), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3574PolyExtStep::Add(506, 2195), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3575PolyExtStep::AndEqz(0, 2209), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3576PolyExtStep::AndEqz(1327, 2210), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3577PolyExtStep::AndEqz(1328, 2211), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3578PolyExtStep::AndEqz(1329, 2212), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3579PolyExtStep::AndEqz(1330, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3580PolyExtStep::AndEqz(1331, 2213), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3581PolyExtStep::AndEqz(1332, 2214), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3582PolyExtStep::AndEqz(1333, 2215), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3583PolyExtStep::AndEqz(1334, 2218), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3584PolyExtStep::AndEqz(1335, 2219), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3585PolyExtStep::Sub(2220, 896), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3586PolyExtStep::AndEqz(1336, 2221), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3587PolyExtStep::Sub(820, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3588PolyExtStep::AndEqz(1337, 2222), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3589PolyExtStep::Sub(835, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3590PolyExtStep::AndEqz(1338, 2223), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3591PolyExtStep::Sub(838, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3592PolyExtStep::AndEqz(1339, 2224), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3593PolyExtStep::AndEqz(1340, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3594PolyExtStep::Sub(823, 896), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3595PolyExtStep::AndEqz(1341, 2225), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3596PolyExtStep::Sub(829, 841), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3597PolyExtStep::AndEqz(1342, 2226), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3598PolyExtStep::Sub(832, 844), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3599PolyExtStep::AndEqz(1343, 2227), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3600PolyExtStep::Sub(838, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3601PolyExtStep::Sub(2228, 826), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3602PolyExtStep::Sub(853, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3603PolyExtStep::AndEqz(1344, 2230), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3604PolyExtStep::Sub(856, 2229), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3605PolyExtStep::AndEqz(1345, 2231), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3606PolyExtStep::AndCond(1326, 860, 1346), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3607PolyExtStep::Mul(1182, 859), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3608PolyExtStep::Mul(1182, 860), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3609PolyExtStep::Add(2232, 2233), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3610PolyExtStep::Mul(1183, 859), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3611PolyExtStep::Mul(1183, 860), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3612PolyExtStep::Add(2235, 2236), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3613PolyExtStep::Mul(1191, 860), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3614PolyExtStep::Add(2232, 2238), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3615PolyExtStep::Mul(1192, 860), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3616PolyExtStep::Add(2235, 2240), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3617PolyExtStep::Sub(2234, 899), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:17) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3618PolyExtStep::AndEqz(1347, 2242), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:17) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3619PolyExtStep::Sub(2237, 902), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :63:17) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3620PolyExtStep::AndEqz(1348, 2243), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :63:17) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3621PolyExtStep::Sub(2239, 905), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :64:17) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3622PolyExtStep::AndEqz(1349, 2244), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :64:17) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3623PolyExtStep::Sub(2241, 908), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :65:18) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3624PolyExtStep::AndEqz(1350, 2245), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :65:18) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3625PolyExtStep::Sub(742, 32), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :134:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3626PolyExtStep::Sub(2206, 4), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :134:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3627PolyExtStep::Sub(902, 29), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :106:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3628PolyExtStep::AndEqz(0, 2246), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :134:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3629PolyExtStep::AndEqz(1352, 2247), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :134:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3630PolyExtStep::AndEqz(1353, 2204), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :134:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3631PolyExtStep::AndEqz(1354, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3632PolyExtStep::AndEqz(1355, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3633PolyExtStep::AndEqz(1356, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3634PolyExtStep::AndEqz(1357, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3635PolyExtStep::AndEqz(1358, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3636PolyExtStep::Mul(914, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3637PolyExtStep::Mul(917, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3638PolyExtStep::Mul(920, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3639PolyExtStep::Mul(923, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3640PolyExtStep::Add(911, 2249), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3641PolyExtStep::Add(2253, 2250), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3642PolyExtStep::Add(2254, 2251), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3643PolyExtStep::Add(2255, 2252), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3644PolyExtStep::AndEqz(1359, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :40:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3645PolyExtStep::Add(1788, 2256), // loc(callsite( builtin Add at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:16) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3646PolyExtStep::Sub(2257, 905), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3647PolyExtStep::AndEqz(1360, 2258), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3648PolyExtStep::Mul(911, 7), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :42:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3649PolyExtStep::Add(2259, 912), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :42:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3650PolyExtStep::Mul(914, 2260), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3651PolyExtStep::Mul(2261, 5), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3652PolyExtStep::Mul(915, 2260), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3653PolyExtStep::Add(2262, 2263), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3654PolyExtStep::Mul(917, 2264), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3655PolyExtStep::Mul(2265, 23), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3656PolyExtStep::Mul(918, 2264), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3657PolyExtStep::Add(2266, 2267), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3658PolyExtStep::Sub(2268, 926), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3659PolyExtStep::AndEqz(1361, 2269), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3660PolyExtStep::Mul(920, 926), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3661PolyExtStep::Mul(2270, 20), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3662PolyExtStep::Mul(921, 926), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3663PolyExtStep::Add(2271, 2272), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3664PolyExtStep::Mul(924, 2273), // loc(callsite( builtin Mul at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3665PolyExtStep::Sub(2274, 929), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3666PolyExtStep::AndEqz(1362, 2275), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3667PolyExtStep::Mul(923, 2273), // loc(callsite( builtin Mul at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:22) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3668PolyExtStep::Sub(2276, 932), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3669PolyExtStep::AndEqz(1363, 2277), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3670PolyExtStep::AndEqz(1364, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3671PolyExtStep::AndEqz(1365, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :57:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3672PolyExtStep::AndEqz(1366, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3673PolyExtStep::AndEqz(1367, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3674PolyExtStep::AndEqz(1368, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3675PolyExtStep::Get(353), // loc(callsite( builtin NondetReg at callsite( ArgU8 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :9:29) at callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :18:16) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3676PolyExtStep::Sub(2278, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3677PolyExtStep::AndEqz(1369, 2279), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3678PolyExtStep::Sub(591, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3679PolyExtStep::AndEqz(1370, 2280), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3680PolyExtStep::AndEqz(1371, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3681PolyExtStep::Mul(1440, 20), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:17) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3682PolyExtStep::Add(1432, 2281), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:12) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3683PolyExtStep::Sub(935, 2282), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3684PolyExtStep::AndEqz(1372, 2283), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3685PolyExtStep::Mul(594, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:18) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3686PolyExtStep::Add(538, 2284), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3687PolyExtStep::Mul(972, 29), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:40) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3688PolyExtStep::Add(2285, 2286), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3689PolyExtStep::Sub(938, 2287), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3690PolyExtStep::AndEqz(1373, 2288), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3691PolyExtStep::Mul(594, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:9) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3692PolyExtStep::Mul(972, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3693PolyExtStep::Add(2289, 2290), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3694PolyExtStep::Sub(539, 2291), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3695PolyExtStep::AndEqz(1374, 2292), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3696PolyExtStep::Sub(601, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3697PolyExtStep::AndEqz(1375, 2293), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3698PolyExtStep::Sub(615, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3699PolyExtStep::AndEqz(1376, 2294), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3700PolyExtStep::Sub(629, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3701PolyExtStep::AndEqz(1377, 2295), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3702PolyExtStep::Sub(639, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3703PolyExtStep::AndEqz(1378, 2296), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3704PolyExtStep::Sub(649, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3705PolyExtStep::AndEqz(1379, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3706PolyExtStep::AndEqz(1380, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3707PolyExtStep::Mul(622, 20), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:17) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3708PolyExtStep::Add(608, 2298), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:12) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3709PolyExtStep::Sub(929, 2299), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3710PolyExtStep::AndEqz(1381, 2300), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3711PolyExtStep::Mul(652, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:18) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3712PolyExtStep::Add(632, 2301), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3713PolyExtStep::Mul(975, 29), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:40) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3714PolyExtStep::Add(2302, 2303), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3715PolyExtStep::Sub(932, 2304), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3716PolyExtStep::AndEqz(1382, 2305), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3717PolyExtStep::Mul(652, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:9) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3718PolyExtStep::Mul(975, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3719PolyExtStep::Add(2306, 2307), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3720PolyExtStep::Sub(646, 2308), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3721PolyExtStep::AndEqz(1383, 2309), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3722PolyExtStep::AndEqz(1384, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3723PolyExtStep::AndEqz(1385, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3724PolyExtStep::Mul(978, 29), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3725PolyExtStep::Add(2310, 1157), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:21) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3726PolyExtStep::Sub(1148, 2311), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3727PolyExtStep::AndEqz(1386, 2312), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3728PolyExtStep::Mul(1432, 608), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :128:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3729PolyExtStep::Add(1143, 2313), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :127:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3730PolyExtStep::Mul(1432, 622), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3731PolyExtStep::Mul(1440, 608), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:36) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3732PolyExtStep::Add(2315, 2316), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3733PolyExtStep::Mul(2317, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3734PolyExtStep::Add(2314, 2318), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :128:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3735PolyExtStep::AndEqz(1387, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3736PolyExtStep::Sub(659, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3737PolyExtStep::AndEqz(1388, 2320), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3738PolyExtStep::AndEqz(1389, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3739PolyExtStep::AndEqz(1390, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3740PolyExtStep::Mul(984, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3741PolyExtStep::Add(2321, 981), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3742PolyExtStep::Mul(2322, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3743PolyExtStep::Mul(666, 33), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3744PolyExtStep::Add(2323, 2324), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3745PolyExtStep::Add(2325, 1160), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3746PolyExtStep::Sub(2319, 2326), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3747PolyExtStep::AndEqz(1391, 2327), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3748PolyExtStep::Mul(2322, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3749PolyExtStep::Add(2328, 666), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3750PolyExtStep::Add(1148, 2329), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :133:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3751PolyExtStep::Mul(1432, 632), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3752PolyExtStep::Add(2330, 2331), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :134:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3753PolyExtStep::Mul(1440, 622), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:27) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3754PolyExtStep::Add(2332, 2333), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3755PolyExtStep::Mul(538, 608), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:43) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3756PolyExtStep::Add(2334, 2335), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3757PolyExtStep::Mul(1432, 646), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3758PolyExtStep::Mul(1440, 632), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:36) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3759PolyExtStep::Add(2337, 2338), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3760PolyExtStep::Mul(538, 622), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:52) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3761PolyExtStep::Add(2339, 2340), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:44) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3762PolyExtStep::Mul(539, 608), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:68) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3763PolyExtStep::Add(2341, 2342), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:60) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3764PolyExtStep::Mul(2343, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3765PolyExtStep::Add(2336, 2344), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3766PolyExtStep::AndEqz(1392, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3767PolyExtStep::Sub(673, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3768PolyExtStep::AndEqz(1393, 2346), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3769PolyExtStep::AndEqz(1394, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3770PolyExtStep::AndEqz(1395, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3771PolyExtStep::Mul(990, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3772PolyExtStep::Add(2347, 987), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3773PolyExtStep::Mul(2348, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3774PolyExtStep::Mul(676, 33), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3775PolyExtStep::Add(2349, 2350), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3776PolyExtStep::Add(2351, 1373), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3777PolyExtStep::Sub(2345, 2352), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3778PolyExtStep::AndEqz(1396, 2353), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3779PolyExtStep::Mul(2348, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3780PolyExtStep::Add(2354, 676), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3781PolyExtStep::Add(2355, 47), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3782PolyExtStep::Mul(1440, 646), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3783PolyExtStep::Add(2356, 2357), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3784PolyExtStep::Mul(538, 632), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:27) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3785PolyExtStep::Add(2358, 2359), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3786PolyExtStep::Mul(539, 622), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:43) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3787PolyExtStep::Add(2360, 2361), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3788PolyExtStep::Mul(538, 646), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3789PolyExtStep::Mul(539, 632), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:36) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3790PolyExtStep::Add(2363, 2364), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3791PolyExtStep::Mul(2365, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3792PolyExtStep::Add(2362, 2366), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3793PolyExtStep::AndEqz(1397, 1810), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3794PolyExtStep::Sub(544, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3795PolyExtStep::AndEqz(1398, 2368), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3796PolyExtStep::AndEqz(1399, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3797PolyExtStep::AndEqz(1400, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3798PolyExtStep::Mul(996, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3799PolyExtStep::Add(2369, 993), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3800PolyExtStep::Mul(2370, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3801PolyExtStep::Mul(551, 33), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3802PolyExtStep::Add(2371, 2372), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3803PolyExtStep::Add(2373, 1382), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3804PolyExtStep::Sub(2367, 2374), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3805PolyExtStep::AndEqz(1401, 2375), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3806PolyExtStep::Mul(2370, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3807PolyExtStep::Add(2376, 551), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3808PolyExtStep::Add(2377, 46), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :151:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3809PolyExtStep::Mul(539, 646), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :153:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3810PolyExtStep::Add(2378, 2379), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3811PolyExtStep::AndEqz(1402, 1811), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3812PolyExtStep::Sub(2380, 1385), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3813PolyExtStep::Mul(2381, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3814PolyExtStep::AndEqz(1403, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3815PolyExtStep::AndEqz(1404, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3816PolyExtStep::Mul(1002, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3817PolyExtStep::Add(2383, 999), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3818PolyExtStep::Sub(2382, 2384), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3819PolyExtStep::AndEqz(1405, 2385), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3820PolyExtStep::Sub(1160, 899), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3821PolyExtStep::AndEqz(1406, 2386), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3822PolyExtStep::Sub(1373, 902), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3823PolyExtStep::AndEqz(1407, 2387), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3824PolyExtStep::AndEqz(1408, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:30) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3825PolyExtStep::Mul(1005, 16), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:36) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3826PolyExtStep::Sub(1382, 2388), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3827PolyExtStep::AndEqz(1409, 2389), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3828PolyExtStep::Sub(1385, 2388), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3829PolyExtStep::AndEqz(1410, 2390), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3830PolyExtStep::AndEqz(1411, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :69:26) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3831PolyExtStep::Mul(1008, 29), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:25) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3832PolyExtStep::Sub(902, 2391), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:18) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3833PolyExtStep::Mul(2392, 7), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:40) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3834PolyExtStep::AndEqz(1412, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3835PolyExtStep::Sub(1392, 2393), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3836PolyExtStep::AndEqz(1413, 2394), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3837PolyExtStep::AndEqz(1414, 1812), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3838PolyExtStep::AndEqz(1415, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3839PolyExtStep::Mul(1011, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3840PolyExtStep::Add(2395, 1401), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3841PolyExtStep::Sub(929, 2396), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3842PolyExtStep::AndEqz(1416, 2397), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3843PolyExtStep::Add(932, 1011), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3844PolyExtStep::AndEqz(1417, 1813), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3845PolyExtStep::AndEqz(1418, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3846PolyExtStep::Mul(1014, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3847PolyExtStep::Add(2399, 1404), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3848PolyExtStep::Sub(2398, 2400), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3849PolyExtStep::AndEqz(1419, 2401), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3850PolyExtStep::AndEqz(1420, 1826), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3851PolyExtStep::AndEqz(1421, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3852PolyExtStep::Mul(1017, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3853PolyExtStep::Add(2402, 1411), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3854PolyExtStep::Sub(1143, 2403), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3855PolyExtStep::AndEqz(1422, 2404), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3856PolyExtStep::Add(1148, 1017), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3857PolyExtStep::AndEqz(1423, 1827), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3858PolyExtStep::AndEqz(1424, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3859PolyExtStep::Mul(1051, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3860PolyExtStep::Add(2406, 1427), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3861PolyExtStep::Sub(2405, 2407), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3862PolyExtStep::AndEqz(1425, 2408), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3863PolyExtStep::AndEqz(1426, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:26) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3864PolyExtStep::AndEqz(1427, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:38) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3865PolyExtStep::Add(1411, 33), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:19) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3866PolyExtStep::Sub(2409, 1401), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:31) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3867PolyExtStep::Add(1427, 16), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:44) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3868PolyExtStep::Sub(2411, 1404), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:55) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3869PolyExtStep::AndEqz(1428, 1828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3870PolyExtStep::AndEqz(1429, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3871PolyExtStep::Mul(1060, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3872PolyExtStep::Add(2413, 1428), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3873PolyExtStep::Sub(2410, 2414), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3874PolyExtStep::AndEqz(1430, 2415), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3875PolyExtStep::Add(2412, 1060), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3876PolyExtStep::AndEqz(1431, 1831), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3877PolyExtStep::AndEqz(1432, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3878PolyExtStep::Mul(1063, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3879PolyExtStep::Add(2417, 1830), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3880PolyExtStep::Sub(2416, 2418), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3881PolyExtStep::AndEqz(1433, 2419), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3882PolyExtStep::Sub(1055, 1057), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:37) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3883PolyExtStep::Sub(1143, 899), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3884PolyExtStep::Sub(1148, 902), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3885PolyExtStep::Sub(935, 16), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3886PolyExtStep::Sub(938, 16), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3887PolyExtStep::AndEqz(0, 929), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :100:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3888PolyExtStep::AndEqz(1435, 932), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :100:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3889PolyExtStep::AndEqz(1436, 2421), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3890PolyExtStep::AndEqz(1437, 2422), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3891PolyExtStep::AndEqz(1438, 2423), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3892PolyExtStep::AndEqz(1439, 2424), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3893PolyExtStep::AndCond(1434, 1054, 1440), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3894PolyExtStep::Sub(929, 16), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3895PolyExtStep::Sub(932, 16), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3896PolyExtStep::Sub(938, 29), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3897PolyExtStep::AndEqz(1228, 899), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :106:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3898PolyExtStep::AndEqz(1442, 2248), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :106:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3899PolyExtStep::AndEqz(1443, 2425), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3900PolyExtStep::AndEqz(1444, 2426), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3901PolyExtStep::AndEqz(1445, 935), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3902PolyExtStep::AndEqz(1446, 2427), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3903PolyExtStep::AndEqz(1447, 1143), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :109:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3904PolyExtStep::AndEqz(1448, 1148), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :109:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3905PolyExtStep::AndCond(1441, 1057, 1449), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3906PolyExtStep::Sub(1064, 1), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:22) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3907PolyExtStep::AndEqz(0, 1005), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :112:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3908PolyExtStep::AndEqz(1451, 2428), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:22) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3909PolyExtStep::AndCond(1450, 2420, 1452), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3910PolyExtStep::AndEqz(1453, 1429), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3911PolyExtStep::AndCond(1351, 377, 1454), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
3912PolyExtStep::Sub(2204, 24), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :140:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3913PolyExtStep::Sub(16, 899), // loc(callsite( builtin Sub at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:14) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3914PolyExtStep::Sub(16, 902), // loc(callsite( builtin Sub at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:14) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3915PolyExtStep::AndEqz(1353, 2429), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :140:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3916PolyExtStep::AndEqz(1456, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3917PolyExtStep::AndEqz(1457, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3918PolyExtStep::AndEqz(1458, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3919PolyExtStep::AndEqz(1459, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3920PolyExtStep::AndEqz(1460, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3921PolyExtStep::AndEqz(1461, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :40:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3922PolyExtStep::AndEqz(1462, 2258), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3923PolyExtStep::AndEqz(1463, 2269), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3924PolyExtStep::AndEqz(1464, 2275), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3925PolyExtStep::AndEqz(1465, 2277), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3926PolyExtStep::AndEqz(1466, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :119:26) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :142:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3927PolyExtStep::AndEqz(1467, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :120:24) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :142:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3928PolyExtStep::Mul(935, 29), // loc(callsite( builtin Mul at callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:24) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :142:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3929PolyExtStep::Add(1845, 2432), // loc(callsite( builtin Add at callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :142:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3930PolyExtStep::Sub(902, 2433), // loc(callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:11) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :142:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3931PolyExtStep::AndEqz(1468, 2434), // loc(callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:11) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :142:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
3932PolyExtStep::Mul(935, 2430), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:4) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3933PolyExtStep::Mul(936, 899), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:39) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3934PolyExtStep::Add(2435, 2436), // loc(callsite( builtin Add at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:24) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3935PolyExtStep::Mul(935, 2431), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:4) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3936PolyExtStep::Mul(936, 902), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:39) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3937PolyExtStep::Add(2438, 2439), // loc(callsite( builtin Add at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:24) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3938PolyExtStep::AndEqz(1469, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3939PolyExtStep::AndEqz(1470, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :57:27) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3940PolyExtStep::AndEqz(1471, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3941PolyExtStep::AndEqz(1472, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3942PolyExtStep::AndEqz(1473, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3943PolyExtStep::AndEqz(1474, 2279), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3944PolyExtStep::AndEqz(1475, 2280), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3945PolyExtStep::AndEqz(1476, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3946PolyExtStep::Sub(938, 2282), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3947PolyExtStep::AndEqz(1477, 2441), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3948PolyExtStep::Add(2285, 2303), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3949PolyExtStep::Sub(972, 2442), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3950PolyExtStep::AndEqz(1478, 2443), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3951PolyExtStep::Add(2289, 2307), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3952PolyExtStep::Sub(539, 2444), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3953PolyExtStep::AndEqz(1479, 2445), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3954PolyExtStep::AndEqz(1480, 2293), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3955PolyExtStep::AndEqz(1481, 2294), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3956PolyExtStep::AndEqz(1482, 2295), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3957PolyExtStep::AndEqz(1483, 2296), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3958PolyExtStep::AndEqz(1484, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3959PolyExtStep::AndEqz(1485, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3960PolyExtStep::AndEqz(1486, 2300), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3961PolyExtStep::Add(2302, 2310), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3962PolyExtStep::Sub(932, 2446), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3963PolyExtStep::AndEqz(1487, 2447), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3964PolyExtStep::Mul(978, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3965PolyExtStep::Add(2306, 2448), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3966PolyExtStep::Sub(646, 2449), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3967PolyExtStep::AndEqz(1488, 2450), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3968PolyExtStep::AndEqz(1489, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3969PolyExtStep::AndEqz(1490, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3970PolyExtStep::Mul(981, 29), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3971PolyExtStep::Add(2451, 1163), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:21) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3972PolyExtStep::Sub(1154, 2452), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3973PolyExtStep::AndEqz(1491, 2453), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
3974PolyExtStep::Add(1148, 2313), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :127:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3975PolyExtStep::Add(2454, 2318), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :128:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3976PolyExtStep::AndEqz(1492, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3977PolyExtStep::AndEqz(1493, 2320), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3978PolyExtStep::AndEqz(1494, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3979PolyExtStep::AndEqz(1495, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3980PolyExtStep::Mul(987, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3981PolyExtStep::Add(2456, 984), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3982PolyExtStep::Mul(2457, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3983PolyExtStep::Add(2458, 2324), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3984PolyExtStep::Add(2459, 1373), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3985PolyExtStep::Sub(2455, 2460), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3986PolyExtStep::AndEqz(1496, 2461), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3987PolyExtStep::Mul(2457, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3988PolyExtStep::Add(2462, 666), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3989PolyExtStep::Add(1154, 2463), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :133:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3990PolyExtStep::Add(2464, 2331), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :134:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3991PolyExtStep::Add(2465, 2333), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3992PolyExtStep::Add(2466, 2335), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3993PolyExtStep::Add(2467, 2344), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
3994PolyExtStep::AndEqz(1497, 1810), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3995PolyExtStep::AndEqz(1498, 2346), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
3996PolyExtStep::AndEqz(1499, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3997PolyExtStep::AndEqz(1500, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
3998PolyExtStep::Mul(993, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
3999PolyExtStep::Add(2469, 990), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4000PolyExtStep::Mul(2470, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4001PolyExtStep::Add(2471, 2350), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4002PolyExtStep::Add(2472, 1382), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4003PolyExtStep::Sub(2468, 2473), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4004PolyExtStep::AndEqz(1501, 2474), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4005PolyExtStep::Mul(2470, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4006PolyExtStep::Add(2475, 676), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4007PolyExtStep::Add(2476, 47), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4008PolyExtStep::Add(2477, 2357), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4009PolyExtStep::Add(2478, 2359), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4010PolyExtStep::Add(2479, 2361), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4011PolyExtStep::Add(2480, 2366), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4012PolyExtStep::AndEqz(1502, 1811), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4013PolyExtStep::AndEqz(1503, 2368), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4014PolyExtStep::AndEqz(1504, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4015PolyExtStep::AndEqz(1505, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4016PolyExtStep::Mul(999, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4017PolyExtStep::Add(2482, 996), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4018PolyExtStep::Mul(2483, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4019PolyExtStep::Add(2484, 2372), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4020PolyExtStep::Add(2485, 1385), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4021PolyExtStep::Sub(2481, 2486), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4022PolyExtStep::AndEqz(1506, 2487), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4023PolyExtStep::Mul(2483, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4024PolyExtStep::Add(2488, 551), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4025PolyExtStep::Add(2489, 46), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :151:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4026PolyExtStep::Add(2490, 2379), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4027PolyExtStep::AndEqz(1507, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4028PolyExtStep::Sub(2491, 1392), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4029PolyExtStep::Mul(2492, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4030PolyExtStep::AndEqz(1508, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4031PolyExtStep::AndEqz(1509, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4032PolyExtStep::Mul(1005, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4033PolyExtStep::Add(2494, 1002), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4034PolyExtStep::Sub(2493, 2495), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4035PolyExtStep::AndEqz(1510, 2496), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4036PolyExtStep::Sub(1373, 2437), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4037PolyExtStep::AndEqz(1511, 2497), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4038PolyExtStep::Sub(1382, 2440), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4039PolyExtStep::AndEqz(1512, 2498), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4040PolyExtStep::AndEqz(1513, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:30) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4041PolyExtStep::Mul(1008, 16), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:36) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4042PolyExtStep::Sub(1385, 2499), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4043PolyExtStep::AndEqz(1514, 2500), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4044PolyExtStep::Sub(1392, 2499), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4045PolyExtStep::AndEqz(1515, 2501), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4046PolyExtStep::AndEqz(1516, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :69:26) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4047PolyExtStep::Mul(1011, 29), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:25) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4048PolyExtStep::Sub(2440, 2502), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4049PolyExtStep::Mul(2503, 7), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:40) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4050PolyExtStep::AndEqz(1517, 1812), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4051PolyExtStep::Sub(1401, 2504), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4052PolyExtStep::AndEqz(1518, 2505), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4053PolyExtStep::AndEqz(1519, 1813), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4054PolyExtStep::AndEqz(1520, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4055PolyExtStep::Sub(929, 2400), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4056PolyExtStep::AndEqz(1521, 2506), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4057PolyExtStep::Add(932, 1014), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4058PolyExtStep::AndEqz(1522, 1826), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4059PolyExtStep::AndEqz(1523, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4060PolyExtStep::Sub(2507, 2403), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4061PolyExtStep::AndEqz(1524, 2508), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4062PolyExtStep::AndEqz(1525, 1827), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4063PolyExtStep::AndEqz(1526, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4064PolyExtStep::Sub(1148, 2407), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4065PolyExtStep::AndEqz(1527, 2509), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4066PolyExtStep::Add(1154, 1051), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4067PolyExtStep::AndEqz(1528, 1828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4068PolyExtStep::AndEqz(1529, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4069PolyExtStep::Mul(1054, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4070PolyExtStep::Add(2511, 1428), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4071PolyExtStep::Sub(2510, 2512), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4072PolyExtStep::AndEqz(1530, 2513), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4073PolyExtStep::AndEqz(1531, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:26) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4074PolyExtStep::AndEqz(1532, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:38) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4075PolyExtStep::Add(1427, 33), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:19) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4076PolyExtStep::Sub(2514, 1404), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:31) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4077PolyExtStep::Add(1428, 16), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:44) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4078PolyExtStep::Sub(2516, 1411), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:55) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4079PolyExtStep::AndEqz(1533, 1831), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4080PolyExtStep::AndEqz(1534, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4081PolyExtStep::Sub(2515, 2418), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4082PolyExtStep::AndEqz(1535, 2518), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4083PolyExtStep::Add(2517, 1063), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4084PolyExtStep::AndEqz(1536, 1434), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4085PolyExtStep::AndEqz(1537, 1068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4086PolyExtStep::Mul(1066, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4087PolyExtStep::Add(2520, 1430), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4088PolyExtStep::Sub(2519, 2521), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4089PolyExtStep::AndEqz(1538, 2522), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4090PolyExtStep::Sub(1058, 1060), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:37) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4091PolyExtStep::Sub(1148, 2437), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4092PolyExtStep::Sub(1154, 2440), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4093PolyExtStep::Sub(972, 16), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4094PolyExtStep::AndEqz(1436, 2524), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4095PolyExtStep::AndEqz(1540, 2525), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4096PolyExtStep::AndEqz(1541, 2424), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4097PolyExtStep::AndEqz(1542, 2526), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4098PolyExtStep::AndCond(1539, 1057, 1543), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4099PolyExtStep::Sub(2440, 29), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :106:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4100PolyExtStep::Sub(972, 29), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4101PolyExtStep::AndEqz(1228, 2437), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :106:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4102PolyExtStep::AndEqz(1545, 2527), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :106:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4103PolyExtStep::AndEqz(1546, 2425), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4104PolyExtStep::AndEqz(1547, 2426), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4105PolyExtStep::AndEqz(1548, 938), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4106PolyExtStep::AndEqz(1549, 2528), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4107PolyExtStep::AndEqz(1550, 1148), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :109:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4108PolyExtStep::AndEqz(1551, 1154), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :109:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4109PolyExtStep::AndCond(1544, 1060, 1552), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4110PolyExtStep::Sub(1067, 1), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:22) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4111PolyExtStep::AndEqz(0, 1008), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :112:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4112PolyExtStep::AndEqz(1554, 2529), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:22) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4113PolyExtStep::AndCond(1553, 2523, 1555), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4114PolyExtStep::AndCond(1455, 380, 1556), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4115PolyExtStep::Sub(742, 38), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :148:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4116PolyExtStep::AndEqz(0, 2530), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :148:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4117PolyExtStep::AndEqz(1558, 2247), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :148:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4118PolyExtStep::AndEqz(1559, 2204), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :148:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4119PolyExtStep::AndEqz(1560, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4120PolyExtStep::AndEqz(1561, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4121PolyExtStep::AndEqz(1562, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4122PolyExtStep::AndEqz(1563, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4123PolyExtStep::AndEqz(1564, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4124PolyExtStep::AndEqz(1565, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :40:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4125PolyExtStep::Sub(2257, 2195), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4126PolyExtStep::AndEqz(1566, 2531), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4127PolyExtStep::AndEqz(1567, 2269), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4128PolyExtStep::AndEqz(1568, 2275), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4129PolyExtStep::AndEqz(1569, 2277), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4130PolyExtStep::AndEqz(1570, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4131PolyExtStep::AndEqz(1571, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :57:27) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4132PolyExtStep::AndEqz(1572, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4133PolyExtStep::AndEqz(1573, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4134PolyExtStep::AndEqz(1574, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4135PolyExtStep::AndEqz(1575, 2279), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4136PolyExtStep::AndEqz(1576, 2280), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4137PolyExtStep::AndEqz(1577, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4138PolyExtStep::AndEqz(1578, 2283), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4139PolyExtStep::AndEqz(1579, 2288), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4140PolyExtStep::AndEqz(1580, 2292), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4141PolyExtStep::AndEqz(1581, 2293), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4142PolyExtStep::AndEqz(1582, 2294), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4143PolyExtStep::AndEqz(1583, 2295), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4144PolyExtStep::AndEqz(1584, 2296), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4145PolyExtStep::AndEqz(1585, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4146PolyExtStep::AndEqz(1586, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4147PolyExtStep::AndEqz(1587, 2300), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4148PolyExtStep::AndEqz(1588, 2305), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4149PolyExtStep::AndEqz(1589, 2309), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4150PolyExtStep::AndEqz(1590, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4151PolyExtStep::AndEqz(1591, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4152PolyExtStep::AndEqz(1592, 2312), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4153PolyExtStep::AndEqz(1593, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4154PolyExtStep::AndEqz(1594, 2320), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4155PolyExtStep::AndEqz(1595, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4156PolyExtStep::AndEqz(1596, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4157PolyExtStep::AndEqz(1597, 2327), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4158PolyExtStep::AndEqz(1598, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4159PolyExtStep::AndEqz(1599, 2346), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4160PolyExtStep::AndEqz(1600, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4161PolyExtStep::AndEqz(1601, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4162PolyExtStep::AndEqz(1602, 2353), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4163PolyExtStep::AndEqz(1603, 1810), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4164PolyExtStep::AndEqz(1604, 2368), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4165PolyExtStep::AndEqz(1605, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4166PolyExtStep::AndEqz(1606, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4167PolyExtStep::AndEqz(1607, 2375), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4168PolyExtStep::AndEqz(1608, 1811), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4169PolyExtStep::AndEqz(1609, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4170PolyExtStep::AndEqz(1610, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4171PolyExtStep::AndEqz(1611, 2385), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4172PolyExtStep::AndEqz(1612, 2386), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4173PolyExtStep::AndEqz(1613, 2387), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4174PolyExtStep::AndEqz(1614, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:30) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4175PolyExtStep::AndEqz(1615, 2389), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4176PolyExtStep::AndEqz(1616, 2390), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4177PolyExtStep::AndEqz(1617, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :69:26) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4178PolyExtStep::AndEqz(1618, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4179PolyExtStep::AndEqz(1619, 2394), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4180PolyExtStep::AndEqz(1620, 1812), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4181PolyExtStep::AndEqz(1621, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4182PolyExtStep::AndEqz(1622, 2397), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4183PolyExtStep::AndEqz(1623, 1813), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4184PolyExtStep::AndEqz(1624, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4185PolyExtStep::AndEqz(1625, 2401), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4186PolyExtStep::AndEqz(1626, 1826), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4187PolyExtStep::AndEqz(1627, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4188PolyExtStep::AndEqz(1628, 2404), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4189PolyExtStep::AndEqz(1629, 1827), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4190PolyExtStep::AndEqz(1630, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4191PolyExtStep::AndEqz(1631, 2408), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4192PolyExtStep::AndEqz(1632, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:26) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4193PolyExtStep::AndEqz(1633, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:38) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4194PolyExtStep::AndEqz(1634, 1828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4195PolyExtStep::AndEqz(1635, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4196PolyExtStep::AndEqz(1636, 2415), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4197PolyExtStep::AndEqz(1637, 1831), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4198PolyExtStep::AndEqz(1638, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4199PolyExtStep::AndEqz(1639, 2419), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4200PolyExtStep::AndCond(1640, 1054, 1440), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4201PolyExtStep::AndCond(1641, 1057, 1449), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4202PolyExtStep::AndCond(1642, 2420, 1452), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4203PolyExtStep::AndEqz(1643, 1429), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4204PolyExtStep::AndCond(1557, 383, 1644), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4205PolyExtStep::AndEqz(1559, 2429), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :154:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4206PolyExtStep::AndEqz(1646, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4207PolyExtStep::AndEqz(1647, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4208PolyExtStep::AndEqz(1648, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4209PolyExtStep::AndEqz(1649, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4210PolyExtStep::AndEqz(1650, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4211PolyExtStep::AndEqz(1651, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :40:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4212PolyExtStep::AndEqz(1652, 2531), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4213PolyExtStep::AndEqz(1653, 2269), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4214PolyExtStep::AndEqz(1654, 2275), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4215PolyExtStep::AndEqz(1655, 2277), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4216PolyExtStep::AndEqz(1656, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :119:26) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4217PolyExtStep::AndEqz(1657, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :120:24) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4218PolyExtStep::AndEqz(1658, 2434), // loc(callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:11) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4219PolyExtStep::AndEqz(1659, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4220PolyExtStep::AndEqz(1660, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :57:27) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4221PolyExtStep::AndEqz(1661, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4222PolyExtStep::AndEqz(1662, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4223PolyExtStep::AndEqz(1663, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4224PolyExtStep::AndEqz(1664, 2279), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4225PolyExtStep::AndEqz(1665, 2280), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4226PolyExtStep::AndEqz(1666, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4227PolyExtStep::AndEqz(1667, 2441), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4228PolyExtStep::AndEqz(1668, 2443), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4229PolyExtStep::AndEqz(1669, 2445), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4230PolyExtStep::AndEqz(1670, 2293), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4231PolyExtStep::AndEqz(1671, 2294), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4232PolyExtStep::AndEqz(1672, 2295), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4233PolyExtStep::AndEqz(1673, 2296), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4234PolyExtStep::AndEqz(1674, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4235PolyExtStep::AndEqz(1675, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4236PolyExtStep::AndEqz(1676, 2300), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4237PolyExtStep::AndEqz(1677, 2447), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4238PolyExtStep::AndEqz(1678, 2450), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4239PolyExtStep::AndEqz(1679, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4240PolyExtStep::AndEqz(1680, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4241PolyExtStep::AndEqz(1681, 2453), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4242PolyExtStep::AndEqz(1682, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4243PolyExtStep::AndEqz(1683, 2320), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4244PolyExtStep::AndEqz(1684, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4245PolyExtStep::AndEqz(1685, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4246PolyExtStep::AndEqz(1686, 2461), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4247PolyExtStep::AndEqz(1687, 1810), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4248PolyExtStep::AndEqz(1688, 2346), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4249PolyExtStep::AndEqz(1689, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4250PolyExtStep::AndEqz(1690, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4251PolyExtStep::AndEqz(1691, 2474), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4252PolyExtStep::AndEqz(1692, 1811), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4253PolyExtStep::AndEqz(1693, 2368), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4254PolyExtStep::AndEqz(1694, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4255PolyExtStep::AndEqz(1695, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4256PolyExtStep::AndEqz(1696, 2487), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4257PolyExtStep::AndEqz(1697, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4258PolyExtStep::AndEqz(1698, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4259PolyExtStep::AndEqz(1699, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4260PolyExtStep::AndEqz(1700, 2496), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4261PolyExtStep::AndEqz(1701, 2497), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4262PolyExtStep::AndEqz(1702, 2498), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4263PolyExtStep::AndEqz(1703, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:30) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4264PolyExtStep::AndEqz(1704, 2500), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4265PolyExtStep::AndEqz(1705, 2501), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4266PolyExtStep::AndEqz(1706, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :69:26) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4267PolyExtStep::AndEqz(1707, 1812), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4268PolyExtStep::AndEqz(1708, 2505), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4269PolyExtStep::AndEqz(1709, 1813), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4270PolyExtStep::AndEqz(1710, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4271PolyExtStep::AndEqz(1711, 2506), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4272PolyExtStep::AndEqz(1712, 1826), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4273PolyExtStep::AndEqz(1713, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4274PolyExtStep::AndEqz(1714, 2508), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4275PolyExtStep::AndEqz(1715, 1827), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4276PolyExtStep::AndEqz(1716, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4277PolyExtStep::AndEqz(1717, 2509), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4278PolyExtStep::AndEqz(1718, 1828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4279PolyExtStep::AndEqz(1719, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4280PolyExtStep::AndEqz(1720, 2513), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4281PolyExtStep::AndEqz(1721, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:26) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4282PolyExtStep::AndEqz(1722, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:38) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4283PolyExtStep::AndEqz(1723, 1831), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4284PolyExtStep::AndEqz(1724, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4285PolyExtStep::AndEqz(1725, 2518), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4286PolyExtStep::AndEqz(1726, 1434), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4287PolyExtStep::AndEqz(1727, 1068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4288PolyExtStep::AndEqz(1728, 2522), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4289PolyExtStep::AndCond(1729, 1057, 1543), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4290PolyExtStep::AndCond(1730, 1060, 1552), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4291PolyExtStep::AndCond(1731, 2523, 1555), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4292PolyExtStep::AndCond(1645, 386, 1732), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4293PolyExtStep::Sub(2206, 5), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :162:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4294PolyExtStep::Sub(2204, 1), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :162:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4295PolyExtStep::Sub(33, 905), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4296PolyExtStep::Sub(16, 908), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :77:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4297PolyExtStep::Sub(905, 16), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4298PolyExtStep::Sub(908, 16), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4299PolyExtStep::AndEqz(1352, 2532), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :162:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4300PolyExtStep::AndEqz(1734, 2533), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :162:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4301PolyExtStep::AndEqz(1735, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4302PolyExtStep::AndEqz(1736, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :57:27) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4303PolyExtStep::AndEqz(1737, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4304PolyExtStep::AndEqz(1738, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4305PolyExtStep::AndEqz(1739, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4306PolyExtStep::AndEqz(1740, 2279), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4307PolyExtStep::AndEqz(1741, 2280), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4308PolyExtStep::AndEqz(1742, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4309PolyExtStep::Sub(911, 2282), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4310PolyExtStep::AndEqz(1743, 2538), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4311PolyExtStep::Mul(917, 29), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:40) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4312PolyExtStep::Add(2285, 2539), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4313PolyExtStep::Sub(914, 2540), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4314PolyExtStep::AndEqz(1744, 2541), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4315PolyExtStep::Mul(917, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4316PolyExtStep::Add(2289, 2542), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4317PolyExtStep::Sub(539, 2543), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4318PolyExtStep::AndEqz(1745, 2544), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4319PolyExtStep::AndEqz(1746, 2293), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4320PolyExtStep::AndEqz(1747, 2294), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4321PolyExtStep::AndEqz(1748, 2295), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4322PolyExtStep::AndEqz(1749, 2296), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4323PolyExtStep::AndEqz(1750, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4324PolyExtStep::AndEqz(1751, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4325PolyExtStep::Sub(905, 2299), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4326PolyExtStep::AndEqz(1752, 2545), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4327PolyExtStep::Mul(920, 29), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:40) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4328PolyExtStep::Add(2302, 2546), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4329PolyExtStep::Sub(908, 2547), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4330PolyExtStep::AndEqz(1753, 2548), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4331PolyExtStep::Mul(920, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4332PolyExtStep::Add(2306, 2549), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4333PolyExtStep::Sub(646, 2550), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4334PolyExtStep::AndEqz(1754, 2551), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4335PolyExtStep::AndEqz(1755, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4336PolyExtStep::AndEqz(1756, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4337PolyExtStep::Mul(923, 29), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4338PolyExtStep::Add(2552, 1151), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:21) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4339PolyExtStep::Sub(1143, 2553), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4340PolyExtStep::AndEqz(1757, 2554), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4341PolyExtStep::Add(1137, 2313), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :127:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4342PolyExtStep::Add(2555, 2318), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :128:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4343PolyExtStep::AndEqz(1758, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4344PolyExtStep::AndEqz(1759, 2320), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4345PolyExtStep::AndEqz(1760, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4346PolyExtStep::AndEqz(1761, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4347PolyExtStep::Mul(929, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4348PolyExtStep::Add(2557, 926), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4349PolyExtStep::Mul(2558, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4350PolyExtStep::Add(2559, 2324), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4351PolyExtStep::Add(2560, 1154), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4352PolyExtStep::Sub(2556, 2561), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4353PolyExtStep::AndEqz(1762, 2562), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4354PolyExtStep::Mul(2558, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4355PolyExtStep::Add(2563, 666), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4356PolyExtStep::Add(1143, 2564), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :133:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4357PolyExtStep::Add(2565, 2331), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :134:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4358PolyExtStep::Add(2566, 2333), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4359PolyExtStep::Add(2567, 2335), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4360PolyExtStep::Add(2568, 2344), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4361PolyExtStep::AndEqz(1763, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4362PolyExtStep::AndEqz(1764, 2346), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4363PolyExtStep::AndEqz(1765, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4364PolyExtStep::AndEqz(1766, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4365PolyExtStep::Mul(935, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4366PolyExtStep::Add(2570, 932), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4367PolyExtStep::Mul(2571, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4368PolyExtStep::Add(2572, 2350), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4369PolyExtStep::Add(2573, 1160), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4370PolyExtStep::Sub(2569, 2574), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4371PolyExtStep::AndEqz(1767, 2575), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4372PolyExtStep::Mul(2571, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4373PolyExtStep::Add(2576, 676), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4374PolyExtStep::Mul(923, 16), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4375PolyExtStep::Add(2577, 2578), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :141:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4376PolyExtStep::Add(2579, 47), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4377PolyExtStep::Mul(2282, 920), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:40) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4378PolyExtStep::Sub(2580, 2581), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4379PolyExtStep::Mul(2299, 917), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:75) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4380PolyExtStep::Sub(2582, 2583), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:47) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4381PolyExtStep::Add(2584, 2357), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4382PolyExtStep::Add(2585, 2359), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4383PolyExtStep::Add(2586, 2361), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4384PolyExtStep::Add(2587, 2366), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4385PolyExtStep::AndEqz(1768, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4386PolyExtStep::AndEqz(1769, 2368), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4387PolyExtStep::AndEqz(1770, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4388PolyExtStep::AndEqz(1771, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4389PolyExtStep::Mul(972, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4390PolyExtStep::Add(2589, 938), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4391PolyExtStep::Mul(2590, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4392PolyExtStep::Add(2591, 2372), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4393PolyExtStep::Add(2592, 1373), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4394PolyExtStep::Sub(2588, 2593), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4395PolyExtStep::AndEqz(1772, 2594), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4396PolyExtStep::Mul(2590, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4397PolyExtStep::Add(2595, 551), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4398PolyExtStep::Add(2596, 2578), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :150:16) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4399PolyExtStep::Add(2597, 46), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :151:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4400PolyExtStep::Mul(539, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:30) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4401PolyExtStep::Add(538, 2599), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:22) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4402PolyExtStep::Mul(2600, 920), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:40) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4403PolyExtStep::Sub(2598, 2601), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4404PolyExtStep::Mul(646, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:65) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4405PolyExtStep::Add(632, 2603), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:57) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4406PolyExtStep::Mul(2604, 917), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:75) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4407PolyExtStep::Sub(2602, 2605), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:47) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4408PolyExtStep::Add(2606, 2379), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4409PolyExtStep::AndEqz(1773, 1810), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4410PolyExtStep::Sub(2607, 1382), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4411PolyExtStep::Mul(2608, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4412PolyExtStep::AndEqz(1774, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4413PolyExtStep::AndEqz(1775, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4414PolyExtStep::Mul(978, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4415PolyExtStep::Add(2610, 975), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4416PolyExtStep::Sub(2609, 2611), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4417PolyExtStep::AndEqz(1776, 2612), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4418PolyExtStep::Sub(1154, 899), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4419PolyExtStep::AndEqz(1777, 2613), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4420PolyExtStep::Sub(1160, 902), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4421PolyExtStep::AndEqz(1778, 2614), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4422PolyExtStep::AndEqz(1779, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:30) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4423PolyExtStep::Mul(981, 16), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:36) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4424PolyExtStep::Sub(1373, 2615), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4425PolyExtStep::AndEqz(1780, 2616), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4426PolyExtStep::Sub(1382, 2615), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4427PolyExtStep::AndEqz(1781, 2617), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4428PolyExtStep::AndEqz(1782, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :69:26) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4429PolyExtStep::Mul(984, 29), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:25) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4430PolyExtStep::Sub(902, 2618), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4431PolyExtStep::Mul(2619, 7), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:40) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4432PolyExtStep::AndEqz(1783, 1811), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4433PolyExtStep::Sub(1385, 2620), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4434PolyExtStep::AndEqz(1784, 2621), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4435PolyExtStep::Mul(920, 2534), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:6) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4436PolyExtStep::Mul(921, 905), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:54) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4437PolyExtStep::Add(2622, 2623), // loc(callsite( builtin Add at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:37) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4438PolyExtStep::Mul(920, 2535), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :77:6) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4439PolyExtStep::Mul(921, 908), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :77:54) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4440PolyExtStep::Add(2625, 2626), // loc(callsite( builtin Add at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :77:37) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4441PolyExtStep::AndEqz(1785, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4442PolyExtStep::AndEqz(1786, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4443PolyExtStep::Add(2057, 1392), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4444PolyExtStep::Sub(2624, 2628), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4445PolyExtStep::AndEqz(1787, 2629), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4446PolyExtStep::Add(2627, 987), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4447PolyExtStep::AndEqz(1788, 1812), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4448PolyExtStep::AndEqz(1789, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4449PolyExtStep::Mul(990, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4450PolyExtStep::Add(2631, 1401), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4451PolyExtStep::Sub(2630, 2632), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4452PolyExtStep::AndEqz(1790, 2633), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4453PolyExtStep::Sub(33, 1137), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:16) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4454PolyExtStep::Mul(984, 2634), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:6) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4455PolyExtStep::Mul(985, 1137), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:48) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4456PolyExtStep::Add(2635, 2636), // loc(callsite( builtin Add at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:33) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4457PolyExtStep::Sub(16, 1143), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :82:16) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4458PolyExtStep::Mul(984, 2638), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :82:6) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4459PolyExtStep::Mul(985, 1143), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :82:48) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4460PolyExtStep::Add(2639, 2640), // loc(callsite( builtin Add at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :82:33) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4461PolyExtStep::AndEqz(1791, 1813), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4462PolyExtStep::AndEqz(1792, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4463PolyExtStep::Mul(993, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4464PolyExtStep::Add(2642, 1404), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4465PolyExtStep::Sub(2637, 2643), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4466PolyExtStep::AndEqz(1793, 2644), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4467PolyExtStep::Add(2641, 993), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4468PolyExtStep::AndEqz(1794, 1826), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4469PolyExtStep::AndEqz(1795, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4470PolyExtStep::Add(2062, 1411), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4471PolyExtStep::Sub(2645, 2646), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4472PolyExtStep::AndEqz(1796, 2647), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4473PolyExtStep::AndEqz(1797, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:26) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4474PolyExtStep::AndEqz(1798, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:38) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4475PolyExtStep::Add(1404, 33), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:19) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4476PolyExtStep::Sub(2648, 1392), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:31) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4477PolyExtStep::Add(1411, 16), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:44) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4478PolyExtStep::Sub(2650, 1401), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:55) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4479PolyExtStep::AndEqz(1799, 1827), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4480PolyExtStep::AndEqz(1800, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4481PolyExtStep::Mul(1005, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4482PolyExtStep::Add(2652, 1427), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4483PolyExtStep::Sub(2649, 2653), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4484PolyExtStep::AndEqz(1801, 2654), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4485PolyExtStep::Add(2651, 1005), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4486PolyExtStep::AndEqz(1802, 1828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4487PolyExtStep::AndEqz(1803, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4488PolyExtStep::Mul(1008, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4489PolyExtStep::Add(2656, 1428), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4490PolyExtStep::Sub(2655, 2657), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4491PolyExtStep::AndEqz(1804, 2658), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4492PolyExtStep::Sub(1000, 1002), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:37) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4493PolyExtStep::Sub(1137, 899), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4494PolyExtStep::Sub(1143, 902), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4495PolyExtStep::Sub(911, 16), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4496PolyExtStep::Sub(914, 16), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4497PolyExtStep::AndEqz(0, 905), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :100:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4498PolyExtStep::AndEqz(1806, 908), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :100:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4499PolyExtStep::AndEqz(1807, 2660), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4500PolyExtStep::AndEqz(1808, 2661), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4501PolyExtStep::AndEqz(1809, 2662), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4502PolyExtStep::AndEqz(1810, 2663), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4503PolyExtStep::AndCond(1805, 999, 1811), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4504PolyExtStep::Sub(914, 29), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4505PolyExtStep::AndEqz(0, 899), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :106:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4506PolyExtStep::AndEqz(1813, 2248), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :106:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4507PolyExtStep::AndEqz(1814, 2536), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4508PolyExtStep::AndEqz(1815, 2537), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4509PolyExtStep::AndEqz(1816, 911), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4510PolyExtStep::AndEqz(1817, 2664), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4511PolyExtStep::AndEqz(1818, 1137), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :109:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4512PolyExtStep::AndEqz(1819, 1143), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :109:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4513PolyExtStep::AndCond(1812, 1002, 1820), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4514PolyExtStep::Sub(981, 984), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :112:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4515PolyExtStep::Sub(1009, 1), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:22) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4516PolyExtStep::AndEqz(0, 2665), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :112:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4517PolyExtStep::AndEqz(1822, 2666), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:22) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4518PolyExtStep::AndCond(1821, 2659, 1823), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4519PolyExtStep::AndEqz(1824, 1829), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4520PolyExtStep::AndEqz(1825, 1429), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4521PolyExtStep::AndCond(1733, 389, 1826), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4522PolyExtStep::AndEqz(1353, 2533), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :167:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4523PolyExtStep::AndEqz(1828, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4524PolyExtStep::AndEqz(1829, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :57:27) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4525PolyExtStep::AndEqz(1830, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4526PolyExtStep::AndEqz(1831, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4527PolyExtStep::AndEqz(1832, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4528PolyExtStep::AndEqz(1833, 2279), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4529PolyExtStep::AndEqz(1834, 2280), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4530PolyExtStep::AndEqz(1835, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4531PolyExtStep::AndEqz(1836, 2538), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4532PolyExtStep::AndEqz(1837, 2541), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4533PolyExtStep::AndEqz(1838, 2544), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4534PolyExtStep::AndEqz(1839, 2293), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4535PolyExtStep::AndEqz(1840, 2294), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4536PolyExtStep::AndEqz(1841, 2295), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4537PolyExtStep::AndEqz(1842, 2296), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4538PolyExtStep::AndEqz(1843, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4539PolyExtStep::AndEqz(1844, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4540PolyExtStep::AndEqz(1845, 2545), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4541PolyExtStep::AndEqz(1846, 2548), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4542PolyExtStep::AndEqz(1847, 2551), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4543PolyExtStep::AndEqz(1848, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4544PolyExtStep::AndEqz(1849, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4545PolyExtStep::AndEqz(1850, 2554), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4546PolyExtStep::AndEqz(1851, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4547PolyExtStep::AndEqz(1852, 2320), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4548PolyExtStep::AndEqz(1853, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4549PolyExtStep::AndEqz(1854, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4550PolyExtStep::AndEqz(1855, 2562), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4551PolyExtStep::AndEqz(1856, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4552PolyExtStep::AndEqz(1857, 2346), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4553PolyExtStep::AndEqz(1858, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4554PolyExtStep::AndEqz(1859, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4555PolyExtStep::AndEqz(1860, 2575), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4556PolyExtStep::Add(2577, 47), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4557PolyExtStep::Add(2667, 2357), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4558PolyExtStep::Add(2668, 2359), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4559PolyExtStep::Add(2669, 2361), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4560PolyExtStep::Add(2670, 2366), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4561PolyExtStep::AndEqz(1861, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4562PolyExtStep::AndEqz(1862, 2368), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4563PolyExtStep::AndEqz(1863, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4564PolyExtStep::AndEqz(1864, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4565PolyExtStep::Sub(2671, 2593), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4566PolyExtStep::AndEqz(1865, 2672), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4567PolyExtStep::Add(2596, 46), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :151:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4568PolyExtStep::Add(2673, 2379), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4569PolyExtStep::AndEqz(1866, 1810), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4570PolyExtStep::Sub(2674, 1382), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4571PolyExtStep::Mul(2675, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4572PolyExtStep::AndEqz(1867, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4573PolyExtStep::AndEqz(1868, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4574PolyExtStep::Sub(2676, 2611), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4575PolyExtStep::AndEqz(1869, 2677), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4576PolyExtStep::AndEqz(1870, 2613), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4577PolyExtStep::AndEqz(1871, 2614), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4578PolyExtStep::AndEqz(1872, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:30) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4579PolyExtStep::AndEqz(1873, 2616), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4580PolyExtStep::AndEqz(1874, 2617), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4581PolyExtStep::AndEqz(1875, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :69:26) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4582PolyExtStep::AndEqz(1876, 1811), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4583PolyExtStep::AndEqz(1877, 2621), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4584PolyExtStep::AndEqz(1878, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4585PolyExtStep::AndEqz(1879, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4586PolyExtStep::Sub(905, 2628), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4587PolyExtStep::AndEqz(1880, 2678), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4588PolyExtStep::Add(908, 987), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4589PolyExtStep::AndEqz(1881, 1812), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4590PolyExtStep::AndEqz(1882, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4591PolyExtStep::Sub(2679, 2632), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4592PolyExtStep::AndEqz(1883, 2680), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4593PolyExtStep::AndEqz(1884, 1813), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4594PolyExtStep::AndEqz(1885, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4595PolyExtStep::Sub(1137, 2643), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4596PolyExtStep::AndEqz(1886, 2681), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4597PolyExtStep::Add(1143, 993), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4598PolyExtStep::AndEqz(1887, 1826), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4599PolyExtStep::AndEqz(1888, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4600PolyExtStep::Sub(2682, 2646), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4601PolyExtStep::AndEqz(1889, 2683), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4602PolyExtStep::AndEqz(1890, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:26) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4603PolyExtStep::AndEqz(1891, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:38) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4604PolyExtStep::AndEqz(1892, 1827), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4605PolyExtStep::AndEqz(1893, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4606PolyExtStep::AndEqz(1894, 2654), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4607PolyExtStep::AndEqz(1895, 1828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4608PolyExtStep::AndEqz(1896, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4609PolyExtStep::AndEqz(1897, 2658), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4610PolyExtStep::AndCond(1898, 999, 1811), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4611PolyExtStep::AndEqz(1443, 2536), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4612PolyExtStep::AndEqz(1900, 2537), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4613PolyExtStep::AndEqz(1901, 911), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4614PolyExtStep::AndEqz(1902, 2664), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4615PolyExtStep::AndEqz(1903, 1137), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :109:17) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4616PolyExtStep::AndEqz(1904, 1143), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :109:17) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4617PolyExtStep::AndCond(1899, 1002, 1905), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4618PolyExtStep::AndEqz(0, 981), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :112:17) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4619PolyExtStep::AndEqz(1907, 2666), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:22) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4620PolyExtStep::AndCond(1906, 2659, 1908), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4621PolyExtStep::AndEqz(1909, 1829), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4622PolyExtStep::AndEqz(1910, 1429), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4623PolyExtStep::AndCond(1827, 392, 1911), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4624PolyExtStep::Sub(2206, 3), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :172:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4625PolyExtStep::AndEqz(1352, 2684), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :172:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4626PolyExtStep::AndEqz(1913, 2533), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :172:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4627PolyExtStep::AndEqz(1914, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4628PolyExtStep::AndEqz(1915, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :57:27) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4629PolyExtStep::AndEqz(1916, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4630PolyExtStep::AndEqz(1917, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4631PolyExtStep::AndEqz(1918, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4632PolyExtStep::AndEqz(1919, 2279), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4633PolyExtStep::AndEqz(1920, 2280), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4634PolyExtStep::AndEqz(1921, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4635PolyExtStep::AndEqz(1922, 2538), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4636PolyExtStep::AndEqz(1923, 2541), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4637PolyExtStep::AndEqz(1924, 2544), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4638PolyExtStep::AndEqz(1925, 2293), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4639PolyExtStep::AndEqz(1926, 2294), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4640PolyExtStep::AndEqz(1927, 2295), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4641PolyExtStep::AndEqz(1928, 2296), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4642PolyExtStep::AndEqz(1929, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4643PolyExtStep::AndEqz(1930, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4644PolyExtStep::AndEqz(1931, 2545), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4645PolyExtStep::AndEqz(1932, 2548), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4646PolyExtStep::AndEqz(1933, 2551), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4647PolyExtStep::AndEqz(1934, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4648PolyExtStep::AndEqz(1935, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4649PolyExtStep::AndEqz(1936, 2554), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4650PolyExtStep::AndEqz(1937, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4651PolyExtStep::AndEqz(1938, 2320), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4652PolyExtStep::AndEqz(1939, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4653PolyExtStep::AndEqz(1940, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4654PolyExtStep::AndEqz(1941, 2562), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4655PolyExtStep::AndEqz(1942, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4656PolyExtStep::AndEqz(1943, 2346), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4657PolyExtStep::AndEqz(1944, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4658PolyExtStep::AndEqz(1945, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4659PolyExtStep::AndEqz(1946, 2575), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4660PolyExtStep::AndEqz(1947, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4661PolyExtStep::AndEqz(1948, 2368), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4662PolyExtStep::AndEqz(1949, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4663PolyExtStep::AndEqz(1950, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4664PolyExtStep::AndEqz(1951, 2594), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4665PolyExtStep::AndEqz(1952, 1810), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4666PolyExtStep::AndEqz(1953, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4667PolyExtStep::AndEqz(1954, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4668PolyExtStep::AndEqz(1955, 2612), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4669PolyExtStep::AndEqz(1956, 2613), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4670PolyExtStep::AndEqz(1957, 2614), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4671PolyExtStep::AndEqz(1958, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:30) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4672PolyExtStep::AndEqz(1959, 2616), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4673PolyExtStep::AndEqz(1960, 2617), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4674PolyExtStep::AndEqz(1961, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :69:26) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4675PolyExtStep::AndEqz(1962, 1811), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4676PolyExtStep::AndEqz(1963, 2621), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4677PolyExtStep::AndEqz(1964, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4678PolyExtStep::AndEqz(1965, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4679PolyExtStep::AndEqz(1966, 2629), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4680PolyExtStep::AndEqz(1967, 1812), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4681PolyExtStep::AndEqz(1968, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4682PolyExtStep::AndEqz(1969, 2633), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4683PolyExtStep::AndEqz(1970, 1813), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4684PolyExtStep::AndEqz(1971, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4685PolyExtStep::AndEqz(1972, 2644), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4686PolyExtStep::AndEqz(1973, 1826), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4687PolyExtStep::AndEqz(1974, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4688PolyExtStep::AndEqz(1975, 2647), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4689PolyExtStep::AndEqz(1976, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:26) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4690PolyExtStep::AndEqz(1977, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:38) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4691PolyExtStep::AndEqz(1978, 1827), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4692PolyExtStep::AndEqz(1979, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4693PolyExtStep::AndEqz(1980, 2654), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4694PolyExtStep::AndEqz(1981, 1828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4695PolyExtStep::AndEqz(1982, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4696PolyExtStep::AndEqz(1983, 2658), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4697PolyExtStep::AndCond(1984, 999, 1811), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4698PolyExtStep::AndCond(1985, 1002, 1820), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4699PolyExtStep::AndCond(1986, 2659, 1823), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4700PolyExtStep::AndEqz(1987, 1829), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4701PolyExtStep::AndEqz(1988, 1429), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4702PolyExtStep::AndCond(1912, 395, 1989), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4703PolyExtStep::Sub(2206, 2), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :177:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4704PolyExtStep::AndEqz(1352, 2685), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :177:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4705PolyExtStep::AndEqz(1991, 2533), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :177:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4706PolyExtStep::AndEqz(1992, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4707PolyExtStep::AndEqz(1993, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :57:27) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4708PolyExtStep::AndEqz(1994, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4709PolyExtStep::AndEqz(1995, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4710PolyExtStep::AndEqz(1996, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4711PolyExtStep::AndEqz(1997, 2279), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4712PolyExtStep::AndEqz(1998, 2280), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4713PolyExtStep::AndEqz(1999, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4714PolyExtStep::AndEqz(2000, 2538), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4715PolyExtStep::AndEqz(2001, 2541), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4716PolyExtStep::AndEqz(2002, 2544), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4717PolyExtStep::AndEqz(2003, 2293), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4718PolyExtStep::AndEqz(2004, 2294), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4719PolyExtStep::AndEqz(2005, 2295), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4720PolyExtStep::AndEqz(2006, 2296), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4721PolyExtStep::AndEqz(2007, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4722PolyExtStep::AndEqz(2008, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4723PolyExtStep::AndEqz(2009, 2545), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4724PolyExtStep::AndEqz(2010, 2548), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4725PolyExtStep::AndEqz(2011, 2551), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4726PolyExtStep::AndEqz(2012, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4727PolyExtStep::AndEqz(2013, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4728PolyExtStep::AndEqz(2014, 2554), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4729PolyExtStep::AndEqz(2015, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4730PolyExtStep::AndEqz(2016, 2320), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4731PolyExtStep::AndEqz(2017, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4732PolyExtStep::AndEqz(2018, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4733PolyExtStep::AndEqz(2019, 2562), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4734PolyExtStep::AndEqz(2020, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4735PolyExtStep::AndEqz(2021, 2346), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4736PolyExtStep::AndEqz(2022, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4737PolyExtStep::AndEqz(2023, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4738PolyExtStep::AndEqz(2024, 2575), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4739PolyExtStep::AndEqz(2025, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4740PolyExtStep::AndEqz(2026, 2368), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4741PolyExtStep::AndEqz(2027, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4742PolyExtStep::AndEqz(2028, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4743PolyExtStep::AndEqz(2029, 2672), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4744PolyExtStep::AndEqz(2030, 1810), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4745PolyExtStep::AndEqz(2031, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4746PolyExtStep::AndEqz(2032, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
4747PolyExtStep::AndEqz(2033, 2677), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4748PolyExtStep::AndEqz(2034, 2613), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4749PolyExtStep::AndEqz(2035, 2614), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4750PolyExtStep::AndEqz(2036, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:30) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4751PolyExtStep::AndEqz(2037, 2616), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4752PolyExtStep::AndEqz(2038, 2617), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4753PolyExtStep::AndEqz(2039, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :69:26) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4754PolyExtStep::AndEqz(2040, 1811), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4755PolyExtStep::AndEqz(2041, 2621), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4756PolyExtStep::AndEqz(2042, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4757PolyExtStep::AndEqz(2043, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4758PolyExtStep::AndEqz(2044, 2678), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4759PolyExtStep::AndEqz(2045, 1812), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4760PolyExtStep::AndEqz(2046, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4761PolyExtStep::AndEqz(2047, 2680), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4762PolyExtStep::AndEqz(2048, 1813), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4763PolyExtStep::AndEqz(2049, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4764PolyExtStep::AndEqz(2050, 2681), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4765PolyExtStep::AndEqz(2051, 1826), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4766PolyExtStep::AndEqz(2052, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4767PolyExtStep::AndEqz(2053, 2683), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4768PolyExtStep::AndEqz(2054, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:26) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4769PolyExtStep::AndEqz(2055, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:38) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4770PolyExtStep::AndEqz(2056, 1827), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4771PolyExtStep::AndEqz(2057, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4772PolyExtStep::AndEqz(2058, 2654), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4773PolyExtStep::AndEqz(2059, 1828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4774PolyExtStep::AndEqz(2060, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4775PolyExtStep::AndEqz(2061, 2658), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4776PolyExtStep::AndCond(2062, 999, 1811), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4777PolyExtStep::AndCond(2063, 1002, 1905), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4778PolyExtStep::AndCond(2064, 2659, 1908), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4779PolyExtStep::AndEqz(2065, 1829), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4780PolyExtStep::AndEqz(2066, 1429), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4781PolyExtStep::AndCond(1990, 398, 2067), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4782PolyExtStep::Mul(1212, 377), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4783PolyExtStep::Sub(16, 1213), // loc(callsite( builtin Sub at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:14) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :144:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4784PolyExtStep::Mul(1212, 2687), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:4) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :144:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4785PolyExtStep::Sub(1, 1212), // loc(callsite( builtin Sub at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:29) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :144:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4786PolyExtStep::Mul(2689, 1213), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:39) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :144:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4787PolyExtStep::Add(2688, 2690), // loc(callsite( builtin Add at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:24) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :144:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4788PolyExtStep::Mul(2691, 380), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4789PolyExtStep::Mul(1212, 383), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4790PolyExtStep::Mul(2691, 386), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4791PolyExtStep::Mul(1204, 389), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4792PolyExtStep::Mul(1204, 392), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4793PolyExtStep::Get(156), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4794PolyExtStep::Mul(2697, 395), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4795PolyExtStep::Mul(2697, 398), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4796PolyExtStep::Add(2686, 2692), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4797PolyExtStep::Add(2700, 2693), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4798PolyExtStep::Add(2701, 2694), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4799PolyExtStep::Add(2702, 2695), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4800PolyExtStep::Add(2703, 2696), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4801PolyExtStep::Add(2704, 2698), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4802PolyExtStep::Add(2705, 2699), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4803PolyExtStep::Mul(1213, 377), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4804PolyExtStep::Sub(16, 1281), // loc(callsite( builtin Sub at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:14) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :144:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4805PolyExtStep::Mul(1212, 2708), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:4) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :144:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4806PolyExtStep::Mul(2689, 1281), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:39) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :144:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4807PolyExtStep::Add(2709, 2710), // loc(callsite( builtin Add at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:24) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :144:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4808PolyExtStep::Mul(2711, 380), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4809PolyExtStep::Mul(1213, 383), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4810PolyExtStep::Mul(2711, 386), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4811PolyExtStep::Mul(1205, 389), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4812PolyExtStep::Mul(1205, 392), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4813PolyExtStep::Mul(2013, 395), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4814PolyExtStep::Mul(2013, 398), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4815PolyExtStep::Add(2707, 2712), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4816PolyExtStep::Add(2719, 2713), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4817PolyExtStep::Add(2720, 2714), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4818PolyExtStep::Add(2721, 2715), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4819PolyExtStep::Add(2722, 2716), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4820PolyExtStep::Add(2723, 2717), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4821PolyExtStep::Add(2724, 2718), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
4822PolyExtStep::AndEqz(2068, 1071), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4823PolyExtStep::Mul(2199, 1072), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4824PolyExtStep::Sub(2726, 1070), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4825PolyExtStep::AndEqz(2069, 2727), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4826PolyExtStep::Mul(1069, 2199), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4827PolyExtStep::AndEqz(2070, 2728), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4828PolyExtStep::Mul(1069, 1072), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4829PolyExtStep::AndEqz(2071, 2729), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4830PolyExtStep::Mul(1070, 2199), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4831PolyExtStep::Sub(1, 1070), // loc(callsite( builtin Sub at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:90) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4832PolyExtStep::Mul(2731, 19), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:102) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4833PolyExtStep::Add(506, 2732), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:85) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4834PolyExtStep::Add(2733, 2730), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:106) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4835PolyExtStep::Sub(2734, 1075), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4836PolyExtStep::AndEqz(2072, 2735), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4837PolyExtStep::Get(775), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4838PolyExtStep::Get(776), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4839PolyExtStep::Sub(1081, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4840PolyExtStep::AndEqz(2073, 2738), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4841PolyExtStep::Sub(1093, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4842PolyExtStep::AndEqz(2074, 2739), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4843PolyExtStep::Sub(1096, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4844PolyExtStep::AndEqz(2075, 2740), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4845PolyExtStep::AndEqz(2076, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4846PolyExtStep::Sub(1078, 1075), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4847PolyExtStep::AndEqz(2077, 2741), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4848PolyExtStep::Sub(1096, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4849PolyExtStep::Sub(2742, 1084), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4850PolyExtStep::Get(777), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :54:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4851PolyExtStep::Get(778), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4852PolyExtStep::Sub(2744, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4853PolyExtStep::AndEqz(2078, 2746), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4854PolyExtStep::Sub(2745, 2743), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4855PolyExtStep::AndEqz(2079, 2747), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4856PolyExtStep::Sub(2736, 2706), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4857PolyExtStep::AndEqz(2080, 2748), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4858PolyExtStep::Sub(2737, 2725), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4859PolyExtStep::AndEqz(2081, 2749), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4860PolyExtStep::Get(779), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4861PolyExtStep::Get(780), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4862PolyExtStep::Sub(2750, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4863PolyExtStep::AndEqz(2082, 2752), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4864PolyExtStep::Get(781), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4865PolyExtStep::Sub(1, 2753), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4866PolyExtStep::Mul(2753, 2754), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4867PolyExtStep::AndEqz(2083, 2755), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4868PolyExtStep::Mul(2753, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4869PolyExtStep::Add(2756, 2751), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4870PolyExtStep::Sub(507, 2757), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4871PolyExtStep::AndEqz(2084, 2758), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4872PolyExtStep::Add(370, 2753), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4873PolyExtStep::Get(782), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4874PolyExtStep::Get(783), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4875PolyExtStep::Sub(2760, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4876PolyExtStep::AndEqz(2085, 2762), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4877PolyExtStep::Get(784), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4878PolyExtStep::Sub(1, 2763), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4879PolyExtStep::Mul(2763, 2764), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4880PolyExtStep::AndEqz(2086, 2765), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4881PolyExtStep::Mul(2763, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4882PolyExtStep::Add(2766, 2761), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4883PolyExtStep::Sub(2759, 2767), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4884PolyExtStep::AndEqz(2087, 2768), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4885PolyExtStep::AndCond(1270, 434, 2088), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
4886PolyExtStep::Sub(1160, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4887PolyExtStep::AndEqz(0, 2769), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4888PolyExtStep::Sub(1373, 542), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4889PolyExtStep::AndEqz(2090, 2770), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4890PolyExtStep::AndEqz(2091, 497), // loc(callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :8:21) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
4891PolyExtStep::Sub(1, 1829), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4892PolyExtStep::Mul(1829, 2771), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4893PolyExtStep::Sub(7, 1829), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4894PolyExtStep::Mul(2772, 2773), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4895PolyExtStep::Sub(6, 1829), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4896PolyExtStep::Mul(2774, 2775), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4897PolyExtStep::AndEqz(2092, 2776), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4898PolyExtStep::Sub(1830, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4899PolyExtStep::AndEqz(2093, 2777), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4900PolyExtStep::Sub(1429, 502), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4901PolyExtStep::AndEqz(2094, 2778), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4902PolyExtStep::Sub(1, 1430), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4903PolyExtStep::Mul(1430, 2779), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4904PolyExtStep::AndEqz(2095, 2780), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4905PolyExtStep::Mul(370, 1431), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4906PolyExtStep::Sub(2781, 2779), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4907PolyExtStep::AndEqz(2096, 2782), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4908PolyExtStep::Mul(1430, 370), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4909PolyExtStep::AndEqz(2097, 2783), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4910PolyExtStep::Mul(1430, 1431), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4911PolyExtStep::AndEqz(2098, 2784), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4912PolyExtStep::AndEqz(2099, 1430), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:19) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4913PolyExtStep::Sub(1432, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4914PolyExtStep::AndEqz(2100, 2785), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4915PolyExtStep::Mul(1439, 5), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:4) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4916PolyExtStep::Add(2786, 1829), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:12) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4917PolyExtStep::Sub(2787, 368), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4918PolyExtStep::AndEqz(2101, 2788), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
4919PolyExtStep::Add(503, 1439), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :73:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4920PolyExtStep::AndEqz(2102, 1829), // loc(callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :29:17) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
4921PolyExtStep::Sub(1900, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4922PolyExtStep::AndEqz(2103, 2790), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4923PolyExtStep::AndEqz(2104, 2280), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4924PolyExtStep::Sub(594, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4925PolyExtStep::AndEqz(2105, 2791), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4926PolyExtStep::AndEqz(2106, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4927PolyExtStep::Sub(1440, 2789), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4928PolyExtStep::AndEqz(2107, 2792), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4929PolyExtStep::Sub(2278, 601), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4930PolyExtStep::AndEqz(2108, 2793), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4931PolyExtStep::Sub(539, 608), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4932PolyExtStep::AndEqz(2109, 2794), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
4933PolyExtStep::Sub(594, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4934PolyExtStep::Sub(2795, 538), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4935PolyExtStep::AndEqz(2110, 2294), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4936PolyExtStep::Sub(622, 2796), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4937PolyExtStep::AndEqz(2111, 2797), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4938PolyExtStep::AndEqz(2112, 1377), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4939PolyExtStep::Sub(1, 1382), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4940PolyExtStep::Mul(1382, 2798), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4941PolyExtStep::Sub(7, 1382), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4942PolyExtStep::Mul(2799, 2800), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4943PolyExtStep::Sub(6, 1382), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4944PolyExtStep::Mul(2801, 2802), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4945PolyExtStep::AndEqz(2113, 2803), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4946PolyExtStep::Sub(1, 1383), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4947PolyExtStep::Mul(1383, 2804), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4948PolyExtStep::Sub(7, 1383), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4949PolyExtStep::Mul(2805, 2806), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4950PolyExtStep::Sub(6, 1383), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4951PolyExtStep::Mul(2807, 2808), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4952PolyExtStep::AndEqz(2114, 2809), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4953PolyExtStep::Sub(7, 1385), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4954PolyExtStep::Mul(1387, 2810), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4955PolyExtStep::Sub(6, 1385), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4956PolyExtStep::Mul(2811, 2812), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4957PolyExtStep::AndEqz(2115, 2813), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4958PolyExtStep::Sub(1, 1391), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4959PolyExtStep::Mul(1391, 2814), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4960PolyExtStep::Sub(7, 1391), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4961PolyExtStep::Mul(2815, 2816), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4962PolyExtStep::Sub(6, 1391), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4963PolyExtStep::Mul(2817, 2818), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4964PolyExtStep::AndEqz(2116, 2819), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4965PolyExtStep::Sub(1, 1392), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4966PolyExtStep::Mul(1392, 2820), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4967PolyExtStep::Sub(7, 1392), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4968PolyExtStep::Mul(2821, 2822), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4969PolyExtStep::Sub(6, 1392), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4970PolyExtStep::Mul(2823, 2824), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4971PolyExtStep::AndEqz(2117, 2825), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4972PolyExtStep::AndEqz(2118, 1396), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4973PolyExtStep::Sub(1, 1401), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4974PolyExtStep::Mul(1401, 2826), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4975PolyExtStep::Sub(7, 1401), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4976PolyExtStep::Mul(2827, 2828), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4977PolyExtStep::Sub(6, 1401), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4978PolyExtStep::Mul(2829, 2830), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4979PolyExtStep::AndEqz(2119, 2831), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4980PolyExtStep::Sub(1, 1402), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4981PolyExtStep::Mul(1402, 2832), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4982PolyExtStep::Sub(7, 1402), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4983PolyExtStep::Mul(2833, 2834), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4984PolyExtStep::Sub(6, 1402), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4985PolyExtStep::Mul(2835, 2836), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4986PolyExtStep::AndEqz(2120, 2837), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4987PolyExtStep::AndEqz(2121, 1406), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4988PolyExtStep::AndEqz(2122, 1413), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4989PolyExtStep::Sub(1, 1411), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4990PolyExtStep::Mul(1411, 2838), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4991PolyExtStep::Sub(7, 1411), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4992PolyExtStep::Mul(2839, 2840), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4993PolyExtStep::Sub(6, 1411), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4994PolyExtStep::Mul(2841, 2842), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4995PolyExtStep::AndEqz(2123, 2843), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
4996PolyExtStep::Sub(1, 1424), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4997PolyExtStep::Mul(1424, 2844), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4998PolyExtStep::Sub(7, 1424), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
4999PolyExtStep::Mul(2845, 2846), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5000PolyExtStep::Sub(6, 1424), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5001PolyExtStep::Mul(2847, 2848), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5002PolyExtStep::AndEqz(2124, 2849), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5003PolyExtStep::Sub(1, 1427), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5004PolyExtStep::Mul(1427, 2850), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5005PolyExtStep::Sub(7, 1427), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5006PolyExtStep::Mul(2851, 2852), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5007PolyExtStep::Sub(6, 1427), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5008PolyExtStep::Mul(2853, 2854), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5009PolyExtStep::AndEqz(2125, 2855), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5010PolyExtStep::Sub(1, 1426), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5011PolyExtStep::Mul(1426, 2856), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5012PolyExtStep::AndEqz(2126, 2857), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5013PolyExtStep::Mul(1375, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5014PolyExtStep::Mul(1382, 28), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5015PolyExtStep::Add(2858, 2859), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5016PolyExtStep::Mul(1383, 27), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5017PolyExtStep::Add(2860, 2861), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5018PolyExtStep::Mul(1385, 26), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5019PolyExtStep::Add(2862, 2863), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5020PolyExtStep::Mul(1391, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5021PolyExtStep::Add(2864, 2865), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5022PolyExtStep::Mul(1392, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5023PolyExtStep::Add(2866, 2867), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5024PolyExtStep::Mul(1394, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5025PolyExtStep::Add(2868, 2869), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5026PolyExtStep::Mul(1401, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5027PolyExtStep::Add(2870, 2871), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5028PolyExtStep::Add(2872, 1402), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5029PolyExtStep::Sub(608, 2873), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5030PolyExtStep::AndEqz(2127, 2874), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5031PolyExtStep::Mul(1404, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5032PolyExtStep::Mul(1410, 14), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5033PolyExtStep::Add(2875, 2876), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5034PolyExtStep::Mul(1411, 22), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5035PolyExtStep::Add(2877, 2878), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5036PolyExtStep::Mul(1424, 21), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5037PolyExtStep::Add(2879, 2880), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5038PolyExtStep::Add(2881, 1832), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5039PolyExtStep::Mul(1426, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5040PolyExtStep::Add(2882, 2883), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5041PolyExtStep::Add(2884, 1428), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5042PolyExtStep::Sub(601, 2885), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5043PolyExtStep::AndEqz(2128, 2886), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5044PolyExtStep::Mul(1401, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5045PolyExtStep::Mul(1402, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5046PolyExtStep::Add(2887, 2888), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5047PolyExtStep::Add(2889, 1404), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5048PolyExtStep::Mul(1391, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5049PolyExtStep::Mul(1392, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5050PolyExtStep::Add(2891, 2892), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5051PolyExtStep::Add(2893, 1394), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5052PolyExtStep::Mul(1424, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:17) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5053PolyExtStep::Mul(1427, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:30) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5054PolyExtStep::Add(2895, 2896), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5055PolyExtStep::Add(2897, 1426), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:39) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5056PolyExtStep::Mul(1382, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5057PolyExtStep::Mul(1383, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:38) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5058PolyExtStep::Add(2899, 2900), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5059PolyExtStep::Add(2901, 1385), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:47) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5060PolyExtStep::Mul(1375, 19), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5061PolyExtStep::Add(2903, 2902), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5062PolyExtStep::Mul(1410, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5063PolyExtStep::Add(2905, 1411), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5064PolyExtStep::Mul(1375, 18), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5065PolyExtStep::Mul(2904, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:45) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5066PolyExtStep::Add(2907, 2908), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:36) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5067PolyExtStep::Add(2909, 2894), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:53) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5068PolyExtStep::Mul(1375, 16), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:63) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5069PolyExtStep::Add(506, 2890), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5070PolyExtStep::Sub(2912, 551), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5071PolyExtStep::AndEqz(2129, 2913), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5072PolyExtStep::Sub(632, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5073PolyExtStep::AndEqz(2130, 2914), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5074PolyExtStep::Sub(652, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5075PolyExtStep::AndEqz(2131, 2915), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5076PolyExtStep::Sub(659, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5077PolyExtStep::AndEqz(2132, 2916), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5078PolyExtStep::AndEqz(2133, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5079PolyExtStep::Sub(629, 551), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5080PolyExtStep::AndEqz(2134, 2917), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5081PolyExtStep::Sub(646, 666), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5082PolyExtStep::AndEqz(2135, 2918), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5083PolyExtStep::Sub(649, 673), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5084PolyExtStep::AndEqz(2136, 2919), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5085PolyExtStep::Sub(2320, 639), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5086PolyExtStep::Sub(676, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5087PolyExtStep::AndEqz(2137, 2921), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5088PolyExtStep::Sub(544, 2920), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5089PolyExtStep::AndEqz(2138, 2922), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5090PolyExtStep::Add(666, 2910), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:35) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5091PolyExtStep::Add(673, 2911), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:35) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5092PolyExtStep::Sub(552, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5093PolyExtStep::AndEqz(2139, 2925), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5094PolyExtStep::Sub(1, 556), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5095PolyExtStep::Mul(556, 2926), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5096PolyExtStep::AndEqz(2140, 2927), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5097PolyExtStep::Mul(556, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5098PolyExtStep::Add(2928, 555), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5099PolyExtStep::Sub(2923, 2929), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5100PolyExtStep::AndEqz(2141, 2930), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5101PolyExtStep::Add(2924, 556), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5102PolyExtStep::AndEqz(2142, 565), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5103PolyExtStep::AndEqz(2143, 2091), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5104PolyExtStep::Mul(571, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5105PolyExtStep::Add(2932, 564), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5106PolyExtStep::Sub(2931, 2933), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5107PolyExtStep::AndEqz(2144, 2934), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5108PolyExtStep::AndEqz(2145, 2097), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :81:31) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5109PolyExtStep::AndEqz(2146, 2103), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5110PolyExtStep::Mul(572, 7), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:19) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5111PolyExtStep::Add(2935, 570), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:26) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5112PolyExtStep::Sub(501, 564), // loc(callsite( builtin Sub at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:53) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5113PolyExtStep::Sub(573, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5114PolyExtStep::AndEqz(2147, 2938), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5115PolyExtStep::Sub(574, 2937), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5116PolyExtStep::AndEqz(2148, 2939), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5117PolyExtStep::AndEqz(2149, 2121), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5118PolyExtStep::Mul(564, 576), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5119PolyExtStep::Sub(2940, 2120), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5120PolyExtStep::AndEqz(2150, 2941), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5121PolyExtStep::Mul(575, 564), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5122PolyExtStep::AndEqz(2151, 2942), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5123PolyExtStep::Mul(575, 576), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5124PolyExtStep::AndEqz(2152, 2943), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5125PolyExtStep::AndEqz(2153, 575), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:19) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5126PolyExtStep::AndEqz(2154, 1653), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5127PolyExtStep::Mul(578, 5), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:4) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5128PolyExtStep::Add(2944, 2936), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:12) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5129PolyExtStep::Sub(2945, 555), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5130PolyExtStep::AndEqz(2155, 2946), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5131PolyExtStep::Mul(564, 14), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:19) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5132PolyExtStep::Add(2947, 578), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:30) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5133PolyExtStep::Sub(588, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5134PolyExtStep::AndEqz(2156, 2949), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5135PolyExtStep::Sub(742, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5136PolyExtStep::AndEqz(2157, 2950), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5137PolyExtStep::Sub(743, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5138PolyExtStep::AndEqz(2158, 2951), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5139PolyExtStep::AndEqz(2159, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5140PolyExtStep::Sub(587, 2948), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5141PolyExtStep::AndEqz(2160, 2952), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5142PolyExtStep::Sub(740, 744), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5143PolyExtStep::AndEqz(2161, 2953), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5144PolyExtStep::Sub(741, 745), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5145PolyExtStep::AndEqz(2162, 2954), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5146PolyExtStep::Sub(743, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5147PolyExtStep::Sub(2955, 739), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5148PolyExtStep::AndEqz(2163, 1740), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5149PolyExtStep::Sub(747, 2956), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5150PolyExtStep::AndEqz(2164, 2957), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5151PolyExtStep::Sub(1428, 6), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :86:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5152PolyExtStep::Mul(572, 745), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :87:24) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5153PolyExtStep::Mul(2102, 744), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :87:69) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5154PolyExtStep::Add(2959, 2960), // loc(callsite( builtin Add at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :87:42) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5155PolyExtStep::AndEqz(0, 2958), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :86:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5156PolyExtStep::AndEqz(2166, 2906), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :86:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5157PolyExtStep::AndEqz(2167, 1138), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :88:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5158PolyExtStep::AndEqz(2168, 1144), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :88:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5159PolyExtStep::Mul(1143, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :88:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5160PolyExtStep::Add(2962, 1137), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :88:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5161PolyExtStep::Sub(2961, 2963), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :88:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5162PolyExtStep::AndEqz(2169, 2964), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :88:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5163PolyExtStep::Mul(570, 1143), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :89:23) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5164PolyExtStep::Mul(2096, 1137), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :89:64) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5165PolyExtStep::Add(2965, 2966), // loc(callsite( builtin Add at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :89:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5166PolyExtStep::Sub(1, 760), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :90:27) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5167PolyExtStep::Mul(760, 2968), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :90:27) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5168PolyExtStep::AndEqz(2170, 2969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :90:27) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5169PolyExtStep::AndEqz(2171, 1149), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :91:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5170PolyExtStep::Mul(760, 25), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :92:11) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5171PolyExtStep::Add(2970, 1151), // loc(callsite( builtin Add at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :92:21) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5172PolyExtStep::Sub(2967, 2971), // loc(callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :92:9) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5173PolyExtStep::AndEqz(2172, 2972), // loc(callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :92:9) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5174PolyExtStep::AndEqz(2173, 810), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5175PolyExtStep::AndCond(2165, 377, 2174), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5176PolyExtStep::Sub(2906, 1), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :97:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5177PolyExtStep::AndEqz(2166, 2973), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :97:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5178PolyExtStep::AndEqz(2176, 570), // loc(callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :98:20) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5179PolyExtStep::AndEqz(2177, 2969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :100:27) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5180PolyExtStep::AndEqz(2178, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :101:27) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5181PolyExtStep::Mul(760, 29), // loc(callsite( builtin Mul at callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :102:12) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5182PolyExtStep::Add(2974, 1157), // loc(callsite( builtin Add at callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :102:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5183PolyExtStep::Sub(2961, 2975), // loc(callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :102:10) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5184PolyExtStep::AndEqz(2179, 2976), // loc(callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :102:10) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5185PolyExtStep::AndEqz(2180, 807), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5186PolyExtStep::AndEqz(2181, 808), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5187PolyExtStep::AndEqz(2182, 809), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5188PolyExtStep::AndCond(2175, 380, 2183), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5189PolyExtStep::Sub(2906, 7), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpLW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :107:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :55:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5190PolyExtStep::AndEqz(2166, 2977), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpLW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :107:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :55:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5191PolyExtStep::AndEqz(2185, 570), // loc(callsite( OpLW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :108:20) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :55:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5192PolyExtStep::AndEqz(2186, 572), // loc(callsite( OpLW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :109:20) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :55:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5193PolyExtStep::AndEqz(2187, 807), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5194PolyExtStep::AndEqz(2188, 808), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5195PolyExtStep::AndEqz(2189, 809), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5196PolyExtStep::AndEqz(2190, 810), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5197PolyExtStep::AndCond(2184, 383, 2191), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5198PolyExtStep::Sub(2906, 5), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpLBU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :114:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :56:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5199PolyExtStep::AndEqz(2166, 2978), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpLBU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :114:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :56:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5200PolyExtStep::AndEqz(2193, 1138), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( OpLBU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :116:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :56:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5201PolyExtStep::AndEqz(2194, 1144), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( OpLBU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :116:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :56:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5202PolyExtStep::AndEqz(2195, 2964), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( OpLBU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :116:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :56:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5203PolyExtStep::AndEqz(2196, 809), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5204PolyExtStep::AndEqz(2197, 810), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5205PolyExtStep::AndCond(2192, 386, 2198), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5206PolyExtStep::Sub(2906, 4), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpLHU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :122:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :57:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5207PolyExtStep::AndEqz(2166, 2979), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpLHU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :122:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :57:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5208PolyExtStep::AndEqz(2200, 570), // loc(callsite( OpLHU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :123:20) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :57:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5209PolyExtStep::AndEqz(2201, 807), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5210PolyExtStep::AndEqz(2202, 808), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5211PolyExtStep::AndEqz(2203, 809), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5212PolyExtStep::AndEqz(2204, 810), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5213PolyExtStep::AndCond(2199, 389, 2205), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5214PolyExtStep::AndCond(2206, 392, 1232), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5215PolyExtStep::AndCond(2207, 395, 1232), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5216PolyExtStep::AndCond(2208, 398, 1232), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5217PolyExtStep::Mul(570, 2013), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :89:23) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5218PolyExtStep::Mul(2096, 2697), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :89:64) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5219PolyExtStep::Add(2980, 2981), // loc(callsite( builtin Add at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :89:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5220PolyExtStep::Mul(1760, 50), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :93:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5221PolyExtStep::Add(2982, 2983), // loc(callsite( builtin Add at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :93:11) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5222PolyExtStep::Mul(2984, 377), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5223PolyExtStep::Mul(2961, 380), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5224PolyExtStep::Mul(744, 383), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5225PolyExtStep::Mul(2982, 386), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5226PolyExtStep::Mul(2961, 389), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5227PolyExtStep::Add(2985, 2986), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5228PolyExtStep::Add(2990, 2987), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5229PolyExtStep::Add(2991, 2988), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5230PolyExtStep::Add(2992, 2989), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5231PolyExtStep::Mul(1760, 16), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :93:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5232PolyExtStep::Mul(2994, 377), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5233PolyExtStep::Mul(2994, 380), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5234PolyExtStep::Mul(745, 383), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5235PolyExtStep::Add(2995, 2996), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5236PolyExtStep::Add(2998, 2997), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5237PolyExtStep::Sub(1, 766), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5238PolyExtStep::Mul(766, 3000), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5239PolyExtStep::AndEqz(2209, 3001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5240PolyExtStep::Mul(2898, 767), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5241PolyExtStep::Sub(3002, 3000), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5242PolyExtStep::AndEqz(2210, 3003), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5243PolyExtStep::Mul(766, 2898), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5244PolyExtStep::AndEqz(2211, 3004), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5245PolyExtStep::Mul(766, 767), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5246PolyExtStep::AndEqz(2212, 3005), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5247PolyExtStep::Mul(3000, 2898), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:11) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5248PolyExtStep::Sub(1, 3000), // loc(callsite( builtin Sub at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:90) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5249PolyExtStep::Mul(3007, 19), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:102) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5250PolyExtStep::Add(506, 3008), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:85) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5251PolyExtStep::Add(3009, 3006), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:106) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5252PolyExtStep::Sub(3010, 768), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5253PolyExtStep::AndEqz(2213, 3011), // loc(callsite( Reg ( <preamble> :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5254PolyExtStep::Sub(761, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5255PolyExtStep::AndEqz(2214, 3012), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5256PolyExtStep::AndEqz(2215, 758), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5257PolyExtStep::Sub(757, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5258PolyExtStep::AndEqz(2216, 3013), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5259PolyExtStep::AndEqz(2217, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5260PolyExtStep::Sub(769, 768), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5261PolyExtStep::AndEqz(2218, 3014), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5262PolyExtStep::Sub(757, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5263PolyExtStep::Sub(3015, 770), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5264PolyExtStep::AndEqz(2219, 1758), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5265PolyExtStep::Sub(737, 3016), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5266PolyExtStep::AndEqz(2220, 3017), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5267PolyExtStep::Sub(762, 2993), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5268PolyExtStep::AndEqz(2221, 3018), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5269PolyExtStep::Sub(781, 2999), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5270PolyExtStep::AndEqz(2222, 3019), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5271PolyExtStep::Sub(764, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5272PolyExtStep::AndEqz(2223, 3020), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5273PolyExtStep::Sub(1, 800), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5274PolyExtStep::Mul(800, 3021), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5275PolyExtStep::AndEqz(2224, 3022), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5276PolyExtStep::Mul(800, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5277PolyExtStep::Add(3023, 798), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5278PolyExtStep::Sub(507, 3024), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5279PolyExtStep::AndEqz(2225, 3025), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5280PolyExtStep::Add(370, 800), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5281PolyExtStep::AndEqz(2226, 2211), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5282PolyExtStep::AndEqz(2227, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5283PolyExtStep::Add(1139, 804), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5284PolyExtStep::Sub(3026, 3027), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5285PolyExtStep::AndEqz(2228, 3028), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5286PolyExtStep::AndCond(2089, 437, 2229), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
5287PolyExtStep::Add(2909, 2898), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :67:53) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :20:32) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5288PolyExtStep::AndEqz(2129, 2121), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :49:36) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5289PolyExtStep::Sub(2890, 2894), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :52:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5290PolyExtStep::AndEqz(0, 3030), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :52:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5291PolyExtStep::Sub(2912, 576), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5292PolyExtStep::AndEqz(2232, 3031), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5293PolyExtStep::Sub(629, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5294PolyExtStep::AndEqz(2233, 3032), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5295PolyExtStep::AndEqz(2234, 2915), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5296PolyExtStep::AndEqz(2235, 2916), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5297PolyExtStep::AndEqz(2236, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5298PolyExtStep::Sub(632, 576), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5299PolyExtStep::AndEqz(2237, 3033), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5300PolyExtStep::AndEqz(2238, 2918), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5301PolyExtStep::AndEqz(2239, 2919), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5302PolyExtStep::Sub(570, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5303PolyExtStep::AndEqz(2240, 3034), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5304PolyExtStep::Sub(572, 2920), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5305PolyExtStep::AndEqz(2241, 3035), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5306PolyExtStep::AndEqz(2242, 676), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5307PolyExtStep::AndEqz(2243, 556), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5308PolyExtStep::AndEqz(2244, 573), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5309PolyExtStep::AndCond(2231, 575, 2245), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5310PolyExtStep::Add(506, 2894), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5311PolyExtStep::AndEqz(0, 3031), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5312PolyExtStep::AndEqz(2247, 3032), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5313PolyExtStep::AndEqz(2248, 2915), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5314PolyExtStep::AndEqz(2249, 2916), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5315PolyExtStep::AndEqz(2250, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5316PolyExtStep::AndEqz(2251, 3033), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5317PolyExtStep::AndEqz(2252, 2918), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5318PolyExtStep::AndEqz(2253, 2919), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5319PolyExtStep::AndEqz(2254, 3034), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5320PolyExtStep::AndEqz(2255, 3035), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5321PolyExtStep::Sub(3036, 577), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5322PolyExtStep::AndEqz(2256, 3037), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5323PolyExtStep::Sub(676, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5324PolyExtStep::AndEqz(2257, 3038), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5325PolyExtStep::Sub(556, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5326PolyExtStep::AndEqz(2258, 3039), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5327PolyExtStep::Sub(563, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5328PolyExtStep::AndEqz(2259, 3040), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5329PolyExtStep::AndEqz(2260, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5330PolyExtStep::Sub(544, 577), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5331PolyExtStep::AndEqz(2261, 3041), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5332PolyExtStep::Sub(552, 564), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5333PolyExtStep::AndEqz(2262, 3042), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5334PolyExtStep::Sub(555, 571), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5335PolyExtStep::AndEqz(2263, 3043), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5336PolyExtStep::Sub(565, 551), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5337PolyExtStep::AndEqz(2264, 2938), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5338PolyExtStep::Sub(574, 3044), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5339PolyExtStep::AndEqz(2265, 3045), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
5340PolyExtStep::AndCond(2246, 2120, 2266), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5341PolyExtStep::Get(443), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
5342PolyExtStep::Mul(3046, 575), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5343PolyExtStep::Mul(3046, 2120), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5344PolyExtStep::Add(3047, 3048), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5345PolyExtStep::Get(449), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
5346PolyExtStep::Mul(3050, 575), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5347PolyExtStep::Mul(3050, 2120), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5348PolyExtStep::Add(3051, 3052), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5349PolyExtStep::Get(497), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
5350PolyExtStep::Mul(3054, 2120), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5351PolyExtStep::Add(3047, 3055), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5352PolyExtStep::Get(503), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
5353PolyExtStep::Mul(3057, 2120), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5354PolyExtStep::Add(3051, 3058), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5355PolyExtStep::Sub(3049, 578), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:17) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5356PolyExtStep::AndEqz(2267, 3060), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:17) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5357PolyExtStep::Sub(3053, 587), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :63:17) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5358PolyExtStep::AndEqz(2268, 3061), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :63:17) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5359PolyExtStep::Sub(3056, 588), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :64:17) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5360PolyExtStep::AndEqz(2269, 3062), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :64:17) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5361PolyExtStep::Sub(3059, 739), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :65:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5362PolyExtStep::AndEqz(2270, 3063), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :65:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5363PolyExtStep::Add(578, 3029), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:35) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5364PolyExtStep::Add(587, 2911), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:35) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5365PolyExtStep::Sub(740, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5366PolyExtStep::AndEqz(2271, 3066), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5367PolyExtStep::Sub(1, 742), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5368PolyExtStep::Mul(742, 3067), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5369PolyExtStep::AndEqz(2272, 3068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5370PolyExtStep::Mul(742, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5371PolyExtStep::Add(3069, 741), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5372PolyExtStep::Sub(3064, 3070), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5373PolyExtStep::AndEqz(2273, 3071), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5374PolyExtStep::Add(3065, 742), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5375PolyExtStep::AndEqz(2274, 2955), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5376PolyExtStep::Sub(1, 745), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5377PolyExtStep::Mul(745, 3073), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5378PolyExtStep::AndEqz(2275, 3074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5379PolyExtStep::Mul(745, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5380PolyExtStep::Add(3075, 744), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5381PolyExtStep::Sub(3072, 3076), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5382PolyExtStep::AndEqz(2276, 3077), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5383PolyExtStep::AndEqz(2277, 2075), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :81:31) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5384PolyExtStep::Sub(1, 747), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5385PolyExtStep::Mul(747, 3078), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5386PolyExtStep::AndEqz(2278, 3079), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5387PolyExtStep::Mul(747, 7), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5388PolyExtStep::Add(3080, 746), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:26) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5389PolyExtStep::Sub(501, 744), // loc(callsite( builtin Sub at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:53) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5390PolyExtStep::AndEqz(2279, 2080), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5391PolyExtStep::Sub(766, 3082), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5392PolyExtStep::AndEqz(2280, 3083), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5393PolyExtStep::Sub(1, 767), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5394PolyExtStep::Mul(767, 3084), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
5395PolyExtStep::AndEqz(2281, 3085), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5396PolyExtStep::Mul(744, 768), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5397PolyExtStep::Sub(3086, 3084), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5398PolyExtStep::AndEqz(2282, 3087), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5399PolyExtStep::Mul(767, 744), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5400PolyExtStep::AndEqz(2283, 3088), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5401PolyExtStep::Mul(767, 768), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5402PolyExtStep::AndEqz(2284, 3089), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5403PolyExtStep::AndEqz(2285, 767), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5404PolyExtStep::Sub(769, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5405PolyExtStep::AndEqz(2286, 3090), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5406PolyExtStep::Mul(761, 5), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:4) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5407PolyExtStep::Add(3091, 3081), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:12) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5408PolyExtStep::Sub(3092, 741), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5409PolyExtStep::AndEqz(2287, 3093), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5410PolyExtStep::Mul(744, 14), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5411PolyExtStep::Add(3094, 761), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:30) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5412PolyExtStep::Sub(771, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5413PolyExtStep::AndEqz(2288, 3096), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5414PolyExtStep::AndEqz(2289, 782), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5415PolyExtStep::Sub(781, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5416PolyExtStep::AndEqz(2290, 3097), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5417PolyExtStep::AndEqz(2291, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5418PolyExtStep::Sub(770, 3095), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5419PolyExtStep::AndEqz(2292, 3098), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5420PolyExtStep::Sub(756, 732), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5421PolyExtStep::AndEqz(2293, 3099), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5422PolyExtStep::Sub(757, 737), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5423PolyExtStep::AndEqz(2294, 3100), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5424PolyExtStep::Sub(781, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5425PolyExtStep::Sub(3101, 772), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5426PolyExtStep::AndEqz(2295, 3020), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5427PolyExtStep::Sub(798, 3102), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5428PolyExtStep::AndEqz(2296, 3103), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5429PolyExtStep::Sub(1428, 51), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :129:18) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5430PolyExtStep::Mul(747, 737), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :130:24) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5431PolyExtStep::Mul(3078, 732), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :130:69) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5432PolyExtStep::Add(3105, 3106), // loc(callsite( builtin Add at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :130:42) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5433PolyExtStep::AndEqz(0, 3104), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :129:18) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5434PolyExtStep::AndEqz(2298, 2906), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :129:18) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5435PolyExtStep::AndEqz(2299, 1138), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :131:27) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5436PolyExtStep::AndEqz(2300, 1144), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :131:27) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5437PolyExtStep::Sub(3107, 2963), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :131:27) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5438PolyExtStep::AndEqz(2301, 3108), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :131:27) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5439PolyExtStep::AndEqz(2302, 1149), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :132:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5440PolyExtStep::AndEqz(2303, 1155), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :132:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5441PolyExtStep::Mul(1154, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :132:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5442PolyExtStep::Add(3109, 1148), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :132:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5443PolyExtStep::Sub(588, 3110), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :132:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5444PolyExtStep::AndEqz(2304, 3111), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :132:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5445PolyExtStep::AndCond(2297, 377, 2305), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5446PolyExtStep::AndEqz(2298, 2973), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpSH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :147:18) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :72:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5447PolyExtStep::AndEqz(2307, 746), // loc(callsite( OpSH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :148:20) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :72:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5448PolyExtStep::AndEqz(2308, 807), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5449PolyExtStep::AndEqz(2309, 808), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5450PolyExtStep::AndEqz(2310, 809), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5451PolyExtStep::AndEqz(2311, 810), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5452PolyExtStep::AndCond(2306, 380, 2312), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5453PolyExtStep::AndEqz(2298, 2977), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpSW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :159:18) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :73:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5454PolyExtStep::AndEqz(2314, 746), // loc(callsite( OpSW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :160:20) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :73:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5455PolyExtStep::AndEqz(2315, 747), // loc(callsite( OpSW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :161:20) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :73:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5456PolyExtStep::AndEqz(2316, 807), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5457PolyExtStep::AndEqz(2317, 808), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5458PolyExtStep::AndEqz(2318, 809), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5459PolyExtStep::AndEqz(2319, 810), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5460PolyExtStep::AndCond(2313, 383, 2320), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5461PolyExtStep::AndCond(2321, 386, 1232), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5462PolyExtStep::AndCond(2322, 389, 1232), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5463PolyExtStep::AndCond(2323, 392, 1232), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5464PolyExtStep::AndCond(2324, 395, 1232), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5465PolyExtStep::AndCond(2325, 398, 1232), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5466PolyExtStep::Mul(746, 2697), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :137:6) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5467PolyExtStep::Mul(2074, 2010), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :137:37) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5468PolyExtStep::Add(3112, 3113), // loc(callsite( builtin Add at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :137:22) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5469PolyExtStep::Mul(2074, 2013), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :138:20) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5470PolyExtStep::Mul(746, 2010), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :138:44) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5471PolyExtStep::Add(3115, 3116), // loc(callsite( builtin Add at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :138:35) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5472PolyExtStep::Mul(3117, 20), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :138:6) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5473PolyExtStep::Add(3114, 3118), // loc(callsite( builtin Add at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :137:41) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5474PolyExtStep::Mul(747, 732), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :141:6) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5475PolyExtStep::Mul(3078, 3119), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :141:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5476PolyExtStep::Add(3120, 3121), // loc(callsite( builtin Add at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :141:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5477PolyExtStep::Mul(3122, 377), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5478PolyExtStep::Mul(3078, 588), // loc(callsite( builtin Mul at callsite( OpSH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :153:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :72:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5479PolyExtStep::Add(3120, 3124), // loc(callsite( builtin Add at callsite( OpSH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :153:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :72:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5480PolyExtStep::Mul(3125, 380), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5481PolyExtStep::Mul(588, 383), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5482PolyExtStep::Add(3123, 3126), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5483PolyExtStep::Add(3128, 3127), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5484PolyExtStep::Mul(3078, 737), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :142:13) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5485PolyExtStep::Mul(747, 3119), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :142:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5486PolyExtStep::Add(3130, 3131), // loc(callsite( builtin Add at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :142:21) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5487PolyExtStep::Mul(3132, 377), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5488PolyExtStep::Mul(747, 588), // loc(callsite( builtin Mul at callsite( OpSH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :154:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :72:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5489PolyExtStep::Add(3130, 3134), // loc(callsite( builtin Add at callsite( OpSH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :154:21) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :72:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5490PolyExtStep::Mul(3135, 380), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5491PolyExtStep::Mul(739, 383), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5492PolyExtStep::Add(3133, 3136), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5493PolyExtStep::Add(3138, 3137), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5494PolyExtStep::Sub(802, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5495PolyExtStep::AndEqz(2326, 3140), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5496PolyExtStep::Sub(820, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5497PolyExtStep::AndEqz(2327, 3141), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5498PolyExtStep::Sub(823, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5499PolyExtStep::AndEqz(2328, 3142), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5500PolyExtStep::AndEqz(2329, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5501PolyExtStep::Sub(800, 3095), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5502PolyExtStep::AndEqz(2330, 3143), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5503PolyExtStep::Sub(823, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5504PolyExtStep::Sub(3144, 804), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5505PolyExtStep::Sub(832, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5506PolyExtStep::AndEqz(2331, 3146), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5507PolyExtStep::Sub(835, 3145), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5508PolyExtStep::AndEqz(2332, 3147), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5509PolyExtStep::Sub(826, 3129), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5510PolyExtStep::AndEqz(2333, 3148), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5511PolyExtStep::Sub(829, 3139), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5512PolyExtStep::AndEqz(2334, 3149), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5513PolyExtStep::AndEqz(2335, 2228), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5514PolyExtStep::AndEqz(2336, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5515PolyExtStep::Mul(844, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5516PolyExtStep::Add(3150, 841), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5517PolyExtStep::Sub(507, 3151), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5518PolyExtStep::AndEqz(2337, 3152), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5519PolyExtStep::Add(370, 844), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5520PolyExtStep::AndEqz(2338, 2218), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5521PolyExtStep::AndEqz(2339, 855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5522PolyExtStep::Mul(853, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5523PolyExtStep::Add(3154, 850), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5524PolyExtStep::Sub(3153, 3155), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5525PolyExtStep::AndEqz(2340, 3156), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5526PolyExtStep::AndCond(2230, 440, 2341), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
5527PolyExtStep::Sub(371, 1), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :54:13) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5528PolyExtStep::Add(368, 370), // loc(callsite( builtin Add at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :56:31) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5529PolyExtStep::Sub(374, 1), // loc(callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :94:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5530PolyExtStep::Sub(371, 5), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :104:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5531PolyExtStep::Sub(371, 4), // loc(callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :137:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5532PolyExtStep::Sub(371, 3), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5533PolyExtStep::Sub(371, 2), // loc(callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :183:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5534PolyExtStep::Sub(1078, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :196:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5535PolyExtStep::AndEqz(0, 3164), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :196:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5536PolyExtStep::Sub(1084, 542), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :196:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5537PolyExtStep::AndEqz(2343, 3165), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :196:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5538PolyExtStep::Sub(1, 362), // loc(callsite( builtin Sub at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:13) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5539PolyExtStep::Mul(362, 3166), // loc(callsite( builtin Mul at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5540PolyExtStep::Mul(362, 322), // loc(callsite( builtin Mul at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :27:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5541PolyExtStep::Mul(3166, 54), // loc(callsite( builtin Mul at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :27:47) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5542PolyExtStep::Add(3168, 3169), // loc(callsite( builtin Add at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :27:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5543PolyExtStep::Add(3170, 1), // loc(callsite( builtin Add at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5544PolyExtStep::Add(3170, 7), // loc(callsite( builtin Add at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5545PolyExtStep::Add(3170, 6), // loc(callsite( builtin Add at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5546PolyExtStep::Add(3170, 5), // loc(callsite( builtin Add at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5547PolyExtStep::Add(3170, 4), // loc(callsite( builtin Add at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5548PolyExtStep::Add(3170, 3), // loc(callsite( builtin Add at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5549PolyExtStep::Add(3170, 2), // loc(callsite( builtin Add at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5550PolyExtStep::Sub(1, 3166), // loc(callsite( builtin Sub at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :32:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5551PolyExtStep::AndEqz(0, 371), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5552PolyExtStep::AndEqz(2345, 3167), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5553PolyExtStep::Sub(807, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5554PolyExtStep::AndEqz(2346, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5555PolyExtStep::Sub(1148, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5556PolyExtStep::AndEqz(2347, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5557PolyExtStep::Sub(810, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5558PolyExtStep::AndEqz(2348, 3181), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5559PolyExtStep::AndEqz(2349, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5560PolyExtStep::Sub(1137, 3170), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5561PolyExtStep::AndEqz(2350, 3182), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5562PolyExtStep::Sub(1143, 1154), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5563PolyExtStep::AndEqz(2351, 3183), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5564PolyExtStep::Sub(809, 811), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5565PolyExtStep::AndEqz(2352, 3184), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5566PolyExtStep::Sub(1160, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5567PolyExtStep::AndEqz(2353, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5568PolyExtStep::AndEqz(2354, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5569PolyExtStep::Sub(1385, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5570PolyExtStep::AndEqz(2355, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5571PolyExtStep::AndEqz(2356, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5572PolyExtStep::Sub(1372, 3171), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5573PolyExtStep::AndEqz(2357, 3187), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5574PolyExtStep::Sub(1375, 1391), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5575PolyExtStep::AndEqz(2358, 3188), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5576PolyExtStep::Sub(1382, 1392), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5577PolyExtStep::AndEqz(2359, 3189), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5578PolyExtStep::Sub(1394, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5579PolyExtStep::AndEqz(2360, 3190), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5580PolyExtStep::Sub(1411, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5581PolyExtStep::AndEqz(2361, 3191), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5582PolyExtStep::Sub(1424, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5583PolyExtStep::AndEqz(2362, 3192), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5584PolyExtStep::AndEqz(2363, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5585PolyExtStep::Sub(1401, 3172), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5586PolyExtStep::AndEqz(2364, 3193), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5587PolyExtStep::Sub(1404, 1427), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5588PolyExtStep::AndEqz(2365, 3194), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5589PolyExtStep::Sub(1410, 1426), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5590PolyExtStep::AndEqz(2366, 3195), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5591PolyExtStep::Sub(1428, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5592PolyExtStep::AndEqz(2367, 3196), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5593PolyExtStep::AndEqz(2368, 1854), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5594PolyExtStep::Sub(1432, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5595PolyExtStep::AndEqz(2369, 3197), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5596PolyExtStep::AndEqz(2370, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5597PolyExtStep::Sub(1829, 3173), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5598PolyExtStep::AndEqz(2371, 3198), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5599PolyExtStep::Sub(1429, 1439), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5600PolyExtStep::AndEqz(2372, 3199), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5601PolyExtStep::Sub(1430, 1440), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5602PolyExtStep::AndEqz(2373, 3200), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5603PolyExtStep::AndEqz(2374, 2790), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5604PolyExtStep::AndEqz(2375, 2795), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5605PolyExtStep::Sub(601, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5606PolyExtStep::AndEqz(2376, 3201), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5607PolyExtStep::AndEqz(2377, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5608PolyExtStep::Sub(538, 3174), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5609PolyExtStep::AndEqz(2378, 3202), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5610PolyExtStep::AndEqz(2379, 2794), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5611PolyExtStep::Sub(591, 615), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5612PolyExtStep::AndEqz(2380, 3203), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5613PolyExtStep::Sub(622, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5614PolyExtStep::AndEqz(2381, 3204), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5615PolyExtStep::AndEqz(2382, 2297), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5616PolyExtStep::Sub(652, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5617PolyExtStep::AndEqz(2383, 3205), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5618PolyExtStep::AndEqz(2384, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5619PolyExtStep::Sub(629, 3175), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5620PolyExtStep::AndEqz(2385, 3206), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5621PolyExtStep::Sub(639, 659), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5622PolyExtStep::AndEqz(2386, 3207), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5623PolyExtStep::AndEqz(2387, 2918), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5624PolyExtStep::Sub(673, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5625PolyExtStep::AndEqz(2388, 3208), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5626PolyExtStep::AndEqz(2389, 1639), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5627PolyExtStep::Sub(556, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5628PolyExtStep::AndEqz(2390, 3209), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5629PolyExtStep::AndEqz(2391, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5630PolyExtStep::Sub(676, 3176), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5631PolyExtStep::AndEqz(2392, 3210), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5632PolyExtStep::Sub(551, 563), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5633PolyExtStep::AndEqz(2393, 3211), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5634PolyExtStep::AndEqz(2394, 3042), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5635PolyExtStep::Sub(571, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5636PolyExtStep::AndEqz(2395, 3212), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5637PolyExtStep::AndEqz(2396, 580), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5638PolyExtStep::AndEqz(2397, 581), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5639PolyExtStep::AndEqz(2398, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5640PolyExtStep::Sub(570, 3177), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5641PolyExtStep::AndEqz(2399, 3213), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5642PolyExtStep::AndEqz(2400, 583), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5643PolyExtStep::AndEqz(2401, 584), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5644PolyExtStep::GetGlobal(0, 33), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5645PolyExtStep::Sub(1154, 3214), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5646PolyExtStep::AndEqz(0, 3215), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5647PolyExtStep::GetGlobal(0, 34), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5648PolyExtStep::Sub(811, 3216), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5649PolyExtStep::AndEqz(2403, 3217), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5650PolyExtStep::GetGlobal(0, 35), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5651PolyExtStep::Sub(1391, 3218), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5652PolyExtStep::AndEqz(2404, 3219), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5653PolyExtStep::GetGlobal(0, 36), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5654PolyExtStep::Sub(1392, 3220), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5655PolyExtStep::AndEqz(2405, 3221), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5656PolyExtStep::GetGlobal(0, 37), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5657PolyExtStep::Sub(1427, 3222), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5658PolyExtStep::AndEqz(2406, 3223), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5659PolyExtStep::GetGlobal(0, 38), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5660PolyExtStep::Sub(1426, 3224), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5661PolyExtStep::AndEqz(2407, 3225), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5662PolyExtStep::GetGlobal(0, 39), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5663PolyExtStep::Sub(1439, 3226), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5664PolyExtStep::AndEqz(2408, 3227), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5665PolyExtStep::GetGlobal(0, 40), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5666PolyExtStep::Sub(1440, 3228), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5667PolyExtStep::AndEqz(2409, 3229), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5668PolyExtStep::GetGlobal(0, 41), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5669PolyExtStep::Sub(608, 3230), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5670PolyExtStep::AndEqz(2410, 3231), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5671PolyExtStep::GetGlobal(0, 42), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5672PolyExtStep::Sub(615, 3232), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5673PolyExtStep::AndEqz(2411, 3233), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5674PolyExtStep::GetGlobal(0, 43), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5675PolyExtStep::Sub(659, 3234), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5676PolyExtStep::AndEqz(2412, 3235), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5677PolyExtStep::GetGlobal(0, 44), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5678PolyExtStep::Sub(666, 3236), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5679PolyExtStep::AndEqz(2413, 3237), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5680PolyExtStep::GetGlobal(0, 45), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5681PolyExtStep::Sub(563, 3238), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5682PolyExtStep::AndEqz(2414, 3239), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5683PolyExtStep::GetGlobal(0, 46), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5684PolyExtStep::Sub(564, 3240), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5685PolyExtStep::AndEqz(2415, 3241), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5686PolyExtStep::GetGlobal(0, 47), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5687PolyExtStep::Sub(577, 3242), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5688PolyExtStep::AndEqz(2416, 3243), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5689PolyExtStep::GetGlobal(0, 48), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5690PolyExtStep::Sub(578, 3244), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5691PolyExtStep::AndEqz(2417, 3245), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5692PolyExtStep::AndCond(2402, 3166, 2418), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :32:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5693PolyExtStep::GetGlobal(0, 54), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5694PolyExtStep::Sub(1154, 3246), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5695PolyExtStep::AndEqz(0, 3247), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5696PolyExtStep::GetGlobal(0, 55), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5697PolyExtStep::Sub(811, 3248), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5698PolyExtStep::AndEqz(2420, 3249), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5699PolyExtStep::GetGlobal(0, 56), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5700PolyExtStep::Sub(1391, 3250), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5701PolyExtStep::AndEqz(2421, 3251), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5702PolyExtStep::GetGlobal(0, 57), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5703PolyExtStep::Sub(1392, 3252), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5704PolyExtStep::AndEqz(2422, 3253), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5705PolyExtStep::GetGlobal(0, 58), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5706PolyExtStep::Sub(1427, 3254), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5707PolyExtStep::AndEqz(2423, 3255), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5708PolyExtStep::GetGlobal(0, 59), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5709PolyExtStep::Sub(1426, 3256), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5710PolyExtStep::AndEqz(2424, 3257), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5711PolyExtStep::GetGlobal(0, 60), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5712PolyExtStep::Sub(1439, 3258), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5713PolyExtStep::AndEqz(2425, 3259), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5714PolyExtStep::GetGlobal(0, 61), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5715PolyExtStep::Sub(1440, 3260), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5716PolyExtStep::AndEqz(2426, 3261), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5717PolyExtStep::GetGlobal(0, 62), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5718PolyExtStep::Sub(608, 3262), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5719PolyExtStep::AndEqz(2427, 3263), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5720PolyExtStep::GetGlobal(0, 63), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5721PolyExtStep::Sub(615, 3264), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5722PolyExtStep::AndEqz(2428, 3265), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5723PolyExtStep::GetGlobal(0, 64), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5724PolyExtStep::Sub(659, 3266), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5725PolyExtStep::AndEqz(2429, 3267), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5726PolyExtStep::GetGlobal(0, 65), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5727PolyExtStep::Sub(666, 3268), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5728PolyExtStep::AndEqz(2430, 3269), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5729PolyExtStep::GetGlobal(0, 66), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5730PolyExtStep::Sub(563, 3270), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5731PolyExtStep::AndEqz(2431, 3271), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5732PolyExtStep::GetGlobal(0, 67), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5733PolyExtStep::Sub(564, 3272), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5734PolyExtStep::AndEqz(2432, 3273), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5735PolyExtStep::GetGlobal(0, 68), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5736PolyExtStep::Sub(577, 3274), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5737PolyExtStep::AndEqz(2433, 3275), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5738PolyExtStep::GetGlobal(0, 69), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5739PolyExtStep::Sub(578, 3276), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5740PolyExtStep::AndEqz(2434, 3277), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5741PolyExtStep::AndCond(2419, 3178, 2435), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :32:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5742PolyExtStep::AndEqz(2436, 587), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5743PolyExtStep::AndEqz(2437, 739), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5744PolyExtStep::AndEqz(2438, 741), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5745PolyExtStep::AndEqz(2439, 743), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5746PolyExtStep::AndEqz(2440, 745), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5747PolyExtStep::AndEqz(2441, 747), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5748PolyExtStep::AndEqz(2442, 766), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5749PolyExtStep::AndEqz(2443, 768), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5750PolyExtStep::AndEqz(2444, 761), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5751PolyExtStep::AndEqz(2445, 771), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5752PolyExtStep::AndEqz(2446, 756), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5753PolyExtStep::AndEqz(2447, 762), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5754PolyExtStep::AndEqz(2448, 732), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5755PolyExtStep::AndEqz(2449, 764), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5756PolyExtStep::AndEqz(2450, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5757PolyExtStep::AndEqz(2451, 804), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5758PolyExtStep::AndEqz(2452, 817), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5759PolyExtStep::AndEqz(2453, 823), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5760PolyExtStep::AndEqz(2454, 829), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5761PolyExtStep::AndEqz(2455, 835), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5762PolyExtStep::AndEqz(2456, 841), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5763PolyExtStep::AndEqz(2457, 847), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5764PolyExtStep::AndEqz(2458, 853), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5765PolyExtStep::AndEqz(2459, 859), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5766PolyExtStep::AndEqz(2460, 896), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5767PolyExtStep::AndEqz(2461, 902), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5768PolyExtStep::AndEqz(2462, 908), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5769PolyExtStep::AndEqz(2463, 914), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5770PolyExtStep::AndEqz(2464, 920), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5771PolyExtStep::AndEqz(2465, 926), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5772PolyExtStep::AndEqz(2466, 932), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5773PolyExtStep::AndEqz(2467, 938), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5774PolyExtStep::AndEqz(2468, 975), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5775PolyExtStep::AndEqz(2469, 981), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5776PolyExtStep::AndEqz(2470, 987), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5777PolyExtStep::AndEqz(2471, 993), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5778PolyExtStep::AndEqz(2472, 999), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5779PolyExtStep::AndEqz(2473, 1005), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5780PolyExtStep::AndEqz(2474, 1011), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5781PolyExtStep::AndEqz(2475, 1017), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5782PolyExtStep::AndCond(2344, 377, 2476), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5783PolyExtStep::AndEqz(0, 3157), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :54:13) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5784PolyExtStep::AndEqz(2478, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :56:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5785PolyExtStep::Mul(3158, 1057), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :56:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5786PolyExtStep::Sub(3278, 1055), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :56:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5787PolyExtStep::AndEqz(2479, 3279), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :56:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5788PolyExtStep::Mul(1054, 3158), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :56:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5789PolyExtStep::AndEqz(2480, 3280), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :56:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5790PolyExtStep::Mul(1054, 1057), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :56:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5791PolyExtStep::AndEqz(2481, 3281), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :56:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5792PolyExtStep::AndEqz(0, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5793PolyExtStep::AndEqz(2483, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5794PolyExtStep::AndEqz(2484, 3181), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5795PolyExtStep::AndEqz(2485, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5796PolyExtStep::Sub(1137, 353), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5797PolyExtStep::AndEqz(2486, 3282), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5798PolyExtStep::AndEqz(2487, 3183), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5799PolyExtStep::AndEqz(2488, 3184), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5800PolyExtStep::Sub(1155, 808), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5801PolyExtStep::AndEqz(2489, 589), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5802PolyExtStep::Sub(588, 3283), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5803PolyExtStep::AndEqz(2490, 3284), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5804PolyExtStep::AndEqz(2491, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5805PolyExtStep::AndEqz(2492, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5806PolyExtStep::AndEqz(2493, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5807PolyExtStep::AndEqz(2494, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5808PolyExtStep::Sub(1372, 354), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5809PolyExtStep::AndEqz(2495, 3285), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5810PolyExtStep::AndEqz(2496, 3188), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5811PolyExtStep::AndEqz(2497, 3189), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5812PolyExtStep::Sub(1385, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5813PolyExtStep::Sub(3286, 1373), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5814PolyExtStep::AndEqz(2498, 1660), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5815PolyExtStep::Sub(740, 3287), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5816PolyExtStep::AndEqz(2499, 3288), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5817PolyExtStep::AndEqz(2500, 1394), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5818PolyExtStep::AndEqz(2501, 1411), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5819PolyExtStep::AndEqz(2502, 1428), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5820PolyExtStep::AndEqz(2503, 1431), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5821PolyExtStep::AndEqz(2504, 1900), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5822PolyExtStep::AndEqz(2505, 594), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5823PolyExtStep::AndEqz(2506, 622), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5824PolyExtStep::AndEqz(2507, 649), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5825PolyExtStep::AndEqz(2508, 673), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5826PolyExtStep::AndEqz(2509, 555), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5827PolyExtStep::AndEqz(2510, 571), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5828PolyExtStep::AndEqz(2511, 575), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5829PolyExtStep::AndEqz(2512, 741), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5830PolyExtStep::AndEqz(2513, 743), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5831PolyExtStep::AndEqz(2514, 745), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5832PolyExtStep::AndEqz(2515, 747), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5833PolyExtStep::AndEqz(2516, 766), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5834PolyExtStep::AndEqz(2517, 768), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5835PolyExtStep::AndCond(2482, 1054, 2518), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5836PolyExtStep::GetGlobal(0, 0), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5837PolyExtStep::GetGlobal(0, 1), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5838PolyExtStep::Sub(810, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5839PolyExtStep::AndEqz(2484, 3291), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5840PolyExtStep::AndEqz(2520, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5841PolyExtStep::Sub(1137, 323), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5842PolyExtStep::AndEqz(2521, 3292), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5843PolyExtStep::AndEqz(2522, 589), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5844PolyExtStep::AndEqz(2523, 3284), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5845PolyExtStep::Sub(1154, 3289), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5846PolyExtStep::AndEqz(2524, 3293), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5847PolyExtStep::Sub(811, 3290), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5848PolyExtStep::AndEqz(2525, 3294), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5849PolyExtStep::GetGlobal(0, 2), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5850PolyExtStep::GetGlobal(0, 3), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5851PolyExtStep::AndEqz(2526, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5852PolyExtStep::AndEqz(2527, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5853PolyExtStep::Sub(1385, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5854PolyExtStep::AndEqz(2528, 3297), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5855PolyExtStep::AndEqz(2529, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5856PolyExtStep::Sub(1372, 324), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5857PolyExtStep::AndEqz(2530, 3298), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5858PolyExtStep::AndEqz(2531, 1660), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5859PolyExtStep::AndEqz(2532, 3288), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5860PolyExtStep::Sub(1391, 3295), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5861PolyExtStep::AndEqz(2533, 3299), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5862PolyExtStep::Sub(1392, 3296), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5863PolyExtStep::AndEqz(2534, 3300), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5864PolyExtStep::GetGlobal(0, 4), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5865PolyExtStep::GetGlobal(0, 5), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5866PolyExtStep::AndEqz(2535, 3190), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5867PolyExtStep::AndEqz(2536, 3191), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5868PolyExtStep::Sub(1424, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5869PolyExtStep::AndEqz(2537, 3303), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5870PolyExtStep::AndEqz(2538, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5871PolyExtStep::Sub(1401, 325), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5872PolyExtStep::AndEqz(2539, 3304), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5873PolyExtStep::Sub(1827, 1402), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5874PolyExtStep::Sub(741, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5875PolyExtStep::AndEqz(2540, 3306), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5876PolyExtStep::Sub(742, 3305), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5877PolyExtStep::AndEqz(2541, 3307), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5878PolyExtStep::Sub(1427, 3301), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5879PolyExtStep::AndEqz(2542, 3308), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5880PolyExtStep::Sub(1426, 3302), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5881PolyExtStep::AndEqz(2543, 3309), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5882PolyExtStep::GetGlobal(0, 6), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5883PolyExtStep::GetGlobal(0, 7), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5884PolyExtStep::AndEqz(2544, 3196), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5885PolyExtStep::AndEqz(2545, 1854), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5886PolyExtStep::Sub(1432, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5887PolyExtStep::AndEqz(2546, 3312), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5888PolyExtStep::AndEqz(2547, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5889PolyExtStep::Sub(1829, 326), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5890PolyExtStep::AndEqz(2548, 3313), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5891PolyExtStep::Sub(2785, 1830), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5892PolyExtStep::AndEqz(2549, 2955), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5893PolyExtStep::Sub(744, 3314), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5894PolyExtStep::AndEqz(2550, 3315), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5895PolyExtStep::Sub(1439, 3310), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5896PolyExtStep::AndEqz(2551, 3316), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5897PolyExtStep::Sub(1440, 3311), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5898PolyExtStep::AndEqz(2552, 3317), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5899PolyExtStep::GetGlobal(0, 8), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5900PolyExtStep::GetGlobal(0, 9), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5901PolyExtStep::AndEqz(2553, 2790), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5902PolyExtStep::AndEqz(2554, 2795), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5903PolyExtStep::Sub(601, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5904PolyExtStep::AndEqz(2555, 3320), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5905PolyExtStep::AndEqz(2556, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5906PolyExtStep::Sub(538, 327), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5907PolyExtStep::AndEqz(2557, 3321), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5908PolyExtStep::Sub(2293, 2278), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5909PolyExtStep::AndEqz(2558, 754), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5910PolyExtStep::Sub(746, 3322), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5911PolyExtStep::AndEqz(2559, 3323), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5912PolyExtStep::Sub(608, 3318), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5913PolyExtStep::AndEqz(2560, 3324), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5914PolyExtStep::Sub(615, 3319), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5915PolyExtStep::AndEqz(2561, 3325), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5916PolyExtStep::GetGlobal(0, 10), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5917PolyExtStep::GetGlobal(0, 11), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5918PolyExtStep::AndEqz(2562, 3204), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5919PolyExtStep::AndEqz(2563, 2297), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5920PolyExtStep::Sub(652, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5921PolyExtStep::AndEqz(2564, 3328), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5922PolyExtStep::AndEqz(2565, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5923PolyExtStep::Sub(629, 328), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5924PolyExtStep::AndEqz(2566, 3329), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5925PolyExtStep::Sub(2915, 632), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5926PolyExtStep::AndEqz(2567, 1745), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5927PolyExtStep::Sub(760, 3330), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5928PolyExtStep::AndEqz(2568, 3331), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5929PolyExtStep::Sub(659, 3326), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5930PolyExtStep::AndEqz(2569, 3332), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5931PolyExtStep::Sub(666, 3327), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5932PolyExtStep::AndEqz(2570, 3333), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5933PolyExtStep::GetGlobal(0, 12), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5934PolyExtStep::GetGlobal(0, 13), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5935PolyExtStep::AndEqz(2571, 3208), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5936PolyExtStep::AndEqz(2572, 1639), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5937PolyExtStep::Sub(556, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5938PolyExtStep::AndEqz(2573, 3336), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5939PolyExtStep::AndEqz(2574, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5940PolyExtStep::Sub(676, 329), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5941PolyExtStep::AndEqz(2575, 3337), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5942PolyExtStep::Sub(3039, 544), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5943PolyExtStep::Sub(766, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5944PolyExtStep::AndEqz(2576, 3339), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5945PolyExtStep::Sub(767, 3338), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5946PolyExtStep::AndEqz(2577, 3340), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5947PolyExtStep::Sub(563, 3334), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5948PolyExtStep::AndEqz(2578, 3341), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5949PolyExtStep::Sub(564, 3335), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5950PolyExtStep::AndEqz(2579, 3342), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5951PolyExtStep::GetGlobal(0, 14), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5952PolyExtStep::GetGlobal(0, 15), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5953PolyExtStep::AndEqz(2580, 3212), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5954PolyExtStep::AndEqz(2581, 580), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5955PolyExtStep::Sub(576, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5956PolyExtStep::AndEqz(2582, 3345), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5957PolyExtStep::AndEqz(2583, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5958PolyExtStep::Sub(570, 330), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5959PolyExtStep::AndEqz(2584, 3346), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
5960PolyExtStep::Sub(768, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5961PolyExtStep::AndEqz(2585, 3347), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5962PolyExtStep::Sub(769, 586), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5963PolyExtStep::AndEqz(2586, 3348), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
5964PolyExtStep::Sub(577, 3343), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5965PolyExtStep::AndEqz(2587, 3349), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5966PolyExtStep::Sub(578, 3344), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5967PolyExtStep::AndEqz(2588, 3350), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
5968PolyExtStep::AndCond(2519, 1055, 2589), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
5969PolyExtStep::AndEqz(2590, 761), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5970PolyExtStep::AndEqz(2591, 771), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5971PolyExtStep::AndEqz(2592, 756), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5972PolyExtStep::AndEqz(2593, 762), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5973PolyExtStep::AndEqz(2594, 732), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5974PolyExtStep::AndEqz(2595, 764), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5975PolyExtStep::AndEqz(2596, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5976PolyExtStep::AndEqz(2597, 804), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5977PolyExtStep::AndEqz(2598, 817), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5978PolyExtStep::AndEqz(2599, 823), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5979PolyExtStep::AndEqz(2600, 829), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5980PolyExtStep::AndEqz(2601, 835), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5981PolyExtStep::AndEqz(2602, 841), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5982PolyExtStep::AndEqz(2603, 847), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5983PolyExtStep::AndEqz(2604, 853), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5984PolyExtStep::AndEqz(2605, 859), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5985PolyExtStep::AndEqz(2606, 896), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5986PolyExtStep::AndEqz(2607, 902), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5987PolyExtStep::AndEqz(2608, 908), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5988PolyExtStep::AndEqz(2609, 914), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5989PolyExtStep::AndEqz(2610, 920), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5990PolyExtStep::AndEqz(2611, 926), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5991PolyExtStep::AndEqz(2612, 932), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5992PolyExtStep::AndEqz(2613, 938), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5993PolyExtStep::AndEqz(2614, 975), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5994PolyExtStep::AndEqz(2615, 981), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5995PolyExtStep::AndEqz(2616, 987), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5996PolyExtStep::AndEqz(2617, 993), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5997PolyExtStep::AndEqz(2618, 999), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5998PolyExtStep::AndEqz(2619, 1005), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
5999PolyExtStep::AndEqz(2620, 1011), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6000PolyExtStep::AndEqz(2621, 1017), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6001PolyExtStep::AndCond(2477, 380, 2622), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6002PolyExtStep::Sub(374, 1054), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :73:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6003PolyExtStep::AndEqz(0, 3351), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :73:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6004PolyExtStep::AndEqz(2624, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :81:31) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6005PolyExtStep::AndEqz(2625, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6006PolyExtStep::Mul(1060, 7), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:19) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6007PolyExtStep::Add(3352, 1057), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:26) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6008PolyExtStep::Mul(1054, 16), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:24) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6009PolyExtStep::Mul(1055, 15), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:49) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6010PolyExtStep::Add(3354, 3355), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:31) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6011PolyExtStep::Sub(3356, 370), // loc(callsite( builtin Sub at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:53) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6012PolyExtStep::AndEqz(2626, 774), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6013PolyExtStep::Sub(770, 3357), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6014PolyExtStep::AndEqz(2627, 3358), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6015PolyExtStep::AndEqz(2628, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6016PolyExtStep::Mul(370, 1066), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6017PolyExtStep::Sub(3359, 1064), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6018PolyExtStep::AndEqz(2629, 3360), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6019PolyExtStep::Mul(1063, 370), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6020PolyExtStep::AndEqz(2630, 3361), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6021PolyExtStep::Mul(1063, 1066), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6022PolyExtStep::AndEqz(2631, 3362), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6023PolyExtStep::AndEqz(2632, 1063), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:19) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6024PolyExtStep::AndEqz(2633, 1751), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6025PolyExtStep::Mul(772, 5), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:4) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6026PolyExtStep::Add(3363, 3353), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:12) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6027PolyExtStep::Sub(3364, 368), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6028PolyExtStep::AndEqz(2634, 3365), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6029PolyExtStep::Add(503, 772), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:30) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6030PolyExtStep::AndEqz(2635, 3353), // loc(callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :75:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6031PolyExtStep::AndEqz(2636, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6032PolyExtStep::AndEqz(2637, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6033PolyExtStep::AndEqz(2638, 3181), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6034PolyExtStep::AndEqz(2639, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6035PolyExtStep::Sub(1137, 3366), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6036PolyExtStep::AndEqz(2640, 3367), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6037PolyExtStep::AndEqz(2641, 3183), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6038PolyExtStep::AndEqz(2642, 3184), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6039PolyExtStep::AndEqz(2643, 589), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6040PolyExtStep::AndEqz(2644, 3284), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6041PolyExtStep::AndEqz(2645, 811), // loc(callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :77:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6042PolyExtStep::Sub(1154, 45), // loc(callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :78:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6043PolyExtStep::AndEqz(2646, 3368), // loc(callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :78:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6044PolyExtStep::AndEqz(2647, 497), // loc(callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :79:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6045PolyExtStep::AndEqz(2648, 374), // loc(callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6046PolyExtStep::AndEqz(2649, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6047PolyExtStep::AndEqz(2650, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6048PolyExtStep::AndEqz(2651, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6049PolyExtStep::AndEqz(2652, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6050PolyExtStep::Sub(1372, 331), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6051PolyExtStep::AndEqz(2653, 3369), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6052PolyExtStep::AndEqz(2654, 3188), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6053PolyExtStep::AndEqz(2655, 3189), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6054PolyExtStep::AndEqz(2656, 1660), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6055PolyExtStep::AndEqz(2657, 3288), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6056PolyExtStep::AndEqz(2658, 3190), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6057PolyExtStep::AndEqz(2659, 3191), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6058PolyExtStep::AndEqz(2660, 3303), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6059PolyExtStep::AndEqz(2661, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6060PolyExtStep::Sub(1401, 332), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6061PolyExtStep::AndEqz(2662, 3370), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6062PolyExtStep::AndEqz(2663, 3306), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6063PolyExtStep::AndEqz(2664, 3307), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6064PolyExtStep::Sub(1427, 368), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6065PolyExtStep::AndEqz(2665, 3371), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6066PolyExtStep::Sub(1426, 370), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6067PolyExtStep::AndEqz(2666, 3372), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6068PolyExtStep::AndEqz(2667, 1428), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6069PolyExtStep::AndEqz(2668, 1431), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6070PolyExtStep::AndEqz(2669, 1900), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6071PolyExtStep::AndEqz(2670, 594), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6072PolyExtStep::AndEqz(2671, 622), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6073PolyExtStep::AndEqz(2672, 649), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6074PolyExtStep::AndEqz(2673, 673), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6075PolyExtStep::AndEqz(2674, 555), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6076PolyExtStep::AndEqz(2675, 571), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6077PolyExtStep::AndEqz(2676, 575), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6078PolyExtStep::AndEqz(2677, 743), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6079PolyExtStep::AndEqz(2678, 745), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6080PolyExtStep::AndEqz(2679, 747), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6081PolyExtStep::AndEqz(2680, 766), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6082PolyExtStep::AndEqz(2681, 768), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6083PolyExtStep::AndEqz(2682, 756), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6084PolyExtStep::AndEqz(2683, 762), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6085PolyExtStep::AndEqz(2684, 732), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6086PolyExtStep::AndEqz(2685, 764), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6087PolyExtStep::AndEqz(2686, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6088PolyExtStep::AndEqz(2687, 804), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6089PolyExtStep::AndEqz(2688, 817), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6090PolyExtStep::AndEqz(2689, 823), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6091PolyExtStep::AndEqz(2690, 829), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6092PolyExtStep::AndEqz(2691, 835), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6093PolyExtStep::AndEqz(2692, 841), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6094PolyExtStep::AndEqz(2693, 847), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6095PolyExtStep::AndEqz(2694, 853), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6096PolyExtStep::AndEqz(2695, 859), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6097PolyExtStep::AndEqz(2696, 896), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6098PolyExtStep::AndEqz(2697, 902), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6099PolyExtStep::AndEqz(2698, 908), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6100PolyExtStep::AndEqz(2699, 914), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6101PolyExtStep::AndEqz(2700, 920), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6102PolyExtStep::AndEqz(2701, 926), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6103PolyExtStep::AndEqz(2702, 932), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6104PolyExtStep::AndEqz(2703, 938), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6105PolyExtStep::AndEqz(2704, 975), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6106PolyExtStep::AndEqz(2705, 981), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6107PolyExtStep::AndEqz(2706, 987), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6108PolyExtStep::AndEqz(2707, 993), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6109PolyExtStep::AndEqz(2708, 999), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6110PolyExtStep::AndEqz(2709, 1005), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6111PolyExtStep::AndEqz(2710, 1011), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6112PolyExtStep::AndEqz(2711, 1017), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6113PolyExtStep::AndCond(2623, 383, 2712), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6114PolyExtStep::Sub(811, 333), // loc(callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :91:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6115PolyExtStep::AndEqz(2645, 3373), // loc(callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :91:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6116PolyExtStep::AndEqz(2714, 3368), // loc(callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :92:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6117PolyExtStep::AndEqz(2715, 497), // loc(callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :93:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6118PolyExtStep::AndEqz(2716, 3159), // loc(callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :94:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6119PolyExtStep::AndEqz(2717, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6120PolyExtStep::AndEqz(2718, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6121PolyExtStep::AndEqz(2719, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6122PolyExtStep::AndEqz(2720, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6123PolyExtStep::Sub(1372, 332), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6124PolyExtStep::AndEqz(2721, 3374), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6125PolyExtStep::AndEqz(2722, 3188), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6126PolyExtStep::AndEqz(2723, 3189), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6127PolyExtStep::AndEqz(2724, 1660), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6128PolyExtStep::AndEqz(2725, 3288), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6129PolyExtStep::Add(1391, 5), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6130PolyExtStep::AndEqz(2726, 758), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6131PolyExtStep::AndEqz(2727, 1071), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6132PolyExtStep::Mul(1069, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6133PolyExtStep::Add(3376, 757), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6134PolyExtStep::Sub(3375, 3377), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6135PolyExtStep::AndEqz(2728, 3378), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6136PolyExtStep::Add(1392, 1069), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6137PolyExtStep::AndEqz(2729, 782), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6138PolyExtStep::AndEqz(2730, 1074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6139PolyExtStep::Mul(1072, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6140PolyExtStep::Add(3380, 781), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6141PolyExtStep::Sub(3379, 3381), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6142PolyExtStep::AndEqz(2731, 3382), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6143PolyExtStep::AndEqz(2732, 1394), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6144PolyExtStep::AndEqz(2733, 1411), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6145PolyExtStep::AndEqz(2734, 1428), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6146PolyExtStep::AndEqz(2735, 1431), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6147PolyExtStep::AndEqz(2736, 1900), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6148PolyExtStep::AndEqz(2737, 594), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6149PolyExtStep::AndEqz(2738, 622), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6150PolyExtStep::AndEqz(2739, 649), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6151PolyExtStep::AndEqz(2740, 673), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6152PolyExtStep::AndEqz(2741, 555), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6153PolyExtStep::AndEqz(2742, 571), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6154PolyExtStep::AndEqz(2743, 575), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6155PolyExtStep::AndEqz(2744, 741), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6156PolyExtStep::AndEqz(2745, 743), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6157PolyExtStep::AndEqz(2746, 745), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6158PolyExtStep::AndEqz(2747, 747), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6159PolyExtStep::AndEqz(2748, 766), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6160PolyExtStep::AndEqz(2749, 768), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6161PolyExtStep::AndEqz(2750, 732), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6162PolyExtStep::AndEqz(2751, 764), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6163PolyExtStep::AndEqz(2752, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6164PolyExtStep::AndEqz(2753, 804), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6165PolyExtStep::AndEqz(2754, 817), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6166PolyExtStep::AndEqz(2755, 823), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6167PolyExtStep::AndEqz(2756, 829), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6168PolyExtStep::AndEqz(2757, 835), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6169PolyExtStep::AndEqz(2758, 841), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6170PolyExtStep::AndEqz(2759, 847), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6171PolyExtStep::AndEqz(2760, 853), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6172PolyExtStep::AndEqz(2761, 859), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6173PolyExtStep::AndEqz(2762, 896), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6174PolyExtStep::AndEqz(2763, 902), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6175PolyExtStep::AndEqz(2764, 908), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6176PolyExtStep::AndEqz(2765, 914), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6177PolyExtStep::AndEqz(2766, 920), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6178PolyExtStep::AndEqz(2767, 926), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6179PolyExtStep::AndEqz(2768, 932), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6180PolyExtStep::AndEqz(2769, 938), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6181PolyExtStep::AndEqz(2770, 975), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6182PolyExtStep::AndEqz(2771, 981), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6183PolyExtStep::AndEqz(2772, 987), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6184PolyExtStep::AndEqz(2773, 993), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6185PolyExtStep::AndEqz(2774, 999), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6186PolyExtStep::AndEqz(2775, 1005), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6187PolyExtStep::AndEqz(2776, 1011), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6188PolyExtStep::AndEqz(2777, 1017), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6189PolyExtStep::AndCond(2713, 386, 2778), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6190PolyExtStep::AndEqz(0, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :102:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6191PolyExtStep::Mul(3158, 1060), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :102:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6192PolyExtStep::Sub(3383, 1058), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :102:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6193PolyExtStep::AndEqz(2780, 3384), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :102:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6194PolyExtStep::AndEqz(2781, 3278), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :102:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6195PolyExtStep::Mul(1057, 1060), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :102:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6196PolyExtStep::AndEqz(2782, 3385), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :102:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6197PolyExtStep::AndEqz(0, 3160), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :104:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6198PolyExtStep::AndEqz(2784, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6199PolyExtStep::AndEqz(2785, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6200PolyExtStep::AndEqz(2786, 3181), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6201PolyExtStep::AndEqz(2787, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6202PolyExtStep::Sub(1137, 334), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6203PolyExtStep::AndEqz(2788, 3386), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6204PolyExtStep::AndEqz(2789, 3183), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6205PolyExtStep::AndEqz(2790, 3184), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6206PolyExtStep::AndEqz(2791, 589), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6207PolyExtStep::AndEqz(2792, 3284), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6208PolyExtStep::AndEqz(2793, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6209PolyExtStep::AndEqz(2794, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6210PolyExtStep::AndEqz(2795, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6211PolyExtStep::AndEqz(2796, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6212PolyExtStep::Sub(1372, 335), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6213PolyExtStep::AndEqz(2797, 3387), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6214PolyExtStep::AndEqz(2798, 3188), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6215PolyExtStep::AndEqz(2799, 3189), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6216PolyExtStep::AndEqz(2800, 1660), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6217PolyExtStep::AndEqz(2801, 3288), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6218PolyExtStep::AndEqz(2802, 3190), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6219PolyExtStep::AndEqz(2803, 3191), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6220PolyExtStep::AndEqz(2804, 3192), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6221PolyExtStep::AndEqz(2805, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6222PolyExtStep::Sub(1401, 336), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6223PolyExtStep::AndEqz(2806, 3388), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6224PolyExtStep::AndEqz(2807, 3194), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6225PolyExtStep::AndEqz(2808, 3195), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6226PolyExtStep::AndEqz(2809, 3306), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6227PolyExtStep::AndEqz(2810, 3307), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6228PolyExtStep::AndEqz(2811, 3196), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6229PolyExtStep::AndEqz(2812, 1854), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6230PolyExtStep::AndEqz(2813, 3197), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6231PolyExtStep::AndEqz(2814, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6232PolyExtStep::Sub(1829, 337), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6233PolyExtStep::AndEqz(2815, 3389), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6234PolyExtStep::AndEqz(2816, 3199), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6235PolyExtStep::AndEqz(2817, 3200), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6236PolyExtStep::AndEqz(2818, 2955), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6237PolyExtStep::AndEqz(2819, 3315), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6238PolyExtStep::AndEqz(2820, 2790), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6239PolyExtStep::AndEqz(2821, 2795), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6240PolyExtStep::AndEqz(2822, 3201), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6241PolyExtStep::AndEqz(2823, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6242PolyExtStep::Sub(538, 338), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6243PolyExtStep::AndEqz(2824, 3390), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6244PolyExtStep::AndEqz(2825, 2794), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6245PolyExtStep::AndEqz(2826, 3203), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6246PolyExtStep::AndEqz(2827, 754), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6247PolyExtStep::AndEqz(2828, 3323), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6248PolyExtStep::AndEqz(2829, 3204), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6249PolyExtStep::AndEqz(2830, 2297), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6250PolyExtStep::AndEqz(2831, 3205), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6251PolyExtStep::AndEqz(2832, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6252PolyExtStep::Sub(629, 339), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6253PolyExtStep::AndEqz(2833, 3391), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6254PolyExtStep::AndEqz(2834, 3207), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6255PolyExtStep::AndEqz(2835, 2918), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6256PolyExtStep::AndEqz(2836, 1745), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6257PolyExtStep::AndEqz(2837, 3331), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6258PolyExtStep::AndEqz(2838, 3208), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6259PolyExtStep::AndEqz(2839, 1639), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6260PolyExtStep::AndEqz(2840, 3209), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6261PolyExtStep::AndEqz(2841, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6262PolyExtStep::Sub(676, 340), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6263PolyExtStep::AndEqz(2842, 3392), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6264PolyExtStep::AndEqz(2843, 3211), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6265PolyExtStep::AndEqz(2844, 3042), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6266PolyExtStep::AndEqz(2845, 3339), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6267PolyExtStep::AndEqz(2846, 3340), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6268PolyExtStep::AndEqz(2847, 3212), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6269PolyExtStep::AndEqz(2848, 580), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6270PolyExtStep::AndEqz(2849, 581), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6271PolyExtStep::AndEqz(2850, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6272PolyExtStep::Sub(570, 341), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6273PolyExtStep::AndEqz(2851, 3393), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6274PolyExtStep::AndEqz(2852, 583), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6275PolyExtStep::AndEqz(2853, 584), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6276PolyExtStep::AndEqz(2854, 3347), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6277PolyExtStep::AndEqz(2855, 3348), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6278PolyExtStep::GetGlobal(0, 17), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6279PolyExtStep::Sub(1154, 3394), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6280PolyExtStep::AndEqz(2856, 3395), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6281PolyExtStep::GetGlobal(0, 18), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6282PolyExtStep::Sub(811, 3396), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6283PolyExtStep::AndEqz(2857, 3397), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6284PolyExtStep::GetGlobal(0, 19), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6285PolyExtStep::Sub(1391, 3398), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6286PolyExtStep::AndEqz(2858, 3399), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6287PolyExtStep::GetGlobal(0, 20), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6288PolyExtStep::Sub(1392, 3400), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6289PolyExtStep::AndEqz(2859, 3401), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6290PolyExtStep::GetGlobal(0, 21), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6291PolyExtStep::Sub(1427, 3402), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6292PolyExtStep::AndEqz(2860, 3403), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6293PolyExtStep::GetGlobal(0, 22), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6294PolyExtStep::Sub(1426, 3404), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6295PolyExtStep::AndEqz(2861, 3405), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6296PolyExtStep::GetGlobal(0, 23), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6297PolyExtStep::Sub(1439, 3406), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6298PolyExtStep::AndEqz(2862, 3407), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6299PolyExtStep::GetGlobal(0, 24), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6300PolyExtStep::Sub(1440, 3408), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6301PolyExtStep::AndEqz(2863, 3409), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6302PolyExtStep::GetGlobal(0, 25), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6303PolyExtStep::Sub(608, 3410), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6304PolyExtStep::AndEqz(2864, 3411), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6305PolyExtStep::GetGlobal(0, 26), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6306PolyExtStep::Sub(615, 3412), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6307PolyExtStep::AndEqz(2865, 3413), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6308PolyExtStep::GetGlobal(0, 27), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6309PolyExtStep::Sub(659, 3414), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6310PolyExtStep::AndEqz(2866, 3415), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6311PolyExtStep::GetGlobal(0, 28), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6312PolyExtStep::Sub(666, 3416), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6313PolyExtStep::AndEqz(2867, 3417), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6314PolyExtStep::GetGlobal(0, 29), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6315PolyExtStep::Sub(563, 3418), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6316PolyExtStep::AndEqz(2868, 3419), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6317PolyExtStep::GetGlobal(0, 30), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6318PolyExtStep::Sub(564, 3420), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6319PolyExtStep::AndEqz(2869, 3421), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6320PolyExtStep::GetGlobal(0, 31), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6321PolyExtStep::Sub(577, 3422), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6322PolyExtStep::AndEqz(2870, 3423), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6323PolyExtStep::GetGlobal(0, 32), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6324PolyExtStep::Sub(578, 3424), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6325PolyExtStep::AndEqz(2871, 3425), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6326PolyExtStep::GetGlobal(0, 16), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :106:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6327PolyExtStep::Sub(1, 3426), // loc(callsite( builtin Sub at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :111:10) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6328PolyExtStep::GetGlobal(0, 87), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :112:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6329PolyExtStep::Sub(0, 3428), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :112:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6330PolyExtStep::AndEqz(0, 3429), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :112:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6331PolyExtStep::GetGlobal(0, 86), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :113:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6332PolyExtStep::Sub(0, 3430), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :113:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6333PolyExtStep::AndEqz(2873, 3431), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :113:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6334PolyExtStep::GetGlobal(0, 89), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :114:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6335PolyExtStep::Sub(0, 3432), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :114:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6336PolyExtStep::AndEqz(2874, 3433), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :114:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6337PolyExtStep::GetGlobal(0, 88), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6338PolyExtStep::Sub(0, 3434), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6339PolyExtStep::AndEqz(2875, 3435), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6340PolyExtStep::AndCond(2872, 3427, 2876), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :111:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6341PolyExtStep::AndCond(2783, 1057, 2877), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6342PolyExtStep::Sub(371, 1054), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :123:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6343PolyExtStep::AndEqz(0, 3436), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :123:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6344PolyExtStep::Sub(1054, 13), // loc(callsite( builtin Sub at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :124:7) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6345PolyExtStep::Sub(1054, 5), // loc(callsite( builtin Sub at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :124:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6346PolyExtStep::Mul(3437, 3438), // loc(callsite( builtin Mul at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :124:28) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6347PolyExtStep::AndEqz(2879, 3439), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :124:57) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6348PolyExtStep::Mul(3437, 355), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :127:54) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6349PolyExtStep::Sub(3440, 3426), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :127:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6350PolyExtStep::AndEqz(2880, 3441), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :127:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6351PolyExtStep::AndEqz(2881, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6352PolyExtStep::AndEqz(2882, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6353PolyExtStep::AndEqz(2883, 3291), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6354PolyExtStep::AndEqz(2884, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6355PolyExtStep::AndEqz(2885, 3282), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6356PolyExtStep::AndEqz(2886, 589), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6357PolyExtStep::AndEqz(2887, 3284), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6358PolyExtStep::Sub(1154, 368), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6359PolyExtStep::AndEqz(2888, 3442), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6360PolyExtStep::Sub(811, 370), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6361PolyExtStep::AndEqz(2889, 3443), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6362PolyExtStep::AndEqz(2890, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6363PolyExtStep::AndEqz(2891, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6364PolyExtStep::AndEqz(2892, 3297), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6365PolyExtStep::AndEqz(2893, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6366PolyExtStep::AndEqz(2894, 3285), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6367PolyExtStep::AndEqz(2895, 1660), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6368PolyExtStep::AndEqz(2896, 3288), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6369PolyExtStep::Sub(1391, 374), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6370PolyExtStep::AndEqz(2897, 3444), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6371PolyExtStep::AndEqz(2898, 1392), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6372PolyExtStep::AndEqz(2899, 1394), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6373PolyExtStep::AndEqz(2900, 1411), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6374PolyExtStep::AndEqz(2901, 1428), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6375PolyExtStep::AndEqz(2902, 1431), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6376PolyExtStep::AndEqz(2903, 1900), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6377PolyExtStep::AndEqz(2904, 594), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6378PolyExtStep::AndEqz(2905, 622), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6379PolyExtStep::AndEqz(2906, 649), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6380PolyExtStep::AndEqz(2907, 673), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6381PolyExtStep::AndEqz(2908, 555), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6382PolyExtStep::AndEqz(2909, 571), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6383PolyExtStep::AndEqz(2910, 575), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6384PolyExtStep::AndEqz(2911, 741), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6385PolyExtStep::AndEqz(2912, 743), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6386PolyExtStep::AndEqz(2913, 745), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6387PolyExtStep::AndEqz(2914, 747), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6388PolyExtStep::AndEqz(2915, 766), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6389PolyExtStep::AndEqz(2916, 768), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6390PolyExtStep::AndCond(2878, 1058, 2917), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6391PolyExtStep::AndEqz(2918, 761), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6392PolyExtStep::AndEqz(2919, 771), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6393PolyExtStep::AndEqz(2920, 756), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6394PolyExtStep::AndEqz(2921, 762), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6395PolyExtStep::AndEqz(2922, 732), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6396PolyExtStep::AndEqz(2923, 764), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6397PolyExtStep::AndEqz(2924, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6398PolyExtStep::AndEqz(2925, 804), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6399PolyExtStep::AndEqz(2926, 817), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6400PolyExtStep::AndEqz(2927, 823), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6401PolyExtStep::AndEqz(2928, 829), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6402PolyExtStep::AndEqz(2929, 835), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6403PolyExtStep::AndEqz(2930, 841), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6404PolyExtStep::AndEqz(2931, 847), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6405PolyExtStep::AndEqz(2932, 853), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6406PolyExtStep::AndEqz(2933, 859), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6407PolyExtStep::AndEqz(2934, 896), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6408PolyExtStep::AndEqz(2935, 902), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6409PolyExtStep::AndEqz(2936, 908), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6410PolyExtStep::AndEqz(2937, 914), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6411PolyExtStep::AndEqz(2938, 920), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6412PolyExtStep::AndEqz(2939, 926), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6413PolyExtStep::AndEqz(2940, 932), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6414PolyExtStep::AndEqz(2941, 938), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6415PolyExtStep::AndEqz(2942, 975), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6416PolyExtStep::AndEqz(2943, 981), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6417PolyExtStep::AndEqz(2944, 987), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6418PolyExtStep::AndEqz(2945, 993), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6419PolyExtStep::AndEqz(2946, 999), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6420PolyExtStep::AndEqz(2947, 1005), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6421PolyExtStep::AndEqz(2948, 1011), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6422PolyExtStep::AndEqz(2949, 1017), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6423PolyExtStep::AndCond(2779, 389, 2950), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6424PolyExtStep::AndEqz(0, 3161), // loc(callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :137:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6425PolyExtStep::AndEqz(2952, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6426PolyExtStep::AndEqz(2953, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6427PolyExtStep::AndEqz(2954, 3181), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6428PolyExtStep::AndEqz(2955, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6429PolyExtStep::Sub(1137, 322), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6430PolyExtStep::AndEqz(2956, 3445), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6431PolyExtStep::AndEqz(2957, 589), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6432PolyExtStep::AndEqz(2958, 3284), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6433PolyExtStep::AndEqz(2959, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6434PolyExtStep::AndEqz(2960, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6435PolyExtStep::AndEqz(2961, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6436PolyExtStep::AndEqz(2962, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6437PolyExtStep::Sub(1372, 342), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6438PolyExtStep::AndEqz(2963, 3446), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6439PolyExtStep::AndEqz(2964, 1660), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6440PolyExtStep::AndEqz(2965, 3288), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6441PolyExtStep::AndEqz(2966, 3190), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6442PolyExtStep::AndEqz(2967, 3191), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6443PolyExtStep::AndEqz(2968, 3192), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6444PolyExtStep::AndEqz(2969, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6445PolyExtStep::Sub(1401, 343), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6446PolyExtStep::AndEqz(2970, 3447), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6447PolyExtStep::AndEqz(2971, 3306), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6448PolyExtStep::AndEqz(2972, 3307), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6449PolyExtStep::AndEqz(2973, 3196), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6450PolyExtStep::AndEqz(2974, 1854), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6451PolyExtStep::AndEqz(2975, 3197), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6452PolyExtStep::AndEqz(2976, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6453PolyExtStep::Sub(1829, 344), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6454PolyExtStep::AndEqz(2977, 3448), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6455PolyExtStep::AndEqz(2978, 2955), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6456PolyExtStep::AndEqz(2979, 3315), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6457PolyExtStep::AndEqz(2980, 2790), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6458PolyExtStep::AndEqz(2981, 2795), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6459PolyExtStep::AndEqz(2982, 3201), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6460PolyExtStep::AndEqz(2983, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6461PolyExtStep::Sub(538, 345), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6462PolyExtStep::AndEqz(2984, 3449), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6463PolyExtStep::AndEqz(2985, 754), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6464PolyExtStep::AndEqz(2986, 3323), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6465PolyExtStep::AndEqz(2987, 3204), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6466PolyExtStep::AndEqz(2988, 2297), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6467PolyExtStep::AndEqz(2989, 3205), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6468PolyExtStep::AndEqz(2990, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6469PolyExtStep::Sub(629, 346), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6470PolyExtStep::AndEqz(2991, 3450), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6471PolyExtStep::AndEqz(2992, 1745), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6472PolyExtStep::AndEqz(2993, 3331), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6473PolyExtStep::AndEqz(2994, 3208), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6474PolyExtStep::AndEqz(2995, 1639), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6475PolyExtStep::AndEqz(2996, 3209), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6476PolyExtStep::AndEqz(2997, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6477PolyExtStep::Sub(676, 347), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6478PolyExtStep::AndEqz(2998, 3451), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6479PolyExtStep::AndEqz(2999, 3339), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6480PolyExtStep::AndEqz(3000, 3340), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6481PolyExtStep::AndEqz(3001, 3212), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6482PolyExtStep::AndEqz(3002, 580), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6483PolyExtStep::AndEqz(3003, 581), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6484PolyExtStep::AndEqz(3004, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6485PolyExtStep::Sub(570, 348), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6486PolyExtStep::AndEqz(3005, 3452), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6487PolyExtStep::AndEqz(3006, 3347), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6488PolyExtStep::AndEqz(3007, 3348), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6489PolyExtStep::GetGlobal(0, 70), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6490PolyExtStep::Sub(1143, 3453), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6491PolyExtStep::AndEqz(3008, 3454), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6492PolyExtStep::GetGlobal(0, 71), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6493PolyExtStep::Sub(809, 3455), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6494PolyExtStep::AndEqz(3009, 3456), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6495PolyExtStep::GetGlobal(0, 72), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6496PolyExtStep::Sub(1375, 3457), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6497PolyExtStep::AndEqz(3010, 3458), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6498PolyExtStep::GetGlobal(0, 73), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6499PolyExtStep::Sub(1382, 3459), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6500PolyExtStep::AndEqz(3011, 3460), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6501PolyExtStep::GetGlobal(0, 74), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6502PolyExtStep::Sub(1404, 3461), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6503PolyExtStep::AndEqz(3012, 3462), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6504PolyExtStep::GetGlobal(0, 75), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6505PolyExtStep::Sub(1410, 3463), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6506PolyExtStep::AndEqz(3013, 3464), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6507PolyExtStep::GetGlobal(0, 76), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6508PolyExtStep::Sub(1429, 3465), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6509PolyExtStep::AndEqz(3014, 3466), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6510PolyExtStep::GetGlobal(0, 77), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6511PolyExtStep::Sub(1430, 3467), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6512PolyExtStep::AndEqz(3015, 3468), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6513PolyExtStep::GetGlobal(0, 78), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6514PolyExtStep::Sub(539, 3469), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6515PolyExtStep::AndEqz(3016, 3470), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6516PolyExtStep::GetGlobal(0, 79), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6517PolyExtStep::Sub(591, 3471), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6518PolyExtStep::AndEqz(3017, 3472), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6519PolyExtStep::GetGlobal(0, 80), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6520PolyExtStep::Sub(639, 3473), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6521PolyExtStep::AndEqz(3018, 3474), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6522PolyExtStep::GetGlobal(0, 81), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6523PolyExtStep::Sub(646, 3475), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6524PolyExtStep::AndEqz(3019, 3476), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6525PolyExtStep::GetGlobal(0, 82), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6526PolyExtStep::Sub(551, 3477), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6527PolyExtStep::AndEqz(3020, 3478), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6528PolyExtStep::GetGlobal(0, 83), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6529PolyExtStep::Sub(552, 3479), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6530PolyExtStep::AndEqz(3021, 3480), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6531PolyExtStep::GetGlobal(0, 84), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6532PolyExtStep::Sub(573, 3481), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6533PolyExtStep::AndEqz(3022, 3482), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6534PolyExtStep::GetGlobal(0, 85), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6535PolyExtStep::Sub(574, 3483), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6536PolyExtStep::AndEqz(3023, 3484), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6537PolyExtStep::AndEqz(3024, 761), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6538PolyExtStep::AndEqz(3025, 771), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6539PolyExtStep::AndEqz(3026, 756), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6540PolyExtStep::AndEqz(3027, 762), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6541PolyExtStep::AndEqz(3028, 732), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6542PolyExtStep::AndEqz(3029, 764), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6543PolyExtStep::AndEqz(3030, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6544PolyExtStep::AndEqz(3031, 804), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6545PolyExtStep::AndEqz(3032, 817), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6546PolyExtStep::AndEqz(3033, 823), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6547PolyExtStep::AndEqz(3034, 829), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6548PolyExtStep::AndEqz(3035, 835), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6549PolyExtStep::AndEqz(3036, 841), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6550PolyExtStep::AndEqz(3037, 847), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6551PolyExtStep::AndEqz(3038, 853), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6552PolyExtStep::AndEqz(3039, 859), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6553PolyExtStep::AndEqz(3040, 896), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6554PolyExtStep::AndEqz(3041, 902), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6555PolyExtStep::AndEqz(3042, 908), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6556PolyExtStep::AndEqz(3043, 914), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6557PolyExtStep::AndEqz(3044, 920), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6558PolyExtStep::AndEqz(3045, 926), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6559PolyExtStep::AndEqz(3046, 932), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6560PolyExtStep::AndEqz(3047, 938), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6561PolyExtStep::AndEqz(3048, 975), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6562PolyExtStep::AndEqz(3049, 981), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6563PolyExtStep::AndEqz(3050, 987), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6564PolyExtStep::AndEqz(3051, 993), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6565PolyExtStep::AndEqz(3052, 999), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6566PolyExtStep::AndEqz(3053, 1005), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6567PolyExtStep::AndEqz(3054, 1011), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6568PolyExtStep::AndEqz(3055, 1017), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6569PolyExtStep::AndCond(2951, 392, 3056), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6570PolyExtStep::AndEqz(0, 3162), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6571PolyExtStep::Sub(368, 1060), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :148:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6572PolyExtStep::AndEqz(3058, 3485), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :148:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6573PolyExtStep::Sub(374, 1063), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :149:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6574PolyExtStep::AndEqz(3059, 3486), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :149:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6575PolyExtStep::Add(1060, 1), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6576PolyExtStep::Add(1060, 7), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6577PolyExtStep::Add(1060, 6), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6578PolyExtStep::Add(1060, 5), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6579PolyExtStep::Add(1060, 4), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6580PolyExtStep::Add(1060, 3), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6581PolyExtStep::Add(1060, 2), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6582PolyExtStep::Add(1060, 12), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6583PolyExtStep::Add(1060, 11), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6584PolyExtStep::Add(1060, 10), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6585PolyExtStep::Add(1060, 9), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6586PolyExtStep::Add(1060, 8), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6587PolyExtStep::Add(1060, 34), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6588PolyExtStep::Add(1060, 35), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6589PolyExtStep::Add(1060, 36), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6590PolyExtStep::Add(1060, 23), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :158:14) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6591PolyExtStep::Sub(3502, 33), // loc(callsite( builtin Sub at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :159:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6592PolyExtStep::Sub(770, 1060), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6593PolyExtStep::AndEqz(0, 3504), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6594PolyExtStep::Sub(772, 3487), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6595PolyExtStep::AndEqz(3061, 3505), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6596PolyExtStep::Sub(757, 3488), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6597PolyExtStep::AndEqz(3062, 3506), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6598PolyExtStep::Sub(781, 3489), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6599PolyExtStep::AndEqz(3063, 3507), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6600PolyExtStep::Sub(737, 3490), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6601PolyExtStep::AndEqz(3064, 3508), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6602PolyExtStep::Sub(798, 3491), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6603PolyExtStep::AndEqz(3065, 3509), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6604PolyExtStep::Sub(802, 3492), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6605PolyExtStep::AndEqz(3066, 3510), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6606PolyExtStep::Sub(814, 3493), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6607PolyExtStep::AndEqz(3067, 3511), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6608PolyExtStep::Sub(820, 3494), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6609PolyExtStep::AndEqz(3068, 3512), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6610PolyExtStep::Sub(826, 3495), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6611PolyExtStep::AndEqz(3069, 3513), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6612PolyExtStep::Sub(832, 3496), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6613PolyExtStep::AndEqz(3070, 3514), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6614PolyExtStep::Sub(838, 3497), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6615PolyExtStep::AndEqz(3071, 3515), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6616PolyExtStep::Sub(844, 3498), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6617PolyExtStep::AndEqz(3072, 3516), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6618PolyExtStep::Sub(850, 3499), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6619PolyExtStep::AndEqz(3073, 3517), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6620PolyExtStep::Sub(856, 3500), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6621PolyExtStep::AndEqz(3074, 3518), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6622PolyExtStep::Sub(893, 3501), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6623PolyExtStep::AndEqz(3075, 3519), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6624PolyExtStep::AndEqz(3076, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :159:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6625PolyExtStep::Mul(3503, 1057), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :159:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6626PolyExtStep::Sub(3520, 1055), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :159:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6627PolyExtStep::AndEqz(3077, 3521), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :159:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6628PolyExtStep::Mul(1054, 3503), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :159:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6629PolyExtStep::AndEqz(3078, 3522), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :159:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6630PolyExtStep::AndEqz(3079, 3281), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :159:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6631PolyExtStep::AndEqz(3080, 896), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6632PolyExtStep::AndEqz(3081, 902), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6633PolyExtStep::AndEqz(3082, 908), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6634PolyExtStep::AndEqz(3083, 914), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6635PolyExtStep::AndEqz(3084, 920), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6636PolyExtStep::AndEqz(3085, 926), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6637PolyExtStep::AndEqz(3086, 932), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6638PolyExtStep::AndEqz(3087, 938), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6639PolyExtStep::AndEqz(3088, 975), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6640PolyExtStep::AndEqz(3089, 981), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6641PolyExtStep::AndEqz(3090, 987), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6642PolyExtStep::AndEqz(3091, 993), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6643PolyExtStep::AndEqz(3092, 999), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6644PolyExtStep::AndEqz(3093, 1005), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6645PolyExtStep::AndEqz(3094, 1011), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6646PolyExtStep::AndEqz(3095, 1017), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6647PolyExtStep::AndCond(3060, 1063, 3096), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6648PolyExtStep::Sub(3502, 20), // loc(callsite( builtin Sub at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6649PolyExtStep::Sub(899, 1060), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6650PolyExtStep::AndEqz(0, 3524), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6651PolyExtStep::Sub(905, 3487), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6652PolyExtStep::AndEqz(3098, 3525), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6653PolyExtStep::Sub(911, 3488), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6654PolyExtStep::AndEqz(3099, 3526), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6655PolyExtStep::Sub(917, 3489), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6656PolyExtStep::AndEqz(3100, 3527), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6657PolyExtStep::Sub(923, 3490), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6658PolyExtStep::AndEqz(3101, 3528), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6659PolyExtStep::Sub(929, 3491), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6660PolyExtStep::AndEqz(3102, 3529), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6661PolyExtStep::Sub(935, 3492), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6662PolyExtStep::AndEqz(3103, 3530), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6663PolyExtStep::Sub(972, 3493), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6664PolyExtStep::AndEqz(3104, 3531), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6665PolyExtStep::Sub(978, 3494), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6666PolyExtStep::AndEqz(3105, 3532), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6667PolyExtStep::Sub(984, 3495), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6668PolyExtStep::AndEqz(3106, 3533), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6669PolyExtStep::Sub(990, 3496), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6670PolyExtStep::AndEqz(3107, 3534), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6671PolyExtStep::Sub(996, 3497), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6672PolyExtStep::AndEqz(3108, 3535), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6673PolyExtStep::Sub(1002, 3498), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6674PolyExtStep::AndEqz(3109, 3536), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6675PolyExtStep::Sub(1008, 3499), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6676PolyExtStep::AndEqz(3110, 3537), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6677PolyExtStep::Sub(1014, 3500), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6678PolyExtStep::AndEqz(3111, 3538), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6679PolyExtStep::Sub(1051, 3501), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6680PolyExtStep::AndEqz(3112, 3539), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6681PolyExtStep::AndEqz(3113, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6682PolyExtStep::Mul(3523, 1057), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6683PolyExtStep::Sub(3540, 1055), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6684PolyExtStep::AndEqz(3114, 3541), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6685PolyExtStep::Mul(1054, 3523), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6686PolyExtStep::AndEqz(3115, 3542), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6687PolyExtStep::AndEqz(3116, 3281), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6688PolyExtStep::AndEqz(3117, 761), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6689PolyExtStep::AndEqz(3118, 771), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6690PolyExtStep::AndEqz(3119, 756), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6691PolyExtStep::AndEqz(3120, 762), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6692PolyExtStep::AndEqz(3121, 732), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6693PolyExtStep::AndEqz(3122, 764), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6694PolyExtStep::AndEqz(3123, 800), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6695PolyExtStep::AndEqz(3124, 804), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6696PolyExtStep::AndEqz(3125, 817), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6697PolyExtStep::AndEqz(3126, 823), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6698PolyExtStep::AndEqz(3127, 829), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6699PolyExtStep::AndEqz(3128, 835), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6700PolyExtStep::AndEqz(3129, 841), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6701PolyExtStep::AndEqz(3130, 847), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6702PolyExtStep::AndEqz(3131, 853), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6703PolyExtStep::AndEqz(3132, 859), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6704PolyExtStep::AndCond(3097, 1064, 3133), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6705PolyExtStep::AndEqz(3134, 807), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6706PolyExtStep::AndEqz(3135, 1148), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6707PolyExtStep::AndEqz(3136, 1160), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6708PolyExtStep::AndEqz(3137, 1383), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6709PolyExtStep::AndEqz(3138, 1394), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6710PolyExtStep::AndEqz(3139, 1411), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6711PolyExtStep::AndEqz(3140, 1428), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6712PolyExtStep::AndEqz(3141, 1431), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6713PolyExtStep::AndEqz(3142, 1900), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6714PolyExtStep::AndEqz(3143, 594), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6715PolyExtStep::AndEqz(3144, 622), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6716PolyExtStep::AndEqz(3145, 649), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6717PolyExtStep::AndEqz(3146, 673), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6718PolyExtStep::AndEqz(3147, 555), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6719PolyExtStep::AndEqz(3148, 571), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6720PolyExtStep::AndEqz(3149, 575), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6721PolyExtStep::AndEqz(3150, 587), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6722PolyExtStep::AndEqz(3151, 739), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6723PolyExtStep::AndEqz(3152, 741), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6724PolyExtStep::AndEqz(3153, 743), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6725PolyExtStep::AndEqz(3154, 745), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6726PolyExtStep::AndEqz(3155, 747), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6727PolyExtStep::AndEqz(3156, 766), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6728PolyExtStep::AndEqz(3157, 768), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6729PolyExtStep::AndCond(3057, 395, 3158), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6730PolyExtStep::AndEqz(0, 3163), // loc(callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :183:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6731PolyExtStep::Mul(499, 3427), // loc(callsite( builtin Mul at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :186:23) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6732PolyExtStep::Sub(1, 3543), // loc(callsite( builtin Sub at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :186:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6733PolyExtStep::GetGlobal(0, 53), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :185:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6734PolyExtStep::Sub(362, 3545), // loc(callsite( builtin Sub at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :188:14) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6735PolyExtStep::AndEqz(0, 589), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :188:13) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6736PolyExtStep::Sub(588, 3546), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :188:13) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6737PolyExtStep::AndEqz(3161, 3547), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :188:13) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6738PolyExtStep::AndCond(3160, 3543, 3162), // loc(callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :186:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6739PolyExtStep::AndEqz(0, 587), // loc(callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :186:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6740PolyExtStep::AndCond(3163, 3544, 3164), // loc(callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :186:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6741PolyExtStep::AndEqz(3165, 807), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6742PolyExtStep::AndEqz(3166, 1148), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6743PolyExtStep::AndEqz(3167, 1160), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6744PolyExtStep::AndEqz(3168, 1383), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6745PolyExtStep::AndEqz(3169, 1394), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6746PolyExtStep::AndEqz(3170, 1411), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6747PolyExtStep::AndEqz(3171, 1428), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6748PolyExtStep::AndEqz(3172, 1431), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6749PolyExtStep::AndEqz(3173, 1900), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6750PolyExtStep::AndEqz(3174, 594), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6751PolyExtStep::AndEqz(3175, 622), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6752PolyExtStep::AndEqz(3176, 649), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6753PolyExtStep::AndEqz(3177, 673), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6754PolyExtStep::AndEqz(3178, 555), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6755PolyExtStep::AndEqz(3179, 571), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6756PolyExtStep::AndEqz(3180, 575), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6757PolyExtStep::AndEqz(3181, 739), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6758PolyExtStep::AndEqz(3182, 741), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6759PolyExtStep::AndEqz(3183, 743), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6760PolyExtStep::AndEqz(3184, 745), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6761PolyExtStep::AndEqz(3185, 747), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6762PolyExtStep::AndEqz(3186, 766), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6763PolyExtStep::AndEqz(3187, 768), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6764PolyExtStep::AndEqz(3188, 761), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6765PolyExtStep::AndEqz(3189, 771), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6766PolyExtStep::AndEqz(3190, 756), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6767PolyExtStep::AndEqz(3191, 762), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6768PolyExtStep::AndEqz(3192, 732), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6769PolyExtStep::AndEqz(3193, 764), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6770PolyExtStep::AndEqz(3194, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6771PolyExtStep::AndEqz(3195, 804), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6772PolyExtStep::AndEqz(3196, 817), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6773PolyExtStep::AndEqz(3197, 823), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6774PolyExtStep::AndEqz(3198, 829), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6775PolyExtStep::AndEqz(3199, 835), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6776PolyExtStep::AndEqz(3200, 841), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6777PolyExtStep::AndEqz(3201, 847), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6778PolyExtStep::AndEqz(3202, 853), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6779PolyExtStep::AndEqz(3203, 859), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6780PolyExtStep::AndEqz(3204, 896), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6781PolyExtStep::AndEqz(3205, 902), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6782PolyExtStep::AndEqz(3206, 908), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6783PolyExtStep::AndEqz(3207, 914), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6784PolyExtStep::AndEqz(3208, 920), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6785PolyExtStep::AndEqz(3209, 926), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6786PolyExtStep::AndEqz(3210, 932), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6787PolyExtStep::AndEqz(3211, 938), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6788PolyExtStep::AndEqz(3212, 975), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6789PolyExtStep::AndEqz(3213, 981), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6790PolyExtStep::AndEqz(3214, 987), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6791PolyExtStep::AndEqz(3215, 993), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6792PolyExtStep::AndEqz(3216, 999), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6793PolyExtStep::AndEqz(3217, 1005), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6794PolyExtStep::AndEqz(3218, 1011), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6795PolyExtStep::AndEqz(3219, 1017), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6796PolyExtStep::AndCond(3159, 398, 3220), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6797PolyExtStep::AndCond(2342, 443, 3221), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
6798PolyExtStep::Sub(371, 11), // loc(callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :46:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6799PolyExtStep::Sub(371, 10), // loc(callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :70:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6800PolyExtStep::Sub(371, 9), // loc(callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :103:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6801PolyExtStep::Sub(371, 8), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :121:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6802PolyExtStep::Sub(371, 34), // loc(callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :171:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6803PolyExtStep::Mul(380, 5), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6804PolyExtStep::Mul(386, 13), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6805PolyExtStep::Sub(570, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :201:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6806PolyExtStep::AndEqz(0, 3555), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :201:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6807PolyExtStep::Sub(573, 542), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :201:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6808PolyExtStep::AndEqz(3223, 3556), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :201:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6809PolyExtStep::AndEqz(3224, 2115), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :81:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6810PolyExtStep::AndEqz(3225, 2121), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6811PolyExtStep::Mul(575, 7), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6812PolyExtStep::Add(3557, 574), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6813PolyExtStep::AndEqz(3226, 585), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6814PolyExtStep::Sub(577, 502), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6815PolyExtStep::AndEqz(3227, 3559), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6816PolyExtStep::AndEqz(3228, 2135), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6817PolyExtStep::Mul(370, 587), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6818PolyExtStep::Sub(3560, 2134), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6819PolyExtStep::AndEqz(3229, 3561), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6820PolyExtStep::Mul(578, 370), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6821PolyExtStep::AndEqz(3230, 3562), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6822PolyExtStep::Mul(578, 587), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6823PolyExtStep::AndEqz(3231, 3563), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6824PolyExtStep::AndEqz(3232, 578), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6825PolyExtStep::Sub(588, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6826PolyExtStep::AndEqz(3233, 3564), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6827PolyExtStep::Mul(739, 5), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6828PolyExtStep::Add(3565, 3558), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:12) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6829PolyExtStep::Sub(3566, 368), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6830PolyExtStep::AndEqz(3234, 3567), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6831PolyExtStep::Add(503, 739), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6832PolyExtStep::AndEqz(3235, 3558), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :203:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6833PolyExtStep::Sub(1137, 3568), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6834PolyExtStep::AndEqz(2486, 3569), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6835PolyExtStep::AndEqz(3237, 3183), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6836PolyExtStep::AndEqz(3238, 3184), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6837PolyExtStep::AndEqz(3239, 1901), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6838PolyExtStep::Sub(538, 3283), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6839PolyExtStep::AndEqz(3240, 3570), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6840PolyExtStep::AndEqz(3241, 497), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :27:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6841PolyExtStep::AndEqz(3242, 811), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :28:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6842PolyExtStep::AndEqz(3243, 3368), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :29:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6843PolyExtStep::AndEqz(3244, 3159), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :30:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6844PolyExtStep::AndEqz(3245, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6845PolyExtStep::AndEqz(3246, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6846PolyExtStep::AndEqz(3247, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6847PolyExtStep::AndEqz(3248, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6848PolyExtStep::Sub(1372, 52), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6849PolyExtStep::AndEqz(3249, 3571), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6850PolyExtStep::AndEqz(3250, 3188), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6851PolyExtStep::AndEqz(3251, 3189), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6852PolyExtStep::AndEqz(3252, 2279), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6853PolyExtStep::Sub(539, 3287), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6854PolyExtStep::AndEqz(3253, 3572), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6855PolyExtStep::AndEqz(3254, 1392), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :32:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6856PolyExtStep::AndEqz(3255, 2151), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6857PolyExtStep::AndEqz(3256, 2157), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6858PolyExtStep::AndEqz(3257, 3068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6859PolyExtStep::AndEqz(3258, 2068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6860PolyExtStep::Sub(1, 744), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6861PolyExtStep::Mul(744, 3573), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6862PolyExtStep::AndEqz(3259, 3574), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6863PolyExtStep::AndEqz(3260, 3074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6864PolyExtStep::Add(740, 741), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6865PolyExtStep::Add(3575, 742), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6866PolyExtStep::Add(3576, 743), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6867PolyExtStep::Add(3577, 744), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6868PolyExtStep::Add(3578, 745), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6869PolyExtStep::Sub(3579, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6870PolyExtStep::AndEqz(3261, 3580), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6871PolyExtStep::Mul(742, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6872PolyExtStep::Mul(743, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6873PolyExtStep::Mul(744, 5), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6874PolyExtStep::Mul(745, 4), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6875PolyExtStep::Add(741, 3581), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6876PolyExtStep::Add(3585, 3582), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6877PolyExtStep::Add(3586, 3583), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6878PolyExtStep::Add(3587, 3584), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6879PolyExtStep::Sub(3588, 1391), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6880PolyExtStep::AndEqz(3262, 3589), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6881PolyExtStep::AndEqz(3263, 1394), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6882PolyExtStep::AndEqz(3264, 1411), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6883PolyExtStep::AndEqz(3265, 1428), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6884PolyExtStep::AndEqz(3266, 1431), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6885PolyExtStep::AndEqz(3267, 591), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6886PolyExtStep::AndEqz(3268, 601), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6887PolyExtStep::AndEqz(3269, 615), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6888PolyExtStep::AndEqz(3270, 629), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6889PolyExtStep::AndEqz(3271, 639), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6890PolyExtStep::AndEqz(3272, 649), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6891PolyExtStep::AndEqz(3273, 659), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6892PolyExtStep::AndEqz(3274, 673), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6893PolyExtStep::AndEqz(3275, 544), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6894PolyExtStep::AndEqz(3276, 552), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6895PolyExtStep::AndCond(3236, 377, 3277), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6896PolyExtStep::AndEqz(0, 3548), // loc(callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :46:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6897PolyExtStep::AndEqz(3279, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6898PolyExtStep::AndEqz(3280, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6899PolyExtStep::AndEqz(3281, 3181), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6900PolyExtStep::AndEqz(3282, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6901PolyExtStep::Sub(1137, 62), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6902PolyExtStep::AndEqz(3283, 3590), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6903PolyExtStep::AndEqz(3284, 3183), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6904PolyExtStep::AndEqz(3285, 3184), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6905PolyExtStep::AndEqz(3286, 1901), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6906PolyExtStep::AndEqz(3287, 3570), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6907PolyExtStep::AndEqz(3288, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6908PolyExtStep::AndEqz(3289, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6909PolyExtStep::AndEqz(3290, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6910PolyExtStep::AndEqz(3291, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6911PolyExtStep::Sub(1372, 64), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6912PolyExtStep::AndEqz(3292, 3591), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6913PolyExtStep::AndEqz(3293, 3188), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6914PolyExtStep::AndEqz(3294, 3189), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6915PolyExtStep::AndEqz(3295, 2279), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6916PolyExtStep::AndEqz(3296, 3572), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6917PolyExtStep::Sub(1154, 3428), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :49:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6918PolyExtStep::AndEqz(3297, 3592), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :49:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6919PolyExtStep::Sub(811, 3430), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :50:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6920PolyExtStep::AndEqz(3298, 3593), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :50:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6921PolyExtStep::Sub(1391, 3432), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :51:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6922PolyExtStep::AndEqz(3299, 3594), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :51:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6923PolyExtStep::Sub(1392, 3434), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :52:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6924PolyExtStep::AndEqz(3300, 3595), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :52:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6925PolyExtStep::AndEqz(3301, 1394), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6926PolyExtStep::AndEqz(3302, 1411), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6927PolyExtStep::AndEqz(3303, 1428), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6928PolyExtStep::AndEqz(3304, 1431), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6929PolyExtStep::AndEqz(3305, 591), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6930PolyExtStep::AndEqz(3306, 601), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6931PolyExtStep::AndEqz(3307, 615), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6932PolyExtStep::AndEqz(3308, 629), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6933PolyExtStep::AndEqz(3309, 639), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6934PolyExtStep::AndEqz(3310, 649), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6935PolyExtStep::AndEqz(3311, 659), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6936PolyExtStep::AndEqz(3312, 673), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6937PolyExtStep::AndEqz(3313, 544), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6938PolyExtStep::AndEqz(3314, 552), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6939PolyExtStep::AndCond(3278, 380, 3315), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
6940PolyExtStep::AndEqz(0, 3549), // loc(callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :70:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6941PolyExtStep::AndEqz(3317, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6942PolyExtStep::AndEqz(3318, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6943PolyExtStep::AndEqz(3319, 3181), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6944PolyExtStep::AndEqz(3320, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6945PolyExtStep::AndEqz(3321, 3590), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6946PolyExtStep::AndEqz(3322, 3183), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6947PolyExtStep::AndEqz(3323, 3184), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6948PolyExtStep::AndEqz(3324, 1901), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6949PolyExtStep::AndEqz(3325, 3570), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6950PolyExtStep::AndEqz(3326, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6951PolyExtStep::AndEqz(3327, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6952PolyExtStep::AndEqz(3328, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6953PolyExtStep::AndEqz(3329, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6954PolyExtStep::AndEqz(3330, 3591), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6955PolyExtStep::AndEqz(3331, 3188), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6956PolyExtStep::AndEqz(3332, 3189), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6957PolyExtStep::AndEqz(3333, 2279), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6958PolyExtStep::AndEqz(3334, 3572), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6959PolyExtStep::AndEqz(3335, 3190), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6960PolyExtStep::AndEqz(3336, 3191), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6961PolyExtStep::AndEqz(3337, 3192), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6962PolyExtStep::AndEqz(3338, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6963PolyExtStep::Sub(1401, 65), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6964PolyExtStep::AndEqz(3339, 3596), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6965PolyExtStep::AndEqz(3340, 3194), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6966PolyExtStep::AndEqz(3341, 3195), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6967PolyExtStep::AndEqz(3342, 2280), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6968PolyExtStep::Sub(594, 3305), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6969PolyExtStep::AndEqz(3343, 3597), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6970PolyExtStep::AndEqz(3344, 1426), // loc(callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :76:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
6971PolyExtStep::AndEqz(3345, 2294), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :78:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6972PolyExtStep::Sub(1427, 622), // loc(callsite( builtin Sub at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :80:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6973PolyExtStep::AndEqz(3346, 2295), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :80:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6974PolyExtStep::Sub(632, 3598), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :80:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6975PolyExtStep::AndEqz(3347, 3599), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :80:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6976PolyExtStep::AndEqz(3348, 3196), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6977PolyExtStep::AndEqz(3349, 1854), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6978PolyExtStep::AndEqz(3350, 3312), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6979PolyExtStep::AndEqz(3351, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6980PolyExtStep::Sub(1829, 62), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6981PolyExtStep::AndEqz(3352, 3600), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6982PolyExtStep::AndEqz(3353, 2293), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6983PolyExtStep::Sub(608, 3314), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6984PolyExtStep::AndEqz(3354, 3601), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6985PolyExtStep::Sub(1439, 622), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6986PolyExtStep::AndEqz(3355, 3602), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6987PolyExtStep::AndEqz(3356, 1440), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6988PolyExtStep::AndEqz(3357, 2296), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :59:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6989PolyExtStep::Add(1697, 740), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:12) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
6990PolyExtStep::Sub(1391, 3603), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6991PolyExtStep::AndEqz(3358, 3604), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
6992PolyExtStep::AndEqz(3359, 2157), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6993PolyExtStep::AndEqz(3360, 3068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6994PolyExtStep::AndEqz(3361, 2068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6995PolyExtStep::AndEqz(3362, 3574), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
6996PolyExtStep::Add(741, 742), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6997PolyExtStep::Add(3605, 743), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6998PolyExtStep::Add(3606, 744), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
6999PolyExtStep::Sub(3607, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7000PolyExtStep::AndEqz(3363, 3608), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7001PolyExtStep::Mul(743, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7002PolyExtStep::Mul(744, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7003PolyExtStep::Add(742, 3609), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7004PolyExtStep::Add(3611, 3610), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7005PolyExtStep::Sub(3612, 740), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7006PolyExtStep::AndEqz(3364, 3613), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7007PolyExtStep::AndEqz(3365, 3074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7008PolyExtStep::Mul(646, 746), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7009PolyExtStep::Sub(3614, 3073), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7010PolyExtStep::AndEqz(3366, 3615), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7011PolyExtStep::Mul(745, 646), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7012PolyExtStep::AndEqz(3367, 3616), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7013PolyExtStep::Mul(745, 746), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7014PolyExtStep::AndEqz(3368, 3617), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7015PolyExtStep::Mul(745, 741), // loc(callsite( builtin Mul at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7016PolyExtStep::Sub(3618, 747), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7017PolyExtStep::AndEqz(3369, 3619), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7018PolyExtStep::Add(742, 743), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :66:35) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7019PolyExtStep::Add(3620, 744), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :66:48) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7020PolyExtStep::AndEqz(3370, 2297), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :59:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7021PolyExtStep::Mul(652, 5), // loc(callsite( builtin Mul at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7022PolyExtStep::Add(3622, 760), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:12) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7023PolyExtStep::Sub(622, 3623), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7024PolyExtStep::AndEqz(3371, 3624), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7025PolyExtStep::AndEqz(3372, 3001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7026PolyExtStep::AndEqz(3373, 3085), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7027PolyExtStep::Sub(1, 768), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7028PolyExtStep::Mul(768, 3625), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7029PolyExtStep::AndEqz(3374, 3626), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7030PolyExtStep::Sub(1, 769), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7031PolyExtStep::Mul(769, 3627), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7032PolyExtStep::AndEqz(3375, 3628), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7033PolyExtStep::Add(766, 767), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7034PolyExtStep::Add(3629, 768), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7035PolyExtStep::Add(3630, 769), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7036PolyExtStep::Sub(3631, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7037PolyExtStep::AndEqz(3376, 3632), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7038PolyExtStep::Mul(768, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7039PolyExtStep::Mul(769, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7040PolyExtStep::Add(767, 3633), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7041PolyExtStep::Add(3635, 3634), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7042PolyExtStep::Sub(3636, 760), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7043PolyExtStep::AndEqz(3377, 3637), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7044PolyExtStep::Sub(1, 761), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7045PolyExtStep::Mul(761, 3638), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7046PolyExtStep::AndEqz(3378, 3639), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7047PolyExtStep::Mul(652, 770), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7048PolyExtStep::Sub(3640, 3638), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7049PolyExtStep::AndEqz(3379, 3641), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7050PolyExtStep::Mul(761, 652), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7051PolyExtStep::AndEqz(3380, 3642), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7052PolyExtStep::Mul(761, 770), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7053PolyExtStep::AndEqz(3381, 3643), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7054PolyExtStep::Mul(761, 766), // loc(callsite( builtin Mul at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7055PolyExtStep::Sub(3644, 771), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7056PolyExtStep::AndEqz(3382, 3645), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7057PolyExtStep::Add(767, 768), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :66:35) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7058PolyExtStep::Add(3646, 769), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :66:48) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7059PolyExtStep::Mul(761, 3647), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :88:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7060PolyExtStep::Sub(3648, 772), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :88:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7061PolyExtStep::AndEqz(3383, 3649), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :88:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7062PolyExtStep::Add(772, 3621), // loc(callsite( builtin Add at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :90:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7063PolyExtStep::Mul(772, 3621), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :90:51) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7064PolyExtStep::Sub(3650, 3651), // loc(callsite( builtin Sub at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :90:37) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7065PolyExtStep::Sub(3652, 756), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :90:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7066PolyExtStep::AndEqz(3384, 3653), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :90:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7067PolyExtStep::AndEqz(3385, 659), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7068PolyExtStep::AndEqz(3386, 673), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7069PolyExtStep::AndEqz(3387, 544), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7070PolyExtStep::AndEqz(3388, 552), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7071PolyExtStep::AndCond(3316, 383, 3389), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7072PolyExtStep::AndEqz(0, 3550), // loc(callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :103:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7073PolyExtStep::AndEqz(3391, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7074PolyExtStep::AndEqz(3392, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7075PolyExtStep::AndEqz(3393, 3181), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7076PolyExtStep::AndEqz(3394, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7077PolyExtStep::AndEqz(3395, 3590), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7078PolyExtStep::AndEqz(3396, 3183), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7079PolyExtStep::AndEqz(3397, 3184), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7080PolyExtStep::AndEqz(3398, 1901), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7081PolyExtStep::AndEqz(3399, 3570), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7082PolyExtStep::AndEqz(3400, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7083PolyExtStep::AndEqz(3401, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7084PolyExtStep::AndEqz(3402, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7085PolyExtStep::AndEqz(3403, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7086PolyExtStep::AndEqz(3404, 3591), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7087PolyExtStep::AndEqz(3405, 3188), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7088PolyExtStep::AndEqz(3406, 3189), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7089PolyExtStep::AndEqz(3407, 2279), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7090PolyExtStep::AndEqz(3408, 3572), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7091PolyExtStep::AndEqz(3409, 3190), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7092PolyExtStep::AndEqz(3410, 3191), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7093PolyExtStep::AndEqz(3411, 3192), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7094PolyExtStep::AndEqz(3412, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7095PolyExtStep::AndEqz(3413, 3596), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7096PolyExtStep::AndEqz(3414, 3194), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7097PolyExtStep::AndEqz(3415, 3195), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7098PolyExtStep::AndEqz(3416, 2280), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7099PolyExtStep::AndEqz(3417, 3597), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7100PolyExtStep::AndEqz(3418, 811), // loc(callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :108:12) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7101PolyExtStep::AndEqz(3419, 1426), // loc(callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :109:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7102PolyExtStep::AndEqz(3420, 2294), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :111:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7103PolyExtStep::AndEqz(3421, 2295), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :113:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7104PolyExtStep::AndEqz(3422, 3599), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :113:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7105PolyExtStep::AndEqz(3423, 3196), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7106PolyExtStep::AndEqz(3424, 1854), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7107PolyExtStep::AndEqz(3425, 3312), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7108PolyExtStep::AndEqz(3426, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7109PolyExtStep::AndEqz(3427, 3600), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7110PolyExtStep::AndEqz(3428, 2293), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7111PolyExtStep::AndEqz(3429, 3601), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7112PolyExtStep::AndEqz(3430, 3602), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7113PolyExtStep::AndEqz(3431, 1440), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7114PolyExtStep::AndEqz(3432, 639), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7115PolyExtStep::AndEqz(3433, 649), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7116PolyExtStep::AndEqz(3434, 659), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7117PolyExtStep::AndEqz(3435, 673), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7118PolyExtStep::AndEqz(3436, 544), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7119PolyExtStep::AndEqz(3437, 552), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7120PolyExtStep::AndCond(3390, 386, 3438), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7121PolyExtStep::Get(486), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7122PolyExtStep::Get(492), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:52) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7123PolyExtStep::Get(498), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:58) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7124PolyExtStep::AndEqz(0, 3551), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :121:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7125PolyExtStep::Sub(3656, 1), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7126PolyExtStep::AndEqz(3440, 2294), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :59:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7127PolyExtStep::Mul(622, 5), // loc(callsite( builtin Mul at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:10) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7128PolyExtStep::Add(3658, 740), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:12) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7129PolyExtStep::Sub(3657, 3659), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7130PolyExtStep::AndEqz(3441, 3660), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7131PolyExtStep::AndEqz(3442, 2157), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7132PolyExtStep::AndEqz(3443, 3068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7133PolyExtStep::AndEqz(3444, 2068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7134PolyExtStep::AndEqz(3445, 3574), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7135PolyExtStep::AndEqz(3446, 3608), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7136PolyExtStep::AndEqz(3447, 3613), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7137PolyExtStep::AndEqz(3448, 3074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7138PolyExtStep::Mul(622, 746), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7139PolyExtStep::Sub(3661, 3073), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7140PolyExtStep::AndEqz(3449, 3662), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7141PolyExtStep::Mul(745, 622), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7142PolyExtStep::AndEqz(3450, 3663), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7143PolyExtStep::AndEqz(3451, 3617), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7144PolyExtStep::AndEqz(3452, 3619), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7145PolyExtStep::Mul(745, 3621), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :125:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7146PolyExtStep::Sub(3664, 760), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :125:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7147PolyExtStep::AndEqz(3453, 3665), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :125:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7148PolyExtStep::Sub(3655, 6), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7149PolyExtStep::AndEqz(3454, 3001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7150PolyExtStep::Mul(3666, 767), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7151PolyExtStep::Sub(3667, 3000), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7152PolyExtStep::AndEqz(3455, 3668), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7153PolyExtStep::Mul(766, 3666), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7154PolyExtStep::AndEqz(3456, 3669), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7155PolyExtStep::AndEqz(3457, 3005), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7156PolyExtStep::Add(760, 3000), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :132:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7157PolyExtStep::Mul(760, 3000), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :132:43) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7158PolyExtStep::Sub(3670, 3671), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :132:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7159PolyExtStep::Sub(3672, 768), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :132:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7160PolyExtStep::AndEqz(3458, 3673), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :132:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7161PolyExtStep::AndEqz(3459, 3628), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7162PolyExtStep::Mul(3657, 761), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7163PolyExtStep::Sub(3674, 3627), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7164PolyExtStep::AndEqz(3460, 3675), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7165PolyExtStep::Mul(769, 3657), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7166PolyExtStep::AndEqz(3461, 3676), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7167PolyExtStep::Mul(769, 761), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7168PolyExtStep::AndEqz(3462, 3677), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7169PolyExtStep::Sub(1, 770), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :136:24) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7170PolyExtStep::Mul(770, 3678), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :136:24) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7171PolyExtStep::AndEqz(3463, 3679), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :136:24) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7172PolyExtStep::Sub(3655, 770), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7173PolyExtStep::Mul(3680, 37), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7174PolyExtStep::Sub(1, 771), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7175PolyExtStep::Mul(771, 3682), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7176PolyExtStep::AndEqz(3464, 3683), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7177PolyExtStep::Sub(3681, 771), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7178PolyExtStep::AndEqz(3465, 3684), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7179PolyExtStep::AndEqz(3466, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7180PolyExtStep::AndEqz(3467, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7181PolyExtStep::AndEqz(3468, 3181), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7182PolyExtStep::AndEqz(3469, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7183PolyExtStep::Sub(1137, 3654), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7184PolyExtStep::AndEqz(3470, 3685), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7185PolyExtStep::AndEqz(3471, 3183), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7186PolyExtStep::AndEqz(3472, 3184), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7187PolyExtStep::AndEqz(3473, 1901), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7188PolyExtStep::AndEqz(3474, 3570), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7189PolyExtStep::AndEqz(3475, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7190PolyExtStep::AndEqz(3476, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7191PolyExtStep::AndEqz(3477, 3297), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7192PolyExtStep::AndEqz(3478, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7193PolyExtStep::Sub(1372, 3654), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7194PolyExtStep::AndEqz(3479, 3686), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7195PolyExtStep::AndEqz(3480, 2279), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7196PolyExtStep::AndEqz(3481, 3572), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7197PolyExtStep::Sub(1154, 1391), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :144:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7198PolyExtStep::AndEqz(0, 3687), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :144:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7199PolyExtStep::AndCond(3482, 771, 3483), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :143:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7200PolyExtStep::Sub(811, 1392), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :146:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7201PolyExtStep::AndEqz(0, 3688), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :146:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7202PolyExtStep::AndCond(3484, 3682, 3485), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :143:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7203PolyExtStep::Mul(771, 811), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :149:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7204PolyExtStep::Mul(3682, 1154), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :149:47) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7205PolyExtStep::Add(3689, 3690), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :149:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7206PolyExtStep::Mul(771, 1392), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :150:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7207PolyExtStep::Mul(3682, 1391), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :150:52) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7208PolyExtStep::Add(3692, 3693), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :150:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7209PolyExtStep::AndEqz(3486, 2320), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :152:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7210PolyExtStep::AndEqz(3487, 2346), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :152:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7211PolyExtStep::Add(1708, 666), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :152:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7212PolyExtStep::Sub(3691, 3695), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :152:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7213PolyExtStep::AndEqz(3488, 3696), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :152:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7214PolyExtStep::AndEqz(3489, 2368), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :153:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7215PolyExtStep::AndEqz(3490, 2925), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :153:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7216PolyExtStep::Mul(555, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :153:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7217PolyExtStep::Add(3697, 551), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :153:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7218PolyExtStep::Sub(3694, 3698), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :153:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7219PolyExtStep::AndEqz(3491, 3699), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :153:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7220PolyExtStep::Sub(666, 551), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :156:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7221PolyExtStep::AndEqz(0, 3700), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :156:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7222PolyExtStep::AndCond(3492, 770, 3493), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :155:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7223PolyExtStep::Sub(676, 555), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :158:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7224PolyExtStep::AndEqz(0, 3701), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :158:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7225PolyExtStep::AndCond(3494, 3678, 3495), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :155:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7226PolyExtStep::AndEqz(3496, 1394), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7227PolyExtStep::AndEqz(3497, 1411), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7228PolyExtStep::AndEqz(3498, 1428), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7229PolyExtStep::AndEqz(3499, 1431), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7230PolyExtStep::AndEqz(3500, 591), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7231PolyExtStep::AndEqz(3501, 601), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7232PolyExtStep::AndEqz(3502, 629), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7233PolyExtStep::AndEqz(3503, 639), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7234PolyExtStep::AndEqz(3504, 649), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7235PolyExtStep::AndCond(3439, 389, 3505), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7236PolyExtStep::AndEqz(0, 3552), // loc(callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :171:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7237PolyExtStep::AndEqz(3507, 2294), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :59:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7238PolyExtStep::Sub(3656, 3659), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7239PolyExtStep::AndEqz(3508, 3702), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7240PolyExtStep::AndEqz(3509, 2157), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7241PolyExtStep::AndEqz(3510, 3068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7242PolyExtStep::AndEqz(3511, 2068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7243PolyExtStep::AndEqz(3512, 3574), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7244PolyExtStep::AndEqz(3513, 3608), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7245PolyExtStep::AndEqz(3514, 3613), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7246PolyExtStep::AndEqz(3515, 3074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7247PolyExtStep::AndEqz(3516, 3662), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7248PolyExtStep::AndEqz(3517, 3663), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7249PolyExtStep::AndEqz(3518, 3617), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7250PolyExtStep::AndEqz(3519, 3619), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7251PolyExtStep::AndEqz(3520, 2295), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :59:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7252PolyExtStep::Add(690, 760), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:12) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7253PolyExtStep::Sub(622, 3703), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7254PolyExtStep::AndEqz(3521, 3704), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7255PolyExtStep::AndEqz(3522, 3001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7256PolyExtStep::AndEqz(3523, 3085), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7257PolyExtStep::AndEqz(3524, 3626), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7258PolyExtStep::AndEqz(3525, 3628), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7259PolyExtStep::AndEqz(3526, 3632), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7260PolyExtStep::AndEqz(3527, 3637), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7261PolyExtStep::AndEqz(3528, 3639), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7262PolyExtStep::Mul(632, 770), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7263PolyExtStep::Sub(3705, 3638), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7264PolyExtStep::AndEqz(3529, 3706), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7265PolyExtStep::Mul(761, 632), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7266PolyExtStep::AndEqz(3530, 3707), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7267PolyExtStep::AndEqz(3531, 3643), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7268PolyExtStep::AndEqz(3532, 3645), // loc(callsite( Reg ( <preamble> :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7269PolyExtStep::Add(3648, 3638), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :175:96) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7270PolyExtStep::Add(768, 769), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :176:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7271PolyExtStep::Mul(3709, 761), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :176:54) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7272PolyExtStep::Add(3710, 3638), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :176:69) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7273PolyExtStep::Add(3677, 3638), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :177:45) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7274PolyExtStep::Add(3708, 3711), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :180:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7275PolyExtStep::Add(3713, 3712), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :180:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7276PolyExtStep::Add(3714, 3638), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :180:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7277PolyExtStep::Mul(3708, 3654), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7278PolyExtStep::Sub(1, 3708), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:47) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7279PolyExtStep::Mul(3717, 349), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:60) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7280PolyExtStep::Add(3716, 3718), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:42) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7281PolyExtStep::Sub(3719, 772), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7282PolyExtStep::AndEqz(3533, 3720), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7283PolyExtStep::AndEqz(3534, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7284PolyExtStep::AndEqz(3535, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7285PolyExtStep::AndEqz(3536, 3291), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7286PolyExtStep::AndEqz(3537, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7287PolyExtStep::Sub(1137, 772), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7288PolyExtStep::AndEqz(3538, 3721), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7289PolyExtStep::AndEqz(3539, 1901), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7290PolyExtStep::AndEqz(3540, 3570), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7291PolyExtStep::Add(3654, 1), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7292PolyExtStep::Mul(3711, 3722), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7293PolyExtStep::Sub(1, 3711), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:47) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7294PolyExtStep::Mul(3724, 350), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:60) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7295PolyExtStep::Add(3723, 3725), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:42) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7296PolyExtStep::Sub(3726, 756), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7297PolyExtStep::AndEqz(3541, 3727), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7298PolyExtStep::AndEqz(3542, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7299PolyExtStep::AndEqz(3543, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7300PolyExtStep::AndEqz(3544, 3297), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7301PolyExtStep::AndEqz(3545, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7302PolyExtStep::Sub(1372, 756), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7303PolyExtStep::AndEqz(3546, 3728), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7304PolyExtStep::AndEqz(3547, 2279), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7305PolyExtStep::AndEqz(3548, 3572), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7306PolyExtStep::Add(3654, 7), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7307PolyExtStep::Mul(3712, 3729), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7308PolyExtStep::Sub(1, 3712), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:47) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7309PolyExtStep::Mul(3731, 351), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:60) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7310PolyExtStep::Add(3730, 3732), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:42) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7311PolyExtStep::Sub(3733, 757), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7312PolyExtStep::AndEqz(3549, 3734), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7313PolyExtStep::AndEqz(3550, 3190), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7314PolyExtStep::AndEqz(3551, 3191), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7315PolyExtStep::AndEqz(3552, 3303), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7316PolyExtStep::AndEqz(3553, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7317PolyExtStep::Sub(1401, 757), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7318PolyExtStep::AndEqz(3554, 3735), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7319PolyExtStep::AndEqz(3555, 2280), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7320PolyExtStep::AndEqz(3556, 3597), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7321PolyExtStep::Add(3654, 6), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7322PolyExtStep::Mul(3638, 3736), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7323PolyExtStep::Sub(1, 3638), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:47) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7324PolyExtStep::Mul(3738, 352), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:60) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7325PolyExtStep::Add(3737, 3739), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:42) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7326PolyExtStep::Sub(3740, 762), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7327PolyExtStep::AndEqz(3557, 3741), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7328PolyExtStep::AndEqz(3558, 3196), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7329PolyExtStep::AndEqz(3559, 1854), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7330PolyExtStep::AndEqz(3560, 3312), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7331PolyExtStep::AndEqz(3561, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7332PolyExtStep::Sub(1829, 762), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7333PolyExtStep::AndEqz(3562, 3742), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7334PolyExtStep::AndEqz(3563, 2293), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7335PolyExtStep::AndEqz(3564, 3601), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7336PolyExtStep::Sub(622, 3715), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:39) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7337PolyExtStep::Sub(1, 781), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7338PolyExtStep::Mul(781, 3744), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7339PolyExtStep::AndEqz(3565, 3745), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7340PolyExtStep::Mul(3743, 732), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7341PolyExtStep::Sub(3746, 3744), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7342PolyExtStep::AndEqz(3566, 3747), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7343PolyExtStep::Mul(781, 3743), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7344PolyExtStep::AndEqz(3567, 3748), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7345PolyExtStep::Mul(781, 732), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7346PolyExtStep::AndEqz(3568, 3749), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7347PolyExtStep::Sub(1, 3621), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :186:37) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7348PolyExtStep::Mul(781, 3750), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :186:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7349PolyExtStep::Sub(3751, 737), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :186:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7350PolyExtStep::AndEqz(3569, 3752), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :186:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7351PolyExtStep::AndEqz(3570, 639), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7352PolyExtStep::AndEqz(3571, 649), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7353PolyExtStep::AndEqz(3572, 659), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7354PolyExtStep::AndEqz(3573, 673), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7355PolyExtStep::AndEqz(3574, 544), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7356PolyExtStep::AndEqz(3575, 552), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7357PolyExtStep::AndCond(3506, 392, 3576), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7358PolyExtStep::AndEqz(1229, 1148), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7359PolyExtStep::AndEqz(3578, 1160), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7360PolyExtStep::AndEqz(3579, 1383), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7361PolyExtStep::AndEqz(3580, 1394), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7362PolyExtStep::AndEqz(3581, 1411), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7363PolyExtStep::AndEqz(3582, 1428), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7364PolyExtStep::AndEqz(3583, 1431), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7365PolyExtStep::AndEqz(3584, 1900), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7366PolyExtStep::AndEqz(3585, 2278), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7367PolyExtStep::AndEqz(3586, 591), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7368PolyExtStep::AndEqz(3587, 601), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7369PolyExtStep::AndEqz(3588, 615), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7370PolyExtStep::AndEqz(3589, 629), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7371PolyExtStep::AndEqz(3590, 639), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7372PolyExtStep::AndEqz(3591, 649), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7373PolyExtStep::AndEqz(3592, 659), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7374PolyExtStep::AndEqz(3593, 673), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7375PolyExtStep::AndEqz(3594, 544), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7376PolyExtStep::AndEqz(3595, 552), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7377PolyExtStep::AndCond(3577, 395, 3596), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7378PolyExtStep::AndCond(3597, 398, 3596), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7379PolyExtStep::Get(571), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7380PolyExtStep::Get(576), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7381PolyExtStep::Get(581), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7382PolyExtStep::Get(586), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7383PolyExtStep::Get(591), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7384PolyExtStep::Get(596), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7385PolyExtStep::Mul(3753, 11), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7386PolyExtStep::Mul(3754, 10), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7387PolyExtStep::Mul(3755, 9), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7388PolyExtStep::Mul(3756, 23), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7389PolyExtStep::Mul(3757, 24), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7390PolyExtStep::Mul(3758, 53), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7391PolyExtStep::Add(3759, 3760), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7392PolyExtStep::Add(3765, 3761), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7393PolyExtStep::Add(3766, 3762), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7394PolyExtStep::Add(3767, 3763), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7395PolyExtStep::Add(3768, 3764), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7396PolyExtStep::Mul(3769, 377), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7397PolyExtStep::Mul(792, 13), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :94:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7398PolyExtStep::Sub(1, 792), // loc(callsite( builtin Sub at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :96:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7399PolyExtStep::Mul(3772, 1768), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :96:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7400PolyExtStep::Mul(3773, 8), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :96:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7401PolyExtStep::Add(3771, 3774), // loc(callsite( builtin Add at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :94:37) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7402PolyExtStep::Sub(1, 1768), // loc(callsite( builtin Sub at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :98:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7403PolyExtStep::Mul(3772, 3776), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :98:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7404PolyExtStep::Mul(3777, 34), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :98:42) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7405PolyExtStep::Add(3775, 3778), // loc(callsite( builtin Add at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :96:59) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7406PolyExtStep::Mul(3779, 383), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7407PolyExtStep::Get(626), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :132:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7408PolyExtStep::Get(631), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :8:23) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7409PolyExtStep::Mul(3782, 13), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :162:6) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7410PolyExtStep::Sub(1, 3782), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :164:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7411PolyExtStep::Mul(3784, 3781), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :164:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7412PolyExtStep::Mul(3785, 8), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :164:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7413PolyExtStep::Add(3783, 3786), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :162:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7414PolyExtStep::Sub(1, 3781), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :166:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7415PolyExtStep::Mul(3784, 3788), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :166:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7416PolyExtStep::Mul(3789, 34), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :166:33) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7417PolyExtStep::Add(3787, 3790), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :164:50) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7418PolyExtStep::Mul(3791, 389), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7419PolyExtStep::Get(671), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :8:23) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7420PolyExtStep::Get(681), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :186:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7421PolyExtStep::Mul(3794, 13), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :189:6) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7422PolyExtStep::Sub(1, 3794), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :191:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7423PolyExtStep::Mul(3796, 3793), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :191:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7424PolyExtStep::Mul(3797, 8), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :191:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7425PolyExtStep::Add(3795, 3798), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :189:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7426PolyExtStep::Sub(1, 3793), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :193:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7427PolyExtStep::Mul(3796, 3800), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :193:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7428PolyExtStep::Mul(3801, 34), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :193:41) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7429PolyExtStep::Add(3799, 3802), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :191:58) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7430PolyExtStep::Mul(3803, 392), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7431PolyExtStep::Add(3770, 3553), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7432PolyExtStep::Add(3805, 3780), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7433PolyExtStep::Add(3806, 3554), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7434PolyExtStep::Add(3807, 3792), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7435PolyExtStep::Add(3808, 3804), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7436PolyExtStep::Get(227), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7437PolyExtStep::Get(419), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :59:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7438PolyExtStep::Mul(3810, 14), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :85:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7439PolyExtStep::Add(3812, 3811), // loc(callsite( builtin Add at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :85:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7440PolyExtStep::Mul(3813, 383), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7441PolyExtStep::Get(486), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7442PolyExtStep::Sub(1, 1764), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :128:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7443PolyExtStep::Add(3815, 1), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :129:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7444PolyExtStep::Mul(1764, 3817), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :129:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7445PolyExtStep::Mul(3816, 3815), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :129:49) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7446PolyExtStep::Add(3818, 3819), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :129:45) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7447PolyExtStep::Mul(3820, 389), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7448PolyExtStep::Get(621), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7449PolyExtStep::Get(636), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :8:23) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7450PolyExtStep::Add(3822, 3781), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :175:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7451PolyExtStep::Add(3824, 3782), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :175:53) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7452PolyExtStep::Mul(3825, 3823), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :175:79) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7453PolyExtStep::Sub(1, 3823), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :175:108) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7454PolyExtStep::Add(3826, 3827), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :175:96) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7455PolyExtStep::Add(3781, 3782), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :176:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7456PolyExtStep::Mul(3829, 3823), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :176:54) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7457PolyExtStep::Add(3830, 3827), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :176:69) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7458PolyExtStep::Mul(3782, 3823), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :177:29) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7459PolyExtStep::Add(3832, 3827), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :177:45) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7460PolyExtStep::Add(3828, 3831), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :180:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7461PolyExtStep::Add(3834, 3833), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :180:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7462PolyExtStep::Add(3835, 3827), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :180:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7463PolyExtStep::Add(3815, 3836), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :194:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7464PolyExtStep::Mul(3837, 392), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7465PolyExtStep::Add(3814, 3821), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7466PolyExtStep::Add(3839, 3838), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7467PolyExtStep::Mul(3753, 383), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7468PolyExtStep::Get(492), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:52) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7469PolyExtStep::Add(3842, 1), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :130:36) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7470PolyExtStep::Mul(3816, 3843), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :130:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7471PolyExtStep::Mul(3844, 389), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7472PolyExtStep::Add(3841, 3845), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7473PolyExtStep::Get(395), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :78:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7474PolyExtStep::Mul(3847, 383), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7475PolyExtStep::Get(498), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:58) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7476PolyExtStep::Sub(3849, 1), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :167:53) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7477PolyExtStep::Mul(3850, 389), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7478PolyExtStep::Mul(3836, 5), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :194:53) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7479PolyExtStep::Sub(3849, 3852), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :194:47) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7480PolyExtStep::Mul(3853, 392), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7481PolyExtStep::Add(3848, 3851), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7482PolyExtStep::Add(3855, 3854), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7483PolyExtStep::Sub(3840, 556), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :214:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7484PolyExtStep::AndEqz(3598, 3857), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :214:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7485PolyExtStep::Sub(3846, 563), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :215:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7486PolyExtStep::AndEqz(3599, 3858), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :215:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7487PolyExtStep::Sub(3856, 564), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :216:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7488PolyExtStep::AndEqz(3600, 3859), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :216:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7489PolyExtStep::Sub(3809, 5), // loc(callsite( builtin Sub at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:31) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7490PolyExtStep::AndEqz(3601, 1735), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7491PolyExtStep::Mul(3860, 798), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7492PolyExtStep::Sub(3861, 1734), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7493PolyExtStep::AndEqz(3602, 3862), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7494PolyExtStep::Mul(764, 3860), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7495PolyExtStep::AndEqz(3603, 3863), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7496PolyExtStep::Mul(764, 798), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7497PolyExtStep::AndEqz(3604, 3864), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7498PolyExtStep::Sub(3809, 13), // loc(callsite( builtin Sub at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7499PolyExtStep::AndEqz(3605, 3022), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7500PolyExtStep::Mul(3865, 802), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7501PolyExtStep::Sub(3866, 3021), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7502PolyExtStep::AndEqz(3606, 3867), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7503PolyExtStep::Mul(800, 3865), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7504PolyExtStep::AndEqz(3607, 3868), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7505PolyExtStep::Mul(800, 802), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7506PolyExtStep::AndEqz(3608, 3869), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7507PolyExtStep::Sub(3809, 23), // loc(callsite( builtin Sub at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:31) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7508PolyExtStep::Sub(1, 804), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7509PolyExtStep::Mul(804, 3871), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7510PolyExtStep::AndEqz(3609, 3872), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7511PolyExtStep::Mul(3870, 814), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7512PolyExtStep::Sub(3873, 3871), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7513PolyExtStep::AndEqz(3610, 3874), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7514PolyExtStep::Mul(804, 3870), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7515PolyExtStep::AndEqz(3611, 3875), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7516PolyExtStep::Mul(804, 814), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7517PolyExtStep::AndEqz(3612, 3876), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7518PolyExtStep::Sub(3809, 24), // loc(callsite( builtin Sub at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7519PolyExtStep::AndEqz(3613, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7520PolyExtStep::Mul(3877, 820), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7521PolyExtStep::Sub(3878, 818), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7522PolyExtStep::AndEqz(3614, 3879), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7523PolyExtStep::Mul(817, 3877), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7524PolyExtStep::AndEqz(3615, 3880), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7525PolyExtStep::Mul(817, 820), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7526PolyExtStep::AndEqz(3616, 3881), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7527PolyExtStep::Sub(3809, 53), // loc(callsite( builtin Sub at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7528PolyExtStep::AndEqz(3617, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7529PolyExtStep::Mul(3882, 826), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7530PolyExtStep::Sub(3883, 824), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7531PolyExtStep::AndEqz(3618, 3884), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7532PolyExtStep::Mul(823, 3882), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7533PolyExtStep::AndEqz(3619, 3885), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7534PolyExtStep::Mul(823, 826), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7535PolyExtStep::AndEqz(3620, 3886), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7536PolyExtStep::Add(764, 800), // loc(callsite( builtin Add at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:60) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7537PolyExtStep::Add(3887, 804), // loc(callsite( builtin Add at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:72) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7538PolyExtStep::Add(3888, 817), // loc(callsite( builtin Add at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:83) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7539PolyExtStep::Add(3889, 823), // loc(callsite( builtin Add at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:95) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7540PolyExtStep::Mul(3890, 5), // loc(callsite( builtin Mul at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:121) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7541PolyExtStep::Add(368, 3891), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7542PolyExtStep::Sub(829, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7543PolyExtStep::AndEqz(3621, 3893), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7544PolyExtStep::AndEqz(3622, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7545PolyExtStep::Mul(835, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7546PolyExtStep::Add(3894, 832), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7547PolyExtStep::Sub(3892, 3895), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7548PolyExtStep::AndEqz(3623, 3896), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7549PolyExtStep::Add(370, 835), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7550PolyExtStep::AndEqz(3624, 2228), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7551PolyExtStep::AndEqz(3625, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7552PolyExtStep::Sub(3897, 3151), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7553PolyExtStep::AndEqz(3626, 3898), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7554PolyExtStep::AndCond(3222, 446, 3627), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
7555PolyExtStep::Add(376, 23), // loc(callsite( builtin Add at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:42) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7556PolyExtStep::Sub(371, 3899), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7557PolyExtStep::Mul(374, 56), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :110:15) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7558PolyExtStep::Mul(3901, 55), // loc(callsite( builtin Mul at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :114:22) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7559PolyExtStep::Sub(1, 3901), // loc(callsite( builtin Sub at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :114:46) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7560PolyExtStep::Mul(3903, 54), // loc(callsite( builtin Mul at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :114:57) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7561PolyExtStep::Add(3902, 3904), // loc(callsite( builtin Add at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :114:32) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7562PolyExtStep::Sub(1090, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :469:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7563PolyExtStep::AndEqz(0, 3906), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :469:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7564PolyExtStep::AndEqz(3629, 2740), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :469:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7565PolyExtStep::AndEqz(3630, 3900), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7566PolyExtStep::AndEqz(0, 2755), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7567PolyExtStep::Mul(3158, 2760), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7568PolyExtStep::Sub(3907, 2754), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7569PolyExtStep::AndEqz(3632, 3908), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7570PolyExtStep::Mul(2753, 3158), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7571PolyExtStep::AndEqz(3633, 3909), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7572PolyExtStep::Mul(2753, 2760), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7573PolyExtStep::AndEqz(3634, 3910), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7574PolyExtStep::Sub(0, 807), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7575PolyExtStep::AndEqz(0, 3911), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7576PolyExtStep::Sub(0, 1137), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7577PolyExtStep::AndEqz(3636, 3912), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7578PolyExtStep::Sub(3905, 808), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7579PolyExtStep::AndEqz(3637, 3913), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7580PolyExtStep::Sub(1, 1143), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7581PolyExtStep::AndEqz(3638, 3914), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7582PolyExtStep::Sub(1, 809), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7583PolyExtStep::AndEqz(3639, 3915), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7584PolyExtStep::Sub(1, 1148), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7585PolyExtStep::AndEqz(3640, 3916), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7586PolyExtStep::Sub(57, 810), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7587PolyExtStep::AndEqz(3641, 3917), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7588PolyExtStep::Sub(0, 1154), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7589PolyExtStep::AndEqz(3642, 3918), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7590PolyExtStep::Sub(0, 811), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7591PolyExtStep::AndEqz(3643, 3919), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7592PolyExtStep::Sub(0, 1160), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7593PolyExtStep::AndEqz(3644, 3920), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7594PolyExtStep::Sub(374, 1372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7595PolyExtStep::AndEqz(3645, 3921), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7596PolyExtStep::Sub(0, 1373), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7597PolyExtStep::AndEqz(3646, 3922), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7598PolyExtStep::Sub(0, 1375), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7599PolyExtStep::AndEqz(3647, 3923), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7600PolyExtStep::Sub(0, 1382), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7601PolyExtStep::AndEqz(3648, 3924), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7602PolyExtStep::Sub(0, 1383), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7603PolyExtStep::AndEqz(3649, 3925), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7604PolyExtStep::Sub(0, 1385), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7605PolyExtStep::AndEqz(3650, 3926), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7606PolyExtStep::Sub(0, 1391), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7607PolyExtStep::AndEqz(3651, 3927), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7608PolyExtStep::Sub(0, 1392), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7609PolyExtStep::AndEqz(3652, 3928), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7610PolyExtStep::Sub(0, 1394), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7611PolyExtStep::AndEqz(3653, 3929), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7612PolyExtStep::Sub(0, 1401), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7613PolyExtStep::AndEqz(3654, 3930), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7614PolyExtStep::Sub(0, 1402), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7615PolyExtStep::AndEqz(3655, 3931), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7616PolyExtStep::Sub(0, 1404), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7617PolyExtStep::AndEqz(3656, 3932), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7618PolyExtStep::Sub(0, 1410), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7619PolyExtStep::AndEqz(3657, 3933), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7620PolyExtStep::Sub(0, 1411), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7621PolyExtStep::AndEqz(3658, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7622PolyExtStep::Sub(0, 1424), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7623PolyExtStep::AndEqz(3659, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7624PolyExtStep::Sub(0, 1427), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7625PolyExtStep::AndEqz(3660, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7626PolyExtStep::Sub(0, 1426), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7627PolyExtStep::AndEqz(3661, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7628PolyExtStep::Sub(0, 1428), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7629PolyExtStep::AndEqz(3662, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7630PolyExtStep::Sub(0, 1829), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7631PolyExtStep::AndEqz(3663, 3939), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7632PolyExtStep::Sub(0, 1830), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7633PolyExtStep::AndEqz(3664, 3940), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7634PolyExtStep::Sub(0, 1429), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7635PolyExtStep::AndEqz(3665, 3941), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7636PolyExtStep::Sub(0, 1430), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7637PolyExtStep::AndEqz(3666, 3942), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7638PolyExtStep::Sub(0, 1431), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7639PolyExtStep::AndEqz(3667, 3943), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7640PolyExtStep::Sub(0, 1432), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7641PolyExtStep::AndEqz(3668, 3944), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7642PolyExtStep::Sub(0, 1439), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7643PolyExtStep::AndEqz(3669, 3945), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7644PolyExtStep::Mul(2278, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7645PolyExtStep::Add(538, 3946), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7646PolyExtStep::Mul(3947, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7647PolyExtStep::Add(1900, 3948), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7648PolyExtStep::Mul(3949, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7649PolyExtStep::Add(1440, 3950), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7650PolyExtStep::Sub(3951, 58), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7651PolyExtStep::AndEqz(3670, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7652PolyExtStep::AndEqz(3671, 539), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7653PolyExtStep::AndEqz(3672, 615), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7654PolyExtStep::AndEqz(3673, 639), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7655PolyExtStep::AndEqz(3674, 666), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7656PolyExtStep::AndEqz(3675, 551), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7657PolyExtStep::AndEqz(3676, 564), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7658PolyExtStep::AndEqz(3677, 573), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7659PolyExtStep::AndEqz(3678, 578), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7660PolyExtStep::AndEqz(3679, 838), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7661PolyExtStep::AndEqz(3680, 844), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7662PolyExtStep::AndEqz(3681, 850), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7663PolyExtStep::AndEqz(3682, 856), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7664PolyExtStep::AndCond(3635, 2753, 3683), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7665PolyExtStep::Sub(539, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7666PolyExtStep::AndEqz(0, 3953), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7667PolyExtStep::AndEqz(3685, 2294), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7668PolyExtStep::Sub(622, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7669PolyExtStep::AndEqz(3686, 3954), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7670PolyExtStep::AndEqz(3687, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7671PolyExtStep::Sub(591, 62), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7672PolyExtStep::AndEqz(3688, 3955), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7673PolyExtStep::Sub(601, 629), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7674PolyExtStep::AndEqz(3689, 3956), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7675PolyExtStep::Sub(608, 632), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7676PolyExtStep::AndEqz(3690, 3957), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7677PolyExtStep::Sub(622, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7678PolyExtStep::Sub(3958, 594), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7679PolyExtStep::AndEqz(3691, 2228), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7680PolyExtStep::Sub(841, 3959), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7681PolyExtStep::AndEqz(3692, 3960), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7682PolyExtStep::Mul(632, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7683PolyExtStep::Mul(629, 63), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7684PolyExtStep::Add(3961, 3962), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7685PolyExtStep::Sub(639, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7686PolyExtStep::AndEqz(3693, 3964), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7687PolyExtStep::Sub(666, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7688PolyExtStep::AndEqz(3694, 3965), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7689PolyExtStep::Sub(673, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7690PolyExtStep::AndEqz(3695, 3966), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7691PolyExtStep::AndEqz(3696, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7692PolyExtStep::Sub(646, 64), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7693PolyExtStep::AndEqz(3697, 3967), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7694PolyExtStep::Sub(652, 676), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7695PolyExtStep::AndEqz(3698, 3968), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7696PolyExtStep::Sub(659, 544), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7697PolyExtStep::AndEqz(3699, 3969), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7698PolyExtStep::Sub(2346, 649), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7699PolyExtStep::Sub(844, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7700PolyExtStep::AndEqz(3700, 3971), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7701PolyExtStep::Sub(847, 3970), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7702PolyExtStep::AndEqz(3701, 3972), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7703PolyExtStep::Mul(544, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7704PolyExtStep::Mul(676, 63), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7705PolyExtStep::Add(3973, 3974), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7706PolyExtStep::Sub(551, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7707PolyExtStep::AndEqz(3702, 3976), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7708PolyExtStep::Sub(564, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7709PolyExtStep::AndEqz(3703, 3977), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7710PolyExtStep::Sub(571, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7711PolyExtStep::AndEqz(3704, 3978), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7712PolyExtStep::AndEqz(3705, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7713PolyExtStep::Sub(552, 65), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7714PolyExtStep::AndEqz(3706, 3979), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7715PolyExtStep::Sub(556, 570), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7716PolyExtStep::AndEqz(3707, 3980), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7717PolyExtStep::Sub(563, 572), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7718PolyExtStep::AndEqz(3708, 3981), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7719PolyExtStep::Sub(1647, 555), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7720PolyExtStep::Sub(850, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7721PolyExtStep::AndEqz(3709, 3983), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7722PolyExtStep::Sub(853, 3982), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7723PolyExtStep::AndEqz(3710, 3984), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
7724PolyExtStep::Mul(572, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7725PolyExtStep::Mul(570, 63), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7726PolyExtStep::Add(3985, 3986), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7727PolyExtStep::AndEqz(3711, 1652), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7728PolyExtStep::AndEqz(3712, 1658), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7729PolyExtStep::Sub(587, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7730PolyExtStep::AndEqz(3713, 3988), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7731PolyExtStep::AndEqz(3714, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7732PolyExtStep::Sub(574, 66), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7733PolyExtStep::AndEqz(3715, 3989), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7734PolyExtStep::AndEqz(3716, 1657), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7735PolyExtStep::Sub(577, 739), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7736PolyExtStep::AndEqz(3717, 3990), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7737PolyExtStep::Sub(589, 575), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7738PolyExtStep::Sub(856, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7739PolyExtStep::AndEqz(3718, 3992), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7740PolyExtStep::Sub(859, 3991), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7741PolyExtStep::AndEqz(3719, 3993), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7742PolyExtStep::Sub(1, 2736), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7743PolyExtStep::Mul(2736, 3994), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7744PolyExtStep::AndEqz(3720, 3995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7745PolyExtStep::Mul(3963, 2737), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7746PolyExtStep::Sub(3996, 3994), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7747PolyExtStep::AndEqz(3721, 3997), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7748PolyExtStep::Mul(2736, 3963), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7749PolyExtStep::AndEqz(3722, 3998), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7750PolyExtStep::Mul(2736, 2737), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7751PolyExtStep::AndEqz(3723, 3999), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7752PolyExtStep::Sub(1, 2744), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :94:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7753PolyExtStep::Mul(2744, 4000), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :94:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7754PolyExtStep::AndEqz(3724, 4001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :94:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7755PolyExtStep::Sub(1, 2745), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :95:28) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7756PolyExtStep::Mul(2745, 4002), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :95:28) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7757PolyExtStep::AndEqz(3725, 4003), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :95:28) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7758PolyExtStep::Mul(2744, 29), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :96:24) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7759PolyExtStep::Mul(2745, 14), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :96:42) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7760PolyExtStep::Add(4004, 4005), // loc(callsite( builtin Add at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :96:33) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7761PolyExtStep::Sub(739, 4006), // loc(callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :96:22) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7762PolyExtStep::AndEqz(3726, 4007), // loc(callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :96:22) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7763PolyExtStep::Sub(1, 2750), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7764PolyExtStep::Mul(2750, 4008), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7765PolyExtStep::AndEqz(3727, 4009), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7766PolyExtStep::Mul(588, 2751), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7767PolyExtStep::Sub(4010, 4008), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7768PolyExtStep::AndEqz(3728, 4011), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7769PolyExtStep::Mul(2750, 588), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7770PolyExtStep::AndEqz(3729, 4012), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7771PolyExtStep::Mul(2750, 2751), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7772PolyExtStep::AndEqz(3730, 4013), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7773PolyExtStep::Mul(2750, 13), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :101:6) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7774PolyExtStep::Mul(4008, 3994), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :102:20) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7775PolyExtStep::Mul(4015, 59), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :102:24) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7776PolyExtStep::Add(4014, 4016), // loc(callsite( builtin Add at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :101:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7777PolyExtStep::Sub(1, 3994), // loc(callsite( builtin Sub at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :103:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7778PolyExtStep::Mul(4008, 4018), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :103:20) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7779PolyExtStep::Mul(4019, 60), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :103:37) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7780PolyExtStep::Add(4017, 4020), // loc(callsite( builtin Add at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :102:58) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7781PolyExtStep::Sub(3994, 807), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7782PolyExtStep::AndEqz(3731, 4022), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7783PolyExtStep::Sub(3963, 1137), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7784PolyExtStep::AndEqz(3732, 4023), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7785PolyExtStep::Sub(3987, 808), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7786PolyExtStep::AndEqz(3733, 4024), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7787PolyExtStep::Sub(2744, 1143), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7788PolyExtStep::AndEqz(3734, 4025), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7789PolyExtStep::Sub(2745, 809), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7790PolyExtStep::AndEqz(3735, 4026), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7791PolyExtStep::Sub(0, 1148), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7792PolyExtStep::AndEqz(3736, 4027), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7793PolyExtStep::Sub(4021, 810), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7794PolyExtStep::AndEqz(3737, 4028), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7795PolyExtStep::AndEqz(3738, 3918), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7796PolyExtStep::Sub(3975, 811), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7797PolyExtStep::AndEqz(3739, 4029), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7798PolyExtStep::Sub(588, 1160), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7799PolyExtStep::AndEqz(3740, 4030), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7800PolyExtStep::AndEqz(3741, 3921), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7801PolyExtStep::AndEqz(3742, 3922), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7802PolyExtStep::AndEqz(3743, 3923), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7803PolyExtStep::AndEqz(3744, 3924), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7804PolyExtStep::AndEqz(3745, 3925), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7805PolyExtStep::AndEqz(3746, 3926), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7806PolyExtStep::AndEqz(3747, 3927), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7807PolyExtStep::AndEqz(3748, 3928), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7808PolyExtStep::AndEqz(3749, 3929), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7809PolyExtStep::AndEqz(3750, 3930), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7810PolyExtStep::AndEqz(3751, 3931), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7811PolyExtStep::AndEqz(3752, 3932), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7812PolyExtStep::AndEqz(3753, 3933), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7813PolyExtStep::AndEqz(3754, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7814PolyExtStep::AndEqz(3755, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7815PolyExtStep::AndEqz(3756, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7816PolyExtStep::AndEqz(3757, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7817PolyExtStep::AndEqz(3758, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7818PolyExtStep::AndEqz(3759, 3939), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7819PolyExtStep::AndEqz(3760, 3940), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7820PolyExtStep::AndEqz(3761, 3941), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7821PolyExtStep::AndEqz(3762, 3942), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7822PolyExtStep::AndEqz(3763, 3943), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7823PolyExtStep::AndEqz(3764, 3944), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7824PolyExtStep::AndEqz(3765, 3945), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7825PolyExtStep::AndEqz(3766, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7826PolyExtStep::AndCond(3684, 2754, 3767), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
7827PolyExtStep::AndEqz(3768, 740), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7828PolyExtStep::AndEqz(3769, 745), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7829PolyExtStep::AndEqz(3770, 766), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7830PolyExtStep::AndEqz(3771, 770), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7831PolyExtStep::AndEqz(3772, 757), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7832PolyExtStep::AndEqz(3773, 764), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7833PolyExtStep::AndEqz(3774, 804), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7834PolyExtStep::AndEqz(3775, 826), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7835PolyExtStep::AndEqz(3776, 893), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7836PolyExtStep::AndEqz(3777, 899), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7837PolyExtStep::AndEqz(3778, 905), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7838PolyExtStep::AndEqz(3779, 911), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7839PolyExtStep::AndEqz(3780, 917), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7840PolyExtStep::AndEqz(3781, 920), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7841PolyExtStep::AndEqz(3782, 923), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7842PolyExtStep::AndEqz(3783, 929), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7843PolyExtStep::AndEqz(3784, 932), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7844PolyExtStep::AndEqz(3785, 935), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7845PolyExtStep::AndEqz(3786, 972), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7846PolyExtStep::AndEqz(3787, 975), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7847PolyExtStep::AndEqz(3788, 978), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7848PolyExtStep::AndEqz(3789, 984), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7849PolyExtStep::AndEqz(3790, 987), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7850PolyExtStep::AndEqz(3791, 990), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7851PolyExtStep::AndEqz(3792, 996), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7852PolyExtStep::AndEqz(3793, 999), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7853PolyExtStep::AndEqz(3794, 1002), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7854PolyExtStep::AndEqz(3795, 1008), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7855PolyExtStep::AndEqz(3796, 1011), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7856PolyExtStep::AndEqz(3797, 1014), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7857PolyExtStep::AndEqz(3798, 1051), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7858PolyExtStep::AndEqz(3799, 1054), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7859PolyExtStep::AndEqz(3800, 1057), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7860PolyExtStep::AndEqz(3801, 1063), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7861PolyExtStep::AndEqz(3802, 1066), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7862PolyExtStep::AndEqz(3803, 1069), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7863PolyExtStep::AndEqz(3804, 1075), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7864PolyExtStep::AndEqz(3805, 1081), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7865PolyExtStep::AndCond(3631, 377, 3806), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
7866PolyExtStep::Get(155), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7867PolyExtStep::Get(157), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7868PolyExtStep::Get(159), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7869PolyExtStep::Get(161), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7870PolyExtStep::Get(163), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7871PolyExtStep::Get(165), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7872PolyExtStep::Get(174), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7873PolyExtStep::Get(180), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7874PolyExtStep::Get(186), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7875PolyExtStep::Sub(591, 4032), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7876PolyExtStep::AndEqz(3688, 4040), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7877PolyExtStep::AndEqz(3808, 3956), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7878PolyExtStep::AndEqz(3809, 3957), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7879PolyExtStep::AndEqz(3810, 2228), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7880PolyExtStep::AndEqz(3811, 3960), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7881PolyExtStep::Mul(632, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7882PolyExtStep::Add(4041, 629), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7883PolyExtStep::Add(4032, 1), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7884PolyExtStep::AndEqz(3812, 3964), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7885PolyExtStep::AndEqz(3813, 3965), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7886PolyExtStep::AndEqz(3814, 3966), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7887PolyExtStep::AndEqz(3815, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7888PolyExtStep::Sub(646, 4043), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7889PolyExtStep::AndEqz(3816, 4044), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7890PolyExtStep::AndEqz(3817, 3968), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7891PolyExtStep::AndEqz(3818, 3969), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7892PolyExtStep::AndEqz(3819, 3971), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7893PolyExtStep::AndEqz(3820, 3972), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7894PolyExtStep::Mul(544, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7895PolyExtStep::Add(4045, 676), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7896PolyExtStep::Add(4032, 7), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7897PolyExtStep::AndEqz(3821, 3976), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7898PolyExtStep::AndEqz(3822, 3977), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7899PolyExtStep::AndEqz(3823, 3978), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7900PolyExtStep::AndEqz(3824, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7901PolyExtStep::Sub(552, 4047), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7902PolyExtStep::AndEqz(3825, 4048), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7903PolyExtStep::AndEqz(3826, 3980), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7904PolyExtStep::AndEqz(3827, 3981), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7905PolyExtStep::AndEqz(3828, 3983), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7906PolyExtStep::AndEqz(3829, 3984), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7907PolyExtStep::Mul(572, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7908PolyExtStep::Add(4049, 570), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7909PolyExtStep::Add(4032, 6), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7910PolyExtStep::AndEqz(3830, 1652), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7911PolyExtStep::AndEqz(3831, 1658), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7912PolyExtStep::AndEqz(3832, 3988), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7913PolyExtStep::AndEqz(3833, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7914PolyExtStep::Sub(574, 4051), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7915PolyExtStep::AndEqz(3834, 4052), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7916PolyExtStep::AndEqz(3835, 1657), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7917PolyExtStep::AndEqz(3836, 3990), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7918PolyExtStep::AndEqz(3837, 3992), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7919PolyExtStep::AndEqz(3838, 3993), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7920PolyExtStep::Mul(739, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7921PolyExtStep::Add(4053, 588), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7922PolyExtStep::Add(4032, 5), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7923PolyExtStep::Sub(740, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7924PolyExtStep::AndEqz(3839, 4056), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7925PolyExtStep::AndEqz(3840, 754), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7926PolyExtStep::Sub(746, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7927PolyExtStep::AndEqz(3841, 4057), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7928PolyExtStep::AndEqz(3842, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7929PolyExtStep::Sub(741, 4055), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7930PolyExtStep::AndEqz(3843, 4058), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7931PolyExtStep::AndEqz(3844, 753), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7932PolyExtStep::AndEqz(3845, 1743), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7933PolyExtStep::Sub(1740, 742), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7934PolyExtStep::Sub(893, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7935PolyExtStep::AndEqz(3846, 4060), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7936PolyExtStep::Sub(896, 4059), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7937PolyExtStep::AndEqz(3847, 4061), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7938PolyExtStep::Mul(760, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7939PolyExtStep::Add(4062, 747), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7940PolyExtStep::Add(4032, 4), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7941PolyExtStep::Sub(766, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7942PolyExtStep::AndEqz(3848, 4065), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7943PolyExtStep::AndEqz(3849, 779), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7944PolyExtStep::Sub(771, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7945PolyExtStep::AndEqz(3850, 4066), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7946PolyExtStep::AndEqz(3851, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7947PolyExtStep::Sub(767, 4064), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7948PolyExtStep::AndEqz(3852, 4067), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7949PolyExtStep::AndEqz(3853, 778), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7950PolyExtStep::AndEqz(3854, 1754), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7951PolyExtStep::Sub(1751, 768), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7952PolyExtStep::Sub(899, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7953PolyExtStep::AndEqz(3855, 4069), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7954PolyExtStep::Sub(902, 4068), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7955PolyExtStep::AndEqz(3856, 4070), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7956PolyExtStep::Mul(756, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7957PolyExtStep::Add(4071, 772), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7958PolyExtStep::Add(4032, 3), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7959PolyExtStep::Sub(757, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7960PolyExtStep::AndEqz(3857, 4074), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7961PolyExtStep::AndEqz(3858, 3020), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7962PolyExtStep::Sub(798, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7963PolyExtStep::AndEqz(3859, 4075), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7964PolyExtStep::AndEqz(3860, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7965PolyExtStep::Sub(762, 4073), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7966PolyExtStep::AndEqz(3861, 4076), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7967PolyExtStep::Sub(732, 800), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7968PolyExtStep::AndEqz(3862, 4077), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7969PolyExtStep::Sub(737, 802), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7970PolyExtStep::AndEqz(3863, 4078), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7971PolyExtStep::Sub(798, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7972PolyExtStep::Sub(4079, 781), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7973PolyExtStep::Sub(905, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7974PolyExtStep::AndEqz(3864, 4081), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7975PolyExtStep::Sub(908, 4080), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7976PolyExtStep::AndEqz(3865, 4082), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7977PolyExtStep::Mul(802, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7978PolyExtStep::Add(4083, 800), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7979PolyExtStep::Add(4032, 2), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
7980PolyExtStep::Sub(804, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7981PolyExtStep::AndEqz(3866, 4086), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7982PolyExtStep::Sub(826, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7983PolyExtStep::AndEqz(3867, 4087), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7984PolyExtStep::Sub(829, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7985PolyExtStep::AndEqz(3868, 4088), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7986PolyExtStep::AndEqz(3869, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7987PolyExtStep::Sub(814, 4085), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7988PolyExtStep::AndEqz(3870, 4089), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7989PolyExtStep::Sub(820, 832), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7990PolyExtStep::AndEqz(3871, 4090), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7991PolyExtStep::Sub(823, 835), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7992PolyExtStep::AndEqz(3872, 4091), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
7993PolyExtStep::Sub(3893, 817), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7994PolyExtStep::Sub(911, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7995PolyExtStep::AndEqz(3873, 4093), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7996PolyExtStep::Sub(914, 4092), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7997PolyExtStep::AndEqz(3874, 4094), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
7998PolyExtStep::Sub(4031, 807), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
7999PolyExtStep::AndEqz(3875, 4095), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8000PolyExtStep::Sub(4032, 1137), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8001PolyExtStep::AndEqz(3876, 4096), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8002PolyExtStep::Sub(4033, 808), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8003PolyExtStep::AndEqz(3877, 4097), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8004PolyExtStep::Sub(4034, 1143), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8005PolyExtStep::AndEqz(3878, 4098), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8006PolyExtStep::Sub(4035, 809), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8007PolyExtStep::AndEqz(3879, 4099), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8008PolyExtStep::Sub(4036, 1148), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8009PolyExtStep::AndEqz(3880, 4100), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8010PolyExtStep::Sub(60, 810), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8011PolyExtStep::AndEqz(3881, 4101), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8012PolyExtStep::AndEqz(3882, 3918), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8013PolyExtStep::Sub(4037, 811), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8014PolyExtStep::AndEqz(3883, 4102), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8015PolyExtStep::Sub(4038, 1160), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8016PolyExtStep::AndEqz(3884, 4103), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8017PolyExtStep::Sub(4039, 1372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8018PolyExtStep::AndEqz(3885, 4104), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8019PolyExtStep::AndEqz(3886, 3922), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8020PolyExtStep::AndEqz(3887, 3923), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8021PolyExtStep::AndEqz(3888, 3924), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8022PolyExtStep::AndEqz(3889, 3925), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8023PolyExtStep::AndEqz(3890, 3926), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8024PolyExtStep::AndEqz(3891, 3927), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8025PolyExtStep::AndEqz(3892, 3928), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8026PolyExtStep::AndEqz(3893, 3929), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8027PolyExtStep::AndEqz(3894, 3930), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8028PolyExtStep::AndEqz(3895, 3931), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8029PolyExtStep::AndEqz(3896, 3932), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8030PolyExtStep::AndEqz(3897, 3933), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8031PolyExtStep::AndEqz(3898, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8032PolyExtStep::AndEqz(3899, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8033PolyExtStep::AndEqz(3900, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8034PolyExtStep::AndEqz(3901, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8035PolyExtStep::Sub(4042, 1428), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8036PolyExtStep::AndEqz(3902, 4105), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8037PolyExtStep::Sub(4046, 1829), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8038PolyExtStep::AndEqz(3903, 4106), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8039PolyExtStep::Sub(4050, 1830), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8040PolyExtStep::AndEqz(3904, 4107), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8041PolyExtStep::Sub(4054, 1429), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8042PolyExtStep::AndEqz(3905, 4108), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8043PolyExtStep::Sub(4063, 1430), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8044PolyExtStep::AndEqz(3906, 4109), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8045PolyExtStep::Sub(4072, 1431), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8046PolyExtStep::AndEqz(3907, 4110), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8047PolyExtStep::Sub(4084, 1432), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8048PolyExtStep::AndEqz(3908, 4111), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8049PolyExtStep::Sub(3895, 1439), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8050PolyExtStep::AndEqz(3909, 4112), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8051PolyExtStep::AndEqz(3910, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8052PolyExtStep::AndEqz(3911, 917), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8053PolyExtStep::AndEqz(3912, 920), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8054PolyExtStep::AndEqz(3913, 923), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8055PolyExtStep::AndEqz(3914, 929), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8056PolyExtStep::AndEqz(3915, 932), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8057PolyExtStep::AndEqz(3916, 935), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8058PolyExtStep::AndEqz(3917, 972), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8059PolyExtStep::AndEqz(3918, 975), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8060PolyExtStep::AndEqz(3919, 978), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8061PolyExtStep::AndEqz(3920, 984), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8062PolyExtStep::AndEqz(3921, 987), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8063PolyExtStep::AndEqz(3922, 990), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8064PolyExtStep::AndEqz(3923, 996), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8065PolyExtStep::AndEqz(3924, 999), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8066PolyExtStep::AndEqz(3925, 1002), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8067PolyExtStep::AndEqz(3926, 1008), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8068PolyExtStep::AndEqz(3927, 1011), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8069PolyExtStep::AndEqz(3928, 1014), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8070PolyExtStep::AndEqz(3929, 1051), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8071PolyExtStep::AndEqz(3930, 1054), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8072PolyExtStep::AndEqz(3931, 1057), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8073PolyExtStep::AndEqz(3932, 1063), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8074PolyExtStep::AndEqz(3933, 1066), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8075PolyExtStep::AndEqz(3934, 1069), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8076PolyExtStep::AndEqz(3935, 1075), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8077PolyExtStep::AndEqz(3936, 1081), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8078PolyExtStep::AndCond(3807, 380, 3937), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8079PolyExtStep::Get(168), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8080PolyExtStep::Get(192), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8081PolyExtStep::Get(198), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8082PolyExtStep::Get(204), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8083PolyExtStep::Get(210), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8084PolyExtStep::Get(216), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8085PolyExtStep::Get(222), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8086PolyExtStep::Get(228), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8087PolyExtStep::Get(234), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8088PolyExtStep::Get(240), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8089PolyExtStep::Get(246), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8090PolyExtStep::Get(252), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8091PolyExtStep::Get(258), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8092PolyExtStep::Get(264), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8093PolyExtStep::Get(270), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8094PolyExtStep::Get(276), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8095PolyExtStep::Get(282), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8096PolyExtStep::Get(288), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8097PolyExtStep::Get(294), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8098PolyExtStep::Get(300), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8099PolyExtStep::Get(306), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8100PolyExtStep::Get(312), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8101PolyExtStep::Get(318), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8102PolyExtStep::Get(324), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8103PolyExtStep::Get(330), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8104PolyExtStep::Get(354), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8105PolyExtStep::Get(348), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8106PolyExtStep::Mul(4138, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8107PolyExtStep::Add(4139, 4140), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8108PolyExtStep::Get(342), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8109PolyExtStep::Mul(4141, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8110PolyExtStep::Add(4142, 4143), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8111PolyExtStep::Get(336), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8112PolyExtStep::Mul(4144, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8113PolyExtStep::Add(4145, 4146), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8114PolyExtStep::Add(4034, 4113), // loc(callsite( builtin Add at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :232:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8115PolyExtStep::AndEqz(0, 4003), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8116PolyExtStep::AndEqz(3939, 4009), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8117PolyExtStep::Sub(1, 2751), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8118PolyExtStep::Mul(2751, 4149), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8119PolyExtStep::AndEqz(3940, 4150), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8120PolyExtStep::Add(2745, 2750), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8121PolyExtStep::Add(4151, 2751), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8122PolyExtStep::Sub(4152, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8123PolyExtStep::AndEqz(3941, 4153), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8124PolyExtStep::Mul(2751, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8125PolyExtStep::Add(2750, 4154), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8126PolyExtStep::Sub(4155, 4148), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8127PolyExtStep::AndEqz(3942, 4156), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
8128PolyExtStep::Add(4037, 1), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8129PolyExtStep::Add(4037, 7), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8130PolyExtStep::Add(4037, 6), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8131PolyExtStep::Add(4037, 5), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8132PolyExtStep::Add(4037, 4), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8133PolyExtStep::Add(4037, 3), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8134PolyExtStep::Add(4037, 2), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8135PolyExtStep::Add(4037, 12), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:65) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8136PolyExtStep::Add(4130, 4131), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8137PolyExtStep::Add(4132, 4133), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8138PolyExtStep::Mul(4131, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8139PolyExtStep::Add(4167, 4166), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8140PolyExtStep::Mul(4133, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8141PolyExtStep::Add(4169, 4165), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8142PolyExtStep::Mul(4166, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8143PolyExtStep::Add(4171, 4170), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8144PolyExtStep::Mul(4165, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8145PolyExtStep::Add(4173, 4168), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8146PolyExtStep::Add(4170, 4174), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8147PolyExtStep::Add(4168, 4172), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8148PolyExtStep::Add(4134, 4135), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8149PolyExtStep::Add(4136, 4137), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8150PolyExtStep::Mul(4135, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8151PolyExtStep::Add(4179, 4178), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8152PolyExtStep::Mul(4137, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8153PolyExtStep::Add(4181, 4177), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8154PolyExtStep::Mul(4178, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8155PolyExtStep::Add(4183, 4182), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8156PolyExtStep::Mul(4177, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8157PolyExtStep::Add(4185, 4180), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8158PolyExtStep::Add(4182, 4186), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8159PolyExtStep::Add(4180, 4184), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8160PolyExtStep::AndEqz(0, 3995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8161PolyExtStep::Sub(1, 2737), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8162PolyExtStep::Mul(2737, 4189), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8163PolyExtStep::AndEqz(3944, 4190), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8164PolyExtStep::AndEqz(3945, 4001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8165PolyExtStep::Add(2736, 2737), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8166PolyExtStep::Add(4191, 2744), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8167PolyExtStep::Sub(4192, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8168PolyExtStep::AndEqz(3946, 4193), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8169PolyExtStep::Mul(2744, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8170PolyExtStep::Add(2737, 4194), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8171PolyExtStep::Sub(4195, 4036), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8172PolyExtStep::AndEqz(3947, 4196), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8173PolyExtStep::Sub(591, 4037), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8174PolyExtStep::AndEqz(3688, 4197), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8175PolyExtStep::AndEqz(3949, 3956), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8176PolyExtStep::AndEqz(3950, 3957), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8177PolyExtStep::AndEqz(3951, 2228), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8178PolyExtStep::AndEqz(3952, 3960), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8179PolyExtStep::AndCond(3948, 2736, 3953), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8180PolyExtStep::AndEqz(3951, 838), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8181PolyExtStep::AndCond(3954, 2737, 3955), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8182PolyExtStep::AndEqz(3949, 2228), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8183PolyExtStep::AndEqz(3957, 3960), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8184PolyExtStep::AndCond(3956, 2744, 3958), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8185PolyExtStep::Get(401), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8186PolyExtStep::Mul(4198, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8187PolyExtStep::Mul(4198, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8188PolyExtStep::Get(377), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8189PolyExtStep::Mul(4201, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8190PolyExtStep::Add(4199, 4200), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8191PolyExtStep::Add(4203, 4202), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8192PolyExtStep::Get(407), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8193PolyExtStep::Mul(4205, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8194PolyExtStep::Mul(4205, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8195PolyExtStep::Get(383), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8196PolyExtStep::Mul(4208, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8197PolyExtStep::Add(4206, 4207), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8198PolyExtStep::Add(4210, 4209), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8199PolyExtStep::Sub(4198, 4201), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8200PolyExtStep::Mul(4212, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8201PolyExtStep::Get(371), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8202PolyExtStep::Sub(3847, 4214), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8203PolyExtStep::Mul(4215, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8204PolyExtStep::Sub(4205, 4208), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8205PolyExtStep::Mul(4217, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8206PolyExtStep::Add(2736, 4216), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8207PolyExtStep::Add(4219, 4218), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8208PolyExtStep::AndEqz(0, 3964), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8209PolyExtStep::AndEqz(3960, 3965), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8210PolyExtStep::AndEqz(3961, 3966), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8211PolyExtStep::AndEqz(3962, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8212PolyExtStep::Sub(646, 4157), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8213PolyExtStep::AndEqz(3963, 4221), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8214PolyExtStep::AndEqz(3964, 3968), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8215PolyExtStep::AndEqz(3965, 3969), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8216PolyExtStep::AndEqz(3966, 3971), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8217PolyExtStep::AndEqz(3967, 3972), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8218PolyExtStep::AndCond(3959, 2736, 3968), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8219PolyExtStep::AndEqz(3966, 844), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8220PolyExtStep::AndCond(3969, 2737, 3970), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8221PolyExtStep::AndEqz(3964, 3971), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8222PolyExtStep::AndEqz(3972, 3972), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8223PolyExtStep::AndCond(3971, 2744, 3973), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8224PolyExtStep::Get(455), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8225PolyExtStep::Mul(4222, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8226PolyExtStep::Mul(4222, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8227PolyExtStep::Get(431), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8228PolyExtStep::Mul(4225, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8229PolyExtStep::Add(4223, 4224), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8230PolyExtStep::Add(4227, 4226), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8231PolyExtStep::Get(461), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8232PolyExtStep::Mul(4229, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8233PolyExtStep::Mul(4229, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8234PolyExtStep::Get(437), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8235PolyExtStep::Mul(4232, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8236PolyExtStep::Add(4230, 4231), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8237PolyExtStep::Add(4234, 4233), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8238PolyExtStep::Sub(4222, 4225), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8239PolyExtStep::Mul(4236, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8240PolyExtStep::Get(425), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8241PolyExtStep::Sub(3050, 4238), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8242PolyExtStep::Mul(4239, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8243PolyExtStep::Sub(4229, 4232), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8244PolyExtStep::Mul(4241, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8245PolyExtStep::Add(2736, 4240), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8246PolyExtStep::Add(4243, 4242), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8247PolyExtStep::AndEqz(0, 3976), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8248PolyExtStep::AndEqz(3975, 3977), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8249PolyExtStep::AndEqz(3976, 3978), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8250PolyExtStep::AndEqz(3977, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8251PolyExtStep::Sub(552, 4158), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8252PolyExtStep::AndEqz(3978, 4245), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8253PolyExtStep::AndEqz(3979, 3980), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8254PolyExtStep::AndEqz(3980, 3981), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8255PolyExtStep::AndEqz(3981, 3983), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8256PolyExtStep::AndEqz(3982, 3984), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8257PolyExtStep::AndCond(3974, 2736, 3983), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8258PolyExtStep::AndEqz(3981, 850), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8259PolyExtStep::AndCond(3984, 2737, 3985), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8260PolyExtStep::AndEqz(3979, 3983), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8261PolyExtStep::AndEqz(3987, 3984), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8262PolyExtStep::AndCond(3986, 2744, 3988), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8263PolyExtStep::Get(509), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8264PolyExtStep::Mul(4246, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8265PolyExtStep::Mul(4246, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8266PolyExtStep::Get(485), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8267PolyExtStep::Mul(4249, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8268PolyExtStep::Add(4247, 4248), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8269PolyExtStep::Add(4251, 4250), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8270PolyExtStep::Get(515), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8271PolyExtStep::Mul(4253, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8272PolyExtStep::Mul(4253, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8273PolyExtStep::Get(491), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8274PolyExtStep::Mul(4256, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8275PolyExtStep::Add(4254, 4255), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8276PolyExtStep::Add(4258, 4257), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8277PolyExtStep::Sub(4246, 4249), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8278PolyExtStep::Mul(4260, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8279PolyExtStep::Get(479), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8280PolyExtStep::Sub(3057, 4262), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8281PolyExtStep::Mul(4263, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8282PolyExtStep::Sub(4253, 4256), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8283PolyExtStep::Mul(4265, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8284PolyExtStep::Add(2736, 4264), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8285PolyExtStep::Add(4267, 4266), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8286PolyExtStep::AndEqz(0, 1652), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8287PolyExtStep::AndEqz(3990, 1658), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8288PolyExtStep::AndEqz(3991, 3988), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8289PolyExtStep::AndEqz(3992, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8290PolyExtStep::Sub(574, 4159), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8291PolyExtStep::AndEqz(3993, 4269), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8292PolyExtStep::AndEqz(3994, 1657), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8293PolyExtStep::AndEqz(3995, 3990), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8294PolyExtStep::AndEqz(3996, 3992), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8295PolyExtStep::AndEqz(3997, 3993), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8296PolyExtStep::AndCond(3989, 2736, 3998), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8297PolyExtStep::AndEqz(3996, 856), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8298PolyExtStep::AndCond(3999, 2737, 4000), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8299PolyExtStep::AndEqz(3994, 3992), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8300PolyExtStep::AndEqz(4002, 3993), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8301PolyExtStep::AndCond(4001, 2744, 4003), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8302PolyExtStep::Get(561), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8303PolyExtStep::Mul(4270, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8304PolyExtStep::Mul(4270, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8305PolyExtStep::Get(539), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8306PolyExtStep::Mul(4273, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8307PolyExtStep::Add(4271, 4272), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8308PolyExtStep::Add(4275, 4274), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8309PolyExtStep::Get(566), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8310PolyExtStep::Mul(4277, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8311PolyExtStep::Mul(4277, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8312PolyExtStep::Get(545), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8313PolyExtStep::Mul(4280, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8314PolyExtStep::Add(4278, 4279), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8315PolyExtStep::Add(4282, 4281), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8316PolyExtStep::Sub(4270, 4273), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8317PolyExtStep::Mul(4284, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8318PolyExtStep::Get(533), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8319PolyExtStep::Get(556), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8320PolyExtStep::Sub(4287, 4286), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8321PolyExtStep::Mul(4288, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8322PolyExtStep::Sub(4277, 4280), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8323PolyExtStep::Mul(4290, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8324PolyExtStep::Add(2736, 4289), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8325PolyExtStep::Add(4292, 4291), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8326PolyExtStep::AndEqz(0, 4056), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8327PolyExtStep::AndEqz(4005, 754), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8328PolyExtStep::AndEqz(4006, 4057), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8329PolyExtStep::AndEqz(4007, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8330PolyExtStep::Sub(741, 4160), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8331PolyExtStep::AndEqz(4008, 4294), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8332PolyExtStep::AndEqz(4009, 753), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8333PolyExtStep::AndEqz(4010, 1743), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8334PolyExtStep::AndEqz(4011, 4060), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8335PolyExtStep::AndEqz(4012, 4061), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8336PolyExtStep::AndCond(4004, 2736, 4013), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8337PolyExtStep::AndEqz(4011, 893), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8338PolyExtStep::AndCond(4014, 2737, 4015), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8339PolyExtStep::AndEqz(4009, 4060), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8340PolyExtStep::AndEqz(4017, 4061), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8341PolyExtStep::AndCond(4016, 2744, 4018), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8342PolyExtStep::Mul(788, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8343PolyExtStep::Mul(788, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8344PolyExtStep::Mul(3756, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8345PolyExtStep::Add(4295, 4296), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8346PolyExtStep::Add(4298, 4297), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8347PolyExtStep::Mul(1760, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8348PolyExtStep::Mul(1760, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8349PolyExtStep::Mul(3757, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8350PolyExtStep::Add(4300, 4301), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8351PolyExtStep::Add(4303, 4302), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8352PolyExtStep::Sub(788, 3756), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8353PolyExtStep::Mul(4305, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8354PolyExtStep::Sub(784, 3755), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8355PolyExtStep::Mul(4307, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8356PolyExtStep::Sub(1760, 3757), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8357PolyExtStep::Mul(4309, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8358PolyExtStep::Add(2736, 4308), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8359PolyExtStep::Add(4311, 4310), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8360PolyExtStep::AndEqz(0, 4065), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8361PolyExtStep::AndEqz(4020, 779), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8362PolyExtStep::AndEqz(4021, 4066), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8363PolyExtStep::AndEqz(4022, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8364PolyExtStep::Sub(767, 4161), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8365PolyExtStep::AndEqz(4023, 4313), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8366PolyExtStep::AndEqz(4024, 778), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8367PolyExtStep::AndEqz(4025, 1754), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8368PolyExtStep::AndEqz(4026, 4069), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8369PolyExtStep::AndEqz(4027, 4070), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8370PolyExtStep::AndCond(4019, 2736, 4028), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8371PolyExtStep::AndEqz(4026, 899), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8372PolyExtStep::AndCond(4029, 2737, 4030), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8373PolyExtStep::AndEqz(4024, 4069), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8374PolyExtStep::AndEqz(4032, 4070), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8375PolyExtStep::AndCond(4031, 2744, 4033), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8376PolyExtStep::Mul(795, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8377PolyExtStep::Mul(795, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8378PolyExtStep::Mul(3782, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8379PolyExtStep::Add(4314, 4315), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8380PolyExtStep::Add(4317, 4316), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8381PolyExtStep::Mul(1768, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8382PolyExtStep::Mul(1768, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8383PolyExtStep::Mul(3823, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8384PolyExtStep::Add(4319, 4320), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8385PolyExtStep::Add(4322, 4321), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8386PolyExtStep::Sub(795, 3782), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8387PolyExtStep::Mul(4324, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8388PolyExtStep::Sub(792, 3781), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8389PolyExtStep::Mul(4326, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8390PolyExtStep::Sub(1768, 3823), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8391PolyExtStep::Mul(4328, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8392PolyExtStep::Add(2736, 4327), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8393PolyExtStep::Add(4330, 4329), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8394PolyExtStep::AndEqz(0, 4074), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8395PolyExtStep::AndEqz(4035, 3020), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8396PolyExtStep::AndEqz(4036, 4075), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8397PolyExtStep::AndEqz(4037, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8398PolyExtStep::Sub(762, 4162), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8399PolyExtStep::AndEqz(4038, 4332), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8400PolyExtStep::AndEqz(4039, 4077), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8401PolyExtStep::AndEqz(4040, 4078), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8402PolyExtStep::AndEqz(4041, 4081), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8403PolyExtStep::AndEqz(4042, 4082), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8404PolyExtStep::AndCond(4034, 2736, 4043), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8405PolyExtStep::AndEqz(4041, 905), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8406PolyExtStep::AndCond(4044, 2737, 4045), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8407PolyExtStep::AndEqz(4039, 4081), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8408PolyExtStep::AndEqz(4047, 4082), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8409PolyExtStep::AndCond(4046, 2744, 4048), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8410PolyExtStep::Get(696), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8411PolyExtStep::Mul(4333, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8412PolyExtStep::Mul(4333, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8413PolyExtStep::Get(676), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8414PolyExtStep::Mul(4336, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8415PolyExtStep::Add(4334, 4335), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8416PolyExtStep::Add(4338, 4337), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8417PolyExtStep::Get(701), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8418PolyExtStep::Mul(4340, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8419PolyExtStep::Mul(4340, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8420PolyExtStep::Mul(3794, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8421PolyExtStep::Add(4341, 4342), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8422PolyExtStep::Add(4344, 4343), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8423PolyExtStep::Sub(4333, 4336), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8424PolyExtStep::Mul(4346, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8425PolyExtStep::Get(691), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))
8426PolyExtStep::Sub(4348, 3793), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8427PolyExtStep::Mul(4349, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8428PolyExtStep::Sub(4340, 3794), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8429PolyExtStep::Mul(4351, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8430PolyExtStep::Add(2736, 4350), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8431PolyExtStep::Add(4353, 4352), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8432PolyExtStep::AndEqz(0, 4086), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8433PolyExtStep::AndEqz(4050, 4087), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8434PolyExtStep::AndEqz(4051, 4088), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8435PolyExtStep::AndEqz(4052, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8436PolyExtStep::Sub(814, 4163), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8437PolyExtStep::AndEqz(4053, 4355), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8438PolyExtStep::AndEqz(4054, 4090), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8439PolyExtStep::AndEqz(4055, 4091), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8440PolyExtStep::AndEqz(4056, 4093), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8441PolyExtStep::AndEqz(4057, 4094), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8442PolyExtStep::AndCond(4049, 2736, 4058), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8443PolyExtStep::AndEqz(4056, 911), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8444PolyExtStep::AndCond(4059, 2737, 4060), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8445PolyExtStep::AndEqz(4054, 4093), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8446PolyExtStep::AndEqz(4062, 4094), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8447PolyExtStep::AndCond(4061, 2744, 4063), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8448PolyExtStep::Mul(1188, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8449PolyExtStep::Mul(1188, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8450PolyExtStep::Mul(1184, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8451PolyExtStep::Add(4356, 4357), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8452PolyExtStep::Add(4359, 4358), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8453PolyExtStep::Mul(1189, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8454PolyExtStep::Mul(1189, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8455PolyExtStep::Mul(1185, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8456PolyExtStep::Add(4361, 4362), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8457PolyExtStep::Add(4364, 4363), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8458PolyExtStep::Sub(1188, 1184), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8459PolyExtStep::Mul(4366, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8460PolyExtStep::Sub(1187, 1183), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8461PolyExtStep::Mul(4368, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8462PolyExtStep::Sub(1189, 1185), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8463PolyExtStep::Mul(4370, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8464PolyExtStep::Add(2736, 4369), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8465PolyExtStep::Add(4372, 4371), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8466PolyExtStep::GetGlobal(0, 52), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8467PolyExtStep::GetGlobal(0, 51), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8468PolyExtStep::Mul(4374, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8469PolyExtStep::Add(4375, 4376), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8470PolyExtStep::GetGlobal(0, 50), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8471PolyExtStep::Mul(4377, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8472PolyExtStep::Add(4378, 4379), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8473PolyExtStep::GetGlobal(0, 49), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8474PolyExtStep::Mul(4380, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8475PolyExtStep::Add(4381, 4382), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8476PolyExtStep::Mul(4383, 67), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8477PolyExtStep::Add(4213, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8478PolyExtStep::Mul(4385, 67), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8479PolyExtStep::Add(4386, 58), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8480PolyExtStep::Mul(4384, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8481PolyExtStep::Add(4220, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8482PolyExtStep::Mul(4389, 4384), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8483PolyExtStep::Add(4387, 4390), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8484PolyExtStep::Mul(4388, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8485PolyExtStep::Add(4237, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8486PolyExtStep::Mul(4393, 4388), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8487PolyExtStep::Add(4391, 4394), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8488PolyExtStep::Mul(4392, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8489PolyExtStep::Add(4244, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8490PolyExtStep::Mul(4397, 4392), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8491PolyExtStep::Add(4395, 4398), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8492PolyExtStep::Mul(4396, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8493PolyExtStep::Add(4261, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8494PolyExtStep::Mul(4401, 4396), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8495PolyExtStep::Add(4399, 4402), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8496PolyExtStep::Mul(4400, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8497PolyExtStep::Add(4268, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8498PolyExtStep::Mul(4405, 4400), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8499PolyExtStep::Add(4403, 4406), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8500PolyExtStep::Mul(4404, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8501PolyExtStep::Add(4285, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8502PolyExtStep::Mul(4409, 4404), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8503PolyExtStep::Add(4407, 4410), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8504PolyExtStep::Mul(4408, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8505PolyExtStep::Add(4293, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8506PolyExtStep::Mul(4413, 4408), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8507PolyExtStep::Add(4411, 4414), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8508PolyExtStep::Mul(4412, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8509PolyExtStep::Add(4306, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8510PolyExtStep::Mul(4417, 4412), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8511PolyExtStep::Add(4415, 4418), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8512PolyExtStep::Mul(4416, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8513PolyExtStep::Add(4312, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8514PolyExtStep::Mul(4421, 4416), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8515PolyExtStep::Add(4419, 4422), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8516PolyExtStep::Mul(4420, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8517PolyExtStep::Add(4325, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8518PolyExtStep::Mul(4425, 4420), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8519PolyExtStep::Add(4423, 4426), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8520PolyExtStep::Mul(4424, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8521PolyExtStep::Add(4331, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8522PolyExtStep::Mul(4429, 4424), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8523PolyExtStep::Add(4427, 4430), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8524PolyExtStep::Mul(4428, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8525PolyExtStep::Add(4347, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8526PolyExtStep::Mul(4433, 4428), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8527PolyExtStep::Add(4431, 4434), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8528PolyExtStep::Mul(4432, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8529PolyExtStep::Add(4354, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8530PolyExtStep::Mul(4437, 4432), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8531PolyExtStep::Add(4435, 4438), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8532PolyExtStep::Mul(4436, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8533PolyExtStep::Add(4367, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8534PolyExtStep::Mul(4441, 4436), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8535PolyExtStep::Add(4439, 4442), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8536PolyExtStep::Add(4373, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8537PolyExtStep::Mul(4444, 4440), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8538PolyExtStep::Add(4443, 4445), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
8539PolyExtStep::Mul(4440, 4383), // loc(callsite( builtin ExtMul at callsite( Pow ( zirgen/circuit/rv32im/v2/dsl/poly.zir :10:4) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :171:29) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8540PolyExtStep::Mul(4147, 4447), // loc(callsite( builtin ExtMul at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :171:17) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8541PolyExtStep::Add(4448, 4446), // loc(callsite( builtin ExtAdd at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :171:10) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8542PolyExtStep::Add(4204, 4211), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8543PolyExtStep::Add(4228, 4235), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8544PolyExtStep::Mul(4211, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8545PolyExtStep::Add(4452, 4451), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8546PolyExtStep::Mul(4235, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8547PolyExtStep::Add(4454, 4450), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8548PolyExtStep::Mul(4451, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8549PolyExtStep::Add(4456, 4455), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8550PolyExtStep::Mul(4450, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8551PolyExtStep::Add(4458, 4453), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8552PolyExtStep::Add(4455, 4459), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8553PolyExtStep::Add(4453, 4457), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8554PolyExtStep::Add(4252, 4259), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8555PolyExtStep::Add(4276, 4283), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8556PolyExtStep::Mul(4259, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8557PolyExtStep::Add(4464, 4463), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8558PolyExtStep::Mul(4283, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8559PolyExtStep::Add(4466, 4462), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8560PolyExtStep::Mul(4463, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8561PolyExtStep::Add(4468, 4467), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8562PolyExtStep::Mul(4462, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8563PolyExtStep::Add(4470, 4465), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8564PolyExtStep::Add(4467, 4471), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8565PolyExtStep::Add(4465, 4469), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8566PolyExtStep::Add(4299, 4304), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8567PolyExtStep::Add(4318, 4323), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8568PolyExtStep::Mul(4304, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8569PolyExtStep::Add(4476, 4475), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8570PolyExtStep::Mul(4323, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8571PolyExtStep::Add(4478, 4474), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8572PolyExtStep::Mul(4475, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8573PolyExtStep::Add(4480, 4479), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8574PolyExtStep::Mul(4474, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8575PolyExtStep::Add(4482, 4477), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8576PolyExtStep::Add(4479, 4483), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8577PolyExtStep::Add(4477, 4481), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8578PolyExtStep::Add(4339, 4345), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8579PolyExtStep::Add(4360, 4365), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8580PolyExtStep::Mul(4345, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8581PolyExtStep::Add(4488, 4487), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8582PolyExtStep::Mul(4365, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8583PolyExtStep::Add(4490, 4486), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8584PolyExtStep::Mul(4487, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8585PolyExtStep::Add(4492, 4491), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8586PolyExtStep::Mul(4486, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8587PolyExtStep::Add(4494, 4489), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8588PolyExtStep::Add(4491, 4495), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8589PolyExtStep::Add(4489, 4493), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8590PolyExtStep::Add(4460, 4472), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8591PolyExtStep::Add(4459, 4471), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8592PolyExtStep::Add(4461, 4473), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8593PolyExtStep::Add(4457, 4469), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8594PolyExtStep::Add(4498, 4484), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8595PolyExtStep::Add(4499, 4483), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8596PolyExtStep::Add(4500, 4485), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8597PolyExtStep::Add(4501, 4481), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8598PolyExtStep::Add(4502, 4496), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8599PolyExtStep::Add(4503, 4495), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8600PolyExtStep::Add(4504, 4497), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8601PolyExtStep::Add(4505, 4493), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8602PolyExtStep::Add(4506, 4175), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8603PolyExtStep::Add(4507, 4174), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8604PolyExtStep::Add(4508, 4176), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8605PolyExtStep::Add(4509, 4172), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8606PolyExtStep::Add(4510, 4187), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8607PolyExtStep::Add(4511, 4186), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8608PolyExtStep::Add(4512, 4188), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8609PolyExtStep::Add(4513, 4184), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8610PolyExtStep::Add(4460, 4514), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8611PolyExtStep::Add(4459, 4515), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8612PolyExtStep::Add(4461, 4516), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8613PolyExtStep::Add(4457, 4517), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8614PolyExtStep::Add(4472, 4514), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8615PolyExtStep::Add(4471, 4515), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8616PolyExtStep::Add(4473, 4516), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8617PolyExtStep::Add(4469, 4517), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8618PolyExtStep::Add(4484, 4514), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8619PolyExtStep::Add(4483, 4515), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8620PolyExtStep::Add(4485, 4516), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8621PolyExtStep::Add(4481, 4517), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8622PolyExtStep::Add(4496, 4514), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8623PolyExtStep::Add(4495, 4515), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8624PolyExtStep::Add(4497, 4516), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8625PolyExtStep::Add(4493, 4517), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8626PolyExtStep::Add(4175, 4514), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8627PolyExtStep::Add(4174, 4515), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8628PolyExtStep::Add(4176, 4516), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8629PolyExtStep::Add(4172, 4517), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8630PolyExtStep::Add(4187, 4514), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8631PolyExtStep::Add(4186, 4515), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8632PolyExtStep::Add(4188, 4516), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8633PolyExtStep::Add(4184, 4517), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8634PolyExtStep::AndEqz(4064, 4095), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8635PolyExtStep::AndEqz(4065, 4096), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8636PolyExtStep::AndEqz(4066, 4097), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8637PolyExtStep::AndEqz(4067, 4098), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8638PolyExtStep::AndEqz(4068, 4099), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8639PolyExtStep::AndEqz(4069, 4100), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8640PolyExtStep::Sub(68, 810), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8641PolyExtStep::AndEqz(4070, 4542), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8642PolyExtStep::AndEqz(4071, 3918), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8643PolyExtStep::Sub(4164, 811), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8644PolyExtStep::AndEqz(4072, 4543), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8645PolyExtStep::AndEqz(4073, 4103), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8646PolyExtStep::AndEqz(4074, 4104), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8647PolyExtStep::Sub(4518, 1373), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8648PolyExtStep::AndEqz(4075, 4544), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8649PolyExtStep::Sub(4519, 1375), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8650PolyExtStep::AndEqz(4076, 4545), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8651PolyExtStep::Sub(4520, 1382), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8652PolyExtStep::AndEqz(4077, 4546), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8653PolyExtStep::Sub(4521, 1383), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8654PolyExtStep::AndEqz(4078, 4547), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8655PolyExtStep::Sub(4522, 1385), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8656PolyExtStep::AndEqz(4079, 4548), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8657PolyExtStep::Sub(4523, 1391), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8658PolyExtStep::AndEqz(4080, 4549), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8659PolyExtStep::Sub(4524, 1392), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8660PolyExtStep::AndEqz(4081, 4550), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8661PolyExtStep::Sub(4525, 1394), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8662PolyExtStep::AndEqz(4082, 4551), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8663PolyExtStep::Sub(4526, 1401), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8664PolyExtStep::AndEqz(4083, 4552), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8665PolyExtStep::Sub(4527, 1402), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8666PolyExtStep::AndEqz(4084, 4553), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8667PolyExtStep::Sub(4528, 1404), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8668PolyExtStep::AndEqz(4085, 4554), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8669PolyExtStep::Sub(4529, 1410), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8670PolyExtStep::AndEqz(4086, 4555), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8671PolyExtStep::Sub(4530, 1411), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8672PolyExtStep::AndEqz(4087, 4556), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8673PolyExtStep::Sub(4531, 1424), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8674PolyExtStep::AndEqz(4088, 4557), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8675PolyExtStep::Sub(4532, 1427), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8676PolyExtStep::AndEqz(4089, 4558), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8677PolyExtStep::Sub(4533, 1426), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8678PolyExtStep::AndEqz(4090, 4559), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8679PolyExtStep::Sub(4534, 1428), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8680PolyExtStep::AndEqz(4091, 4560), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8681PolyExtStep::Sub(4535, 1829), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8682PolyExtStep::AndEqz(4092, 4561), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8683PolyExtStep::Sub(4536, 1830), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8684PolyExtStep::AndEqz(4093, 4562), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8685PolyExtStep::Sub(4537, 1429), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8686PolyExtStep::AndEqz(4094, 4563), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8687PolyExtStep::Sub(4538, 1430), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8688PolyExtStep::AndEqz(4095, 4564), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8689PolyExtStep::Sub(4539, 1431), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8690PolyExtStep::AndEqz(4096, 4565), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8691PolyExtStep::Sub(4540, 1432), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8692PolyExtStep::AndEqz(4097, 4566), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8693PolyExtStep::Sub(4541, 1439), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8694PolyExtStep::AndEqz(4098, 4567), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8695PolyExtStep::Sub(3951, 4449), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8696PolyExtStep::AndEqz(4099, 4568), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8697PolyExtStep::AndCond(3943, 2745, 4100), // loc(callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8698PolyExtStep::Mul(4211, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8699PolyExtStep::Add(4569, 4204), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8700PolyExtStep::Mul(4235, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8701PolyExtStep::Add(4571, 4228), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8702PolyExtStep::Mul(4259, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8703PolyExtStep::Add(4573, 4252), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8704PolyExtStep::Mul(4283, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8705PolyExtStep::Add(4575, 4276), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8706PolyExtStep::Mul(4304, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8707PolyExtStep::Add(4577, 4299), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8708PolyExtStep::Mul(4323, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8709PolyExtStep::Add(4579, 4318), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8710PolyExtStep::Mul(4345, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8711PolyExtStep::Add(4581, 4339), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8712PolyExtStep::Mul(4365, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8713PolyExtStep::Add(4583, 4360), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8714PolyExtStep::AndEqz(4070, 4101), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8715PolyExtStep::Sub(1, 1154), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8716PolyExtStep::AndEqz(4102, 4585), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8717PolyExtStep::AndEqz(4103, 4543), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8718PolyExtStep::AndEqz(4104, 4103), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8719PolyExtStep::AndEqz(4105, 4104), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8720PolyExtStep::Sub(4570, 1373), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8721PolyExtStep::AndEqz(4106, 4586), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8722PolyExtStep::Sub(4572, 1375), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8723PolyExtStep::AndEqz(4107, 4587), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8724PolyExtStep::Sub(4574, 1382), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8725PolyExtStep::AndEqz(4108, 4588), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8726PolyExtStep::Sub(4576, 1383), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8727PolyExtStep::AndEqz(4109, 4589), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8728PolyExtStep::Sub(4578, 1385), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8729PolyExtStep::AndEqz(4110, 4590), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8730PolyExtStep::Sub(4580, 1391), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8731PolyExtStep::AndEqz(4111, 4591), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8732PolyExtStep::Sub(4582, 1392), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8733PolyExtStep::AndEqz(4112, 4592), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8734PolyExtStep::Sub(4584, 1394), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8735PolyExtStep::AndEqz(4113, 4593), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8736PolyExtStep::Sub(4122, 1401), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8737PolyExtStep::AndEqz(4114, 4594), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8738PolyExtStep::Sub(4123, 1402), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8739PolyExtStep::AndEqz(4115, 4595), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8740PolyExtStep::Sub(4124, 1404), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8741PolyExtStep::AndEqz(4116, 4596), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8742PolyExtStep::Sub(4125, 1410), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8743PolyExtStep::AndEqz(4117, 4597), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8744PolyExtStep::Sub(4126, 1411), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8745PolyExtStep::AndEqz(4118, 4598), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8746PolyExtStep::Sub(4127, 1424), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8747PolyExtStep::AndEqz(4119, 4599), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8748PolyExtStep::Sub(4128, 1427), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8749PolyExtStep::AndEqz(4120, 4600), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8750PolyExtStep::Sub(4129, 1426), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8751PolyExtStep::AndEqz(4121, 4601), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8752PolyExtStep::Sub(4130, 1428), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8753PolyExtStep::AndEqz(4122, 4602), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8754PolyExtStep::Sub(4131, 1829), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8755PolyExtStep::AndEqz(4123, 4603), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8756PolyExtStep::Sub(4132, 1830), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8757PolyExtStep::AndEqz(4124, 4604), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8758PolyExtStep::Sub(4133, 1429), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8759PolyExtStep::AndEqz(4125, 4605), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8760PolyExtStep::Sub(4134, 1430), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8761PolyExtStep::AndEqz(4126, 4606), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8762PolyExtStep::Sub(4135, 1431), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8763PolyExtStep::AndEqz(4127, 4607), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8764PolyExtStep::Sub(4136, 1432), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8765PolyExtStep::AndEqz(4128, 4608), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8766PolyExtStep::Sub(4137, 1439), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8767PolyExtStep::AndEqz(4129, 4609), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8768PolyExtStep::AndEqz(4130, 4568), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8769PolyExtStep::AndCond(4101, 2750, 4131), // loc(callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8770PolyExtStep::Add(4114, 4115), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8771PolyExtStep::Add(4116, 4117), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8772PolyExtStep::Mul(4115, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8773PolyExtStep::Add(4612, 4611), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8774PolyExtStep::Mul(4117, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8775PolyExtStep::Add(4614, 4610), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8776PolyExtStep::Mul(4611, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8777PolyExtStep::Add(4616, 4615), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8778PolyExtStep::Mul(4610, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8779PolyExtStep::Add(4618, 4613), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8780PolyExtStep::Add(4615, 4619), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8781PolyExtStep::Add(4613, 4617), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8782PolyExtStep::Add(4118, 4119), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8783PolyExtStep::Add(4120, 4121), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8784PolyExtStep::Mul(4119, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8785PolyExtStep::Add(4624, 4623), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8786PolyExtStep::Mul(4121, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8787PolyExtStep::Add(4626, 4622), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8788PolyExtStep::Mul(4623, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8789PolyExtStep::Add(4628, 4627), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8790PolyExtStep::Mul(4622, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8791PolyExtStep::Add(4630, 4625), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8792PolyExtStep::Add(4627, 4631), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8793PolyExtStep::Add(4625, 4629), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8794PolyExtStep::Add(4620, 4632), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8795PolyExtStep::Add(4619, 4631), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8796PolyExtStep::Add(4621, 4633), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8797PolyExtStep::Add(4617, 4629), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8798PolyExtStep::Add(4570, 4572), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8799PolyExtStep::Add(4574, 4576), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8800PolyExtStep::Mul(4572, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8801PolyExtStep::Add(4640, 4639), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8802PolyExtStep::Mul(4576, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8803PolyExtStep::Add(4642, 4638), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8804PolyExtStep::Mul(4639, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8805PolyExtStep::Add(4644, 4643), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8806PolyExtStep::Mul(4638, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8807PolyExtStep::Add(4646, 4641), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8808PolyExtStep::Add(4643, 4647), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8809PolyExtStep::Add(4641, 4645), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8810PolyExtStep::Add(4578, 4580), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8811PolyExtStep::Add(4582, 4584), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8812PolyExtStep::Mul(4580, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8813PolyExtStep::Add(4652, 4651), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8814PolyExtStep::Mul(4584, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8815PolyExtStep::Add(4654, 4650), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8816PolyExtStep::Mul(4651, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8817PolyExtStep::Add(4656, 4655), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8818PolyExtStep::Mul(4650, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8819PolyExtStep::Add(4658, 4653), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8820PolyExtStep::Add(4655, 4659), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8821PolyExtStep::Add(4653, 4657), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8822PolyExtStep::Add(4634, 4648), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8823PolyExtStep::Add(4635, 4647), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8824PolyExtStep::Add(4636, 4649), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8825PolyExtStep::Add(4637, 4645), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8826PolyExtStep::Add(4662, 4660), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8827PolyExtStep::Add(4663, 4659), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8828PolyExtStep::Add(4664, 4661), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8829PolyExtStep::Add(4665, 4657), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8830PolyExtStep::Add(4666, 4175), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8831PolyExtStep::Add(4667, 4174), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8832PolyExtStep::Add(4668, 4176), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8833PolyExtStep::Add(4669, 4172), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8834PolyExtStep::Add(4670, 4187), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8835PolyExtStep::Add(4671, 4186), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8836PolyExtStep::Add(4672, 4188), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8837PolyExtStep::Add(4673, 4184), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8838PolyExtStep::Add(4620, 4674), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8839PolyExtStep::Add(4619, 4675), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8840PolyExtStep::Add(4621, 4676), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8841PolyExtStep::Add(4617, 4677), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8842PolyExtStep::Add(4632, 4674), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8843PolyExtStep::Add(4631, 4675), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8844PolyExtStep::Add(4633, 4676), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8845PolyExtStep::Add(4629, 4677), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8846PolyExtStep::Add(4648, 4674), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8847PolyExtStep::Add(4647, 4675), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8848PolyExtStep::Add(4649, 4676), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8849PolyExtStep::Add(4645, 4677), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8850PolyExtStep::Add(4660, 4674), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8851PolyExtStep::Add(4659, 4675), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8852PolyExtStep::Add(4661, 4676), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8853PolyExtStep::Add(4657, 4677), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8854PolyExtStep::Add(4175, 4674), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8855PolyExtStep::Add(4174, 4675), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8856PolyExtStep::Add(4176, 4676), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8857PolyExtStep::Add(4172, 4677), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8858PolyExtStep::Add(4187, 4674), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8859PolyExtStep::Add(4186, 4675), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8860PolyExtStep::Add(4188, 4676), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8861PolyExtStep::Add(4184, 4677), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8862PolyExtStep::Sub(4678, 1373), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8863PolyExtStep::AndEqz(4075, 4702), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8864PolyExtStep::Sub(4679, 1375), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8865PolyExtStep::AndEqz(4133, 4703), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8866PolyExtStep::Sub(4680, 1382), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8867PolyExtStep::AndEqz(4134, 4704), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8868PolyExtStep::Sub(4681, 1383), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8869PolyExtStep::AndEqz(4135, 4705), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8870PolyExtStep::Sub(4682, 1385), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8871PolyExtStep::AndEqz(4136, 4706), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8872PolyExtStep::Sub(4683, 1391), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8873PolyExtStep::AndEqz(4137, 4707), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8874PolyExtStep::Sub(4684, 1392), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8875PolyExtStep::AndEqz(4138, 4708), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8876PolyExtStep::Sub(4685, 1394), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8877PolyExtStep::AndEqz(4139, 4709), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8878PolyExtStep::Sub(4686, 1401), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8879PolyExtStep::AndEqz(4140, 4710), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8880PolyExtStep::Sub(4687, 1402), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8881PolyExtStep::AndEqz(4141, 4711), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8882PolyExtStep::Sub(4688, 1404), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8883PolyExtStep::AndEqz(4142, 4712), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8884PolyExtStep::Sub(4689, 1410), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8885PolyExtStep::AndEqz(4143, 4713), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8886PolyExtStep::Sub(4690, 1411), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8887PolyExtStep::AndEqz(4144, 4714), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8888PolyExtStep::Sub(4691, 1424), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8889PolyExtStep::AndEqz(4145, 4715), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8890PolyExtStep::Sub(4692, 1427), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8891PolyExtStep::AndEqz(4146, 4716), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8892PolyExtStep::Sub(4693, 1426), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8893PolyExtStep::AndEqz(4147, 4717), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8894PolyExtStep::Sub(4694, 1428), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8895PolyExtStep::AndEqz(4148, 4718), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8896PolyExtStep::Sub(4695, 1829), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8897PolyExtStep::AndEqz(4149, 4719), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8898PolyExtStep::Sub(4696, 1830), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8899PolyExtStep::AndEqz(4150, 4720), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8900PolyExtStep::Sub(4697, 1429), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8901PolyExtStep::AndEqz(4151, 4721), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8902PolyExtStep::Sub(4698, 1430), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8903PolyExtStep::AndEqz(4152, 4722), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8904PolyExtStep::Sub(4699, 1431), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8905PolyExtStep::AndEqz(4153, 4723), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8906PolyExtStep::Sub(4700, 1432), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8907PolyExtStep::AndEqz(4154, 4724), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8908PolyExtStep::Sub(4701, 1439), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8909PolyExtStep::AndEqz(4155, 4725), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8910PolyExtStep::AndEqz(4156, 4568), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
8911PolyExtStep::AndCond(4132, 2751, 4157), // loc(callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
8912PolyExtStep::AndEqz(4158, 917), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8913PolyExtStep::AndEqz(4159, 920), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8914PolyExtStep::AndEqz(4160, 923), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8915PolyExtStep::AndEqz(4161, 929), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8916PolyExtStep::AndEqz(4162, 932), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8917PolyExtStep::AndEqz(4163, 935), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8918PolyExtStep::AndEqz(4164, 972), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8919PolyExtStep::AndEqz(4165, 975), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8920PolyExtStep::AndEqz(4166, 978), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8921PolyExtStep::AndEqz(4167, 984), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8922PolyExtStep::AndEqz(4168, 987), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8923PolyExtStep::AndEqz(4169, 990), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8924PolyExtStep::AndEqz(4170, 996), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8925PolyExtStep::AndEqz(4171, 999), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8926PolyExtStep::AndEqz(4172, 1002), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8927PolyExtStep::AndEqz(4173, 1008), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8928PolyExtStep::AndEqz(4174, 1011), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8929PolyExtStep::AndEqz(4175, 1014), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8930PolyExtStep::AndEqz(4176, 1051), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8931PolyExtStep::AndEqz(4177, 1054), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8932PolyExtStep::AndEqz(4178, 1057), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8933PolyExtStep::AndEqz(4179, 1063), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8934PolyExtStep::AndEqz(4180, 1066), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8935PolyExtStep::AndEqz(4181, 1069), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8936PolyExtStep::AndEqz(4182, 1075), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8937PolyExtStep::AndEqz(4183, 1081), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8938PolyExtStep::AndCond(3938, 383, 4184), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8939PolyExtStep::AndEqz(1228, 3911), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8940PolyExtStep::AndEqz(4186, 3912), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8941PolyExtStep::Sub(0, 808), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8942PolyExtStep::AndEqz(4187, 4726), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8943PolyExtStep::Sub(0, 1143), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8944PolyExtStep::AndEqz(4188, 4727), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8945PolyExtStep::Sub(0, 809), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8946PolyExtStep::AndEqz(4189, 4728), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8947PolyExtStep::AndEqz(4190, 4027), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8948PolyExtStep::Sub(0, 810), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8949PolyExtStep::AndEqz(4191, 4729), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8950PolyExtStep::AndEqz(4192, 3918), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8951PolyExtStep::AndEqz(4193, 3919), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8952PolyExtStep::AndEqz(4194, 3920), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8953PolyExtStep::Sub(0, 1372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8954PolyExtStep::AndEqz(4195, 4730), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8955PolyExtStep::AndEqz(4196, 3922), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8956PolyExtStep::AndEqz(4197, 3923), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8957PolyExtStep::AndEqz(4198, 3924), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8958PolyExtStep::AndEqz(4199, 3925), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8959PolyExtStep::AndEqz(4200, 3926), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8960PolyExtStep::AndEqz(4201, 3927), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8961PolyExtStep::AndEqz(4202, 3928), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8962PolyExtStep::AndEqz(4203, 3929), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8963PolyExtStep::AndEqz(4204, 3930), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8964PolyExtStep::AndEqz(4205, 3931), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8965PolyExtStep::AndEqz(4206, 3932), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8966PolyExtStep::AndEqz(4207, 3933), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8967PolyExtStep::AndEqz(4208, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8968PolyExtStep::AndEqz(4209, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8969PolyExtStep::AndEqz(4210, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8970PolyExtStep::AndEqz(4211, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8971PolyExtStep::AndEqz(4212, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8972PolyExtStep::AndEqz(4213, 3939), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8973PolyExtStep::AndEqz(4214, 3940), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8974PolyExtStep::AndEqz(4215, 3941), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8975PolyExtStep::AndEqz(4216, 3942), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8976PolyExtStep::AndEqz(4217, 3943), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8977PolyExtStep::AndEqz(4218, 3944), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8978PolyExtStep::AndEqz(4219, 3945), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
8979PolyExtStep::AndEqz(4220, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
8980PolyExtStep::AndEqz(4221, 539), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8981PolyExtStep::AndEqz(4222, 615), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8982PolyExtStep::AndEqz(4223, 639), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8983PolyExtStep::AndEqz(4224, 666), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8984PolyExtStep::AndEqz(4225, 551), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8985PolyExtStep::AndEqz(4226, 564), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8986PolyExtStep::AndEqz(4227, 573), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8987PolyExtStep::AndEqz(4228, 578), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8988PolyExtStep::AndEqz(4229, 740), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8989PolyExtStep::AndEqz(4230, 745), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8990PolyExtStep::AndEqz(4231, 766), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8991PolyExtStep::AndEqz(4232, 770), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8992PolyExtStep::AndEqz(4233, 757), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8993PolyExtStep::AndEqz(4234, 764), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8994PolyExtStep::AndEqz(4235, 804), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8995PolyExtStep::AndEqz(4236, 826), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8996PolyExtStep::AndEqz(4237, 838), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8997PolyExtStep::AndEqz(4238, 844), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8998PolyExtStep::AndEqz(4239, 850), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
8999PolyExtStep::AndEqz(4240, 856), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9000PolyExtStep::AndEqz(4241, 893), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9001PolyExtStep::AndEqz(4242, 899), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9002PolyExtStep::AndEqz(4243, 905), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9003PolyExtStep::AndEqz(4244, 911), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9004PolyExtStep::AndEqz(4245, 917), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9005PolyExtStep::AndEqz(4246, 920), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9006PolyExtStep::AndEqz(4247, 923), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9007PolyExtStep::AndEqz(4248, 929), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9008PolyExtStep::AndEqz(4249, 932), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9009PolyExtStep::AndEqz(4250, 935), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9010PolyExtStep::AndEqz(4251, 972), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9011PolyExtStep::AndEqz(4252, 975), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9012PolyExtStep::AndEqz(4253, 978), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9013PolyExtStep::AndEqz(4254, 984), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9014PolyExtStep::AndEqz(4255, 987), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9015PolyExtStep::AndEqz(4256, 990), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9016PolyExtStep::AndEqz(4257, 996), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9017PolyExtStep::AndEqz(4258, 999), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9018PolyExtStep::AndEqz(4259, 1002), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9019PolyExtStep::AndEqz(4260, 1008), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9020PolyExtStep::AndEqz(4261, 1011), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9021PolyExtStep::AndEqz(4262, 1014), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9022PolyExtStep::AndEqz(4263, 1051), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9023PolyExtStep::AndEqz(4264, 1054), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9024PolyExtStep::AndEqz(4265, 1057), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9025PolyExtStep::AndEqz(4266, 1063), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9026PolyExtStep::AndEqz(4267, 1066), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9027PolyExtStep::AndEqz(4268, 1069), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9028PolyExtStep::AndEqz(4269, 1075), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9029PolyExtStep::AndEqz(4270, 1081), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9030PolyExtStep::AndCond(4185, 386, 4271), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9031PolyExtStep::AndCond(4272, 389, 4271), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9032PolyExtStep::Sub(1, 4035), // loc(callsite( builtin Sub at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9033PolyExtStep::Add(4033, 1), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9034PolyExtStep::Add(4033, 7), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9035PolyExtStep::Add(4033, 6), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9036PolyExtStep::Add(4033, 5), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9037PolyExtStep::Add(4033, 4), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9038PolyExtStep::Add(4033, 3), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9039PolyExtStep::Add(4033, 2), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9040PolyExtStep::Mul(4031, 44), // loc(callsite( builtin Mul at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :269:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9041PolyExtStep::Sub(1, 4031), // loc(callsite( builtin Sub at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :269:62) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9042PolyExtStep::Sub(591, 4033), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9043PolyExtStep::AndEqz(3688, 4741), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9044PolyExtStep::AndEqz(4274, 3956), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9045PolyExtStep::AndEqz(4275, 3957), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9046PolyExtStep::AndEqz(4276, 2228), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9047PolyExtStep::AndEqz(4277, 3960), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9048PolyExtStep::Sub(4042, 4114), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9049PolyExtStep::AndEqz(4278, 4742), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9050PolyExtStep::AndEqz(4279, 3964), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9051PolyExtStep::AndEqz(4280, 3965), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9052PolyExtStep::AndEqz(4281, 3966), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9053PolyExtStep::AndEqz(4282, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9054PolyExtStep::Sub(646, 4732), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9055PolyExtStep::AndEqz(4283, 4743), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9056PolyExtStep::AndEqz(4284, 3968), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9057PolyExtStep::AndEqz(4285, 3969), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9058PolyExtStep::AndEqz(4286, 3971), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9059PolyExtStep::AndEqz(4287, 3972), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9060PolyExtStep::Sub(4046, 4115), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9061PolyExtStep::AndEqz(4288, 4744), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9062PolyExtStep::AndEqz(4289, 3976), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9063PolyExtStep::AndEqz(4290, 3977), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9064PolyExtStep::AndEqz(4291, 3978), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9065PolyExtStep::AndEqz(4292, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9066PolyExtStep::Sub(552, 4733), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9067PolyExtStep::AndEqz(4293, 4745), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9068PolyExtStep::AndEqz(4294, 3980), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9069PolyExtStep::AndEqz(4295, 3981), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9070PolyExtStep::AndEqz(4296, 3983), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9071PolyExtStep::AndEqz(4297, 3984), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9072PolyExtStep::Sub(4050, 4116), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9073PolyExtStep::AndEqz(4298, 4746), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9074PolyExtStep::AndEqz(4299, 1652), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9075PolyExtStep::AndEqz(4300, 1658), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9076PolyExtStep::AndEqz(4301, 3988), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9077PolyExtStep::AndEqz(4302, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9078PolyExtStep::Sub(574, 4734), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9079PolyExtStep::AndEqz(4303, 4747), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9080PolyExtStep::AndEqz(4304, 1657), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9081PolyExtStep::AndEqz(4305, 3990), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9082PolyExtStep::AndEqz(4306, 3992), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9083PolyExtStep::AndEqz(4307, 3993), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9084PolyExtStep::Sub(4054, 4117), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9085PolyExtStep::AndEqz(4308, 4748), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9086PolyExtStep::AndEqz(4309, 4056), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9087PolyExtStep::AndEqz(4310, 754), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9088PolyExtStep::AndEqz(4311, 4057), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9089PolyExtStep::AndEqz(4312, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9090PolyExtStep::Sub(741, 4735), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9091PolyExtStep::AndEqz(4313, 4749), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9092PolyExtStep::AndEqz(4314, 753), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9093PolyExtStep::AndEqz(4315, 1743), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9094PolyExtStep::AndEqz(4316, 4060), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9095PolyExtStep::AndEqz(4317, 4061), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9096PolyExtStep::Sub(4063, 4118), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9097PolyExtStep::AndEqz(4318, 4750), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9098PolyExtStep::AndEqz(4319, 4065), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9099PolyExtStep::AndEqz(4320, 779), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9100PolyExtStep::AndEqz(4321, 4066), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9101PolyExtStep::AndEqz(4322, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9102PolyExtStep::Sub(767, 4736), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9103PolyExtStep::AndEqz(4323, 4751), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9104PolyExtStep::AndEqz(4324, 778), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9105PolyExtStep::AndEqz(4325, 1754), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9106PolyExtStep::AndEqz(4326, 4069), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9107PolyExtStep::AndEqz(4327, 4070), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9108PolyExtStep::Sub(4072, 4119), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9109PolyExtStep::AndEqz(4328, 4752), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9110PolyExtStep::AndEqz(4329, 4074), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9111PolyExtStep::AndEqz(4330, 3020), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9112PolyExtStep::AndEqz(4331, 4075), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9113PolyExtStep::AndEqz(4332, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9114PolyExtStep::Sub(762, 4737), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9115PolyExtStep::AndEqz(4333, 4753), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9116PolyExtStep::AndEqz(4334, 4077), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9117PolyExtStep::AndEqz(4335, 4078), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9118PolyExtStep::AndEqz(4336, 4081), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9119PolyExtStep::AndEqz(4337, 4082), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9120PolyExtStep::Sub(4084, 4120), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9121PolyExtStep::AndEqz(4338, 4754), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9122PolyExtStep::AndEqz(4339, 4086), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9123PolyExtStep::AndEqz(4340, 4087), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9124PolyExtStep::AndEqz(4341, 4088), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9125PolyExtStep::AndEqz(4342, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9126PolyExtStep::Sub(814, 4738), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9127PolyExtStep::AndEqz(4343, 4755), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9128PolyExtStep::AndEqz(4344, 4090), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9129PolyExtStep::AndEqz(4345, 4091), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9130PolyExtStep::AndEqz(4346, 4093), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9131PolyExtStep::AndEqz(4347, 4094), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9132PolyExtStep::Sub(3895, 4121), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9133PolyExtStep::AndEqz(4348, 4756), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9134PolyExtStep::AndEqz(4349, 3995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9135PolyExtStep::Mul(4036, 2737), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9136PolyExtStep::Sub(4757, 3994), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9137PolyExtStep::AndEqz(4350, 4758), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9138PolyExtStep::Mul(2736, 4036), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9139PolyExtStep::AndEqz(4351, 4759), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9140PolyExtStep::AndEqz(4352, 3999), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9141PolyExtStep::Mul(2736, 13), // loc(callsite( builtin Mul at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :268:16) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9142PolyExtStep::Mul(3994, 57), // loc(callsite( builtin Mul at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :268:56) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9143PolyExtStep::Add(4760, 4761), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :268:39) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9144PolyExtStep::Mul(4740, 4762), // loc(callsite( builtin Mul at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :269:80) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9145PolyExtStep::Add(4739, 4763), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :269:57) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9146PolyExtStep::AndEqz(4353, 4095), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9147PolyExtStep::AndEqz(4354, 4096), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9148PolyExtStep::AndEqz(4355, 4097), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9149PolyExtStep::AndEqz(4356, 4098), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9150PolyExtStep::AndEqz(4357, 4099), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9151PolyExtStep::AndEqz(4358, 4100), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9152PolyExtStep::Sub(4764, 810), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9153PolyExtStep::AndEqz(4359, 4765), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9154PolyExtStep::AndEqz(4360, 3918), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9155PolyExtStep::AndEqz(4361, 3919), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9156PolyExtStep::AndEqz(4362, 3920), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9157PolyExtStep::AndEqz(4363, 4104), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9158PolyExtStep::Sub(4114, 1373), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9159PolyExtStep::AndEqz(4364, 4766), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9160PolyExtStep::Sub(4115, 1375), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9161PolyExtStep::AndEqz(4365, 4767), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9162PolyExtStep::Sub(4116, 1382), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9163PolyExtStep::AndEqz(4366, 4768), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9164PolyExtStep::Sub(4117, 1383), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9165PolyExtStep::AndEqz(4367, 4769), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9166PolyExtStep::Sub(4118, 1385), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9167PolyExtStep::AndEqz(4368, 4770), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9168PolyExtStep::Sub(4119, 1391), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9169PolyExtStep::AndEqz(4369, 4771), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9170PolyExtStep::Sub(4120, 1392), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9171PolyExtStep::AndEqz(4370, 4772), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9172PolyExtStep::Sub(4121, 1394), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9173PolyExtStep::AndEqz(4371, 4773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9174PolyExtStep::AndEqz(4372, 4594), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9175PolyExtStep::AndEqz(4373, 4595), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9176PolyExtStep::AndEqz(4374, 4596), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9177PolyExtStep::AndEqz(4375, 4597), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9178PolyExtStep::AndEqz(4376, 4598), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9179PolyExtStep::AndEqz(4377, 4599), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9180PolyExtStep::AndEqz(4378, 4600), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9181PolyExtStep::AndEqz(4379, 4601), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9182PolyExtStep::AndEqz(4380, 4602), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9183PolyExtStep::AndEqz(4381, 4603), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9184PolyExtStep::AndEqz(4382, 4604), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9185PolyExtStep::AndEqz(4383, 4605), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9186PolyExtStep::AndEqz(4384, 4606), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9187PolyExtStep::AndEqz(4385, 4607), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9188PolyExtStep::AndEqz(4386, 4608), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9189PolyExtStep::AndEqz(4387, 4609), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9190PolyExtStep::AndEqz(4388, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9191PolyExtStep::AndEqz(4389, 917), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9192PolyExtStep::AndEqz(4390, 920), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9193PolyExtStep::AndEqz(4391, 923), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9194PolyExtStep::AndEqz(4392, 929), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9195PolyExtStep::AndEqz(4393, 932), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9196PolyExtStep::AndEqz(4394, 935), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9197PolyExtStep::AndEqz(4395, 972), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9198PolyExtStep::AndEqz(4396, 975), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9199PolyExtStep::AndEqz(4397, 978), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9200PolyExtStep::AndEqz(4398, 984), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9201PolyExtStep::AndEqz(4399, 987), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9202PolyExtStep::AndEqz(4400, 990), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9203PolyExtStep::AndEqz(4401, 996), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9204PolyExtStep::AndEqz(4402, 999), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9205PolyExtStep::AndEqz(4403, 1002), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9206PolyExtStep::AndEqz(4404, 1008), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9207PolyExtStep::AndEqz(4405, 1011), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9208PolyExtStep::AndEqz(4406, 1014), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9209PolyExtStep::AndEqz(4407, 1051), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9210PolyExtStep::AndEqz(4408, 1054), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9211PolyExtStep::AndEqz(4409, 1057), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9212PolyExtStep::AndEqz(4410, 1063), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9213PolyExtStep::AndEqz(4411, 1066), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9214PolyExtStep::AndEqz(4412, 1069), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9215PolyExtStep::AndCond(0, 4035, 4413), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9216PolyExtStep::Sub(917, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9217PolyExtStep::AndEqz(0, 4774), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9218PolyExtStep::Sub(4114, 629), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9219PolyExtStep::Mul(4775, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9220PolyExtStep::Sub(920, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9221PolyExtStep::AndEqz(4415, 4777), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9222PolyExtStep::Sub(632, 4776), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9223PolyExtStep::AndEqz(4416, 4778), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9224PolyExtStep::AndEqz(4417, 3995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9225PolyExtStep::Sub(70, 632), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9226PolyExtStep::AndEqz(0, 629), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9227PolyExtStep::Sub(923, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9228PolyExtStep::AndEqz(4419, 4780), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9229PolyExtStep::Sub(926, 4779), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9230PolyExtStep::AndEqz(4420, 4781), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9231PolyExtStep::AndCond(4418, 2736, 4421), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9232PolyExtStep::Sub(69, 632), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9233PolyExtStep::AndEqz(0, 4780), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9234PolyExtStep::Sub(926, 4782), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9235PolyExtStep::AndEqz(4423, 4783), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9236PolyExtStep::AndCond(4422, 3994, 4424), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9237PolyExtStep::AndEqz(4425, 3953), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9238PolyExtStep::AndEqz(4426, 2294), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9239PolyExtStep::Sub(622, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9240PolyExtStep::AndEqz(4427, 4784), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9241PolyExtStep::AndEqz(4428, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9242PolyExtStep::AndEqz(4429, 4741), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9243PolyExtStep::AndEqz(4430, 2228), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9244PolyExtStep::AndEqz(4431, 3960), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9245PolyExtStep::AndEqz(4432, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9246PolyExtStep::AndEqz(4433, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9247PolyExtStep::Sub(929, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9248PolyExtStep::AndEqz(4434, 4785), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9249PolyExtStep::Sub(4115, 676), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9250PolyExtStep::Mul(4786, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9251PolyExtStep::AndEqz(4435, 2047), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9252PolyExtStep::Sub(544, 4787), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9253PolyExtStep::AndEqz(4436, 4788), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9254PolyExtStep::AndEqz(4437, 4190), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9255PolyExtStep::Sub(70, 544), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9256PolyExtStep::AndEqz(0, 676), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9257PolyExtStep::AndEqz(4439, 2050), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9258PolyExtStep::Sub(938, 4789), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9259PolyExtStep::AndEqz(4440, 4790), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9260PolyExtStep::AndCond(4438, 2737, 4441), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9261PolyExtStep::Sub(69, 544), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9262PolyExtStep::AndEqz(0, 2050), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9263PolyExtStep::Sub(938, 4791), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9264PolyExtStep::AndEqz(4443, 4792), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9265PolyExtStep::AndCond(4442, 4189, 4444), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9266PolyExtStep::AndEqz(4445, 3964), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9267PolyExtStep::AndEqz(4446, 3965), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9268PolyExtStep::Sub(673, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9269PolyExtStep::AndEqz(4447, 4793), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9270PolyExtStep::AndEqz(4448, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9271PolyExtStep::AndEqz(4449, 4743), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9272PolyExtStep::AndEqz(4450, 3971), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9273PolyExtStep::AndEqz(4451, 3972), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9274PolyExtStep::AndEqz(4452, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9275PolyExtStep::AndEqz(4453, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9276PolyExtStep::Sub(972, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9277PolyExtStep::AndEqz(4454, 4794), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9278PolyExtStep::Sub(4116, 570), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9279PolyExtStep::Mul(4795, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9280PolyExtStep::AndEqz(4455, 2052), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9281PolyExtStep::Sub(572, 4796), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9282PolyExtStep::AndEqz(4456, 4797), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9283PolyExtStep::AndEqz(4457, 4001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9284PolyExtStep::Sub(70, 572), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9285PolyExtStep::AndEqz(0, 570), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9286PolyExtStep::Sub(978, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9287PolyExtStep::AndEqz(4459, 4799), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9288PolyExtStep::Sub(981, 4798), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9289PolyExtStep::AndEqz(4460, 4800), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9290PolyExtStep::AndCond(4458, 2744, 4461), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9291PolyExtStep::Sub(69, 572), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9292PolyExtStep::AndEqz(0, 4799), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9293PolyExtStep::Sub(981, 4801), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9294PolyExtStep::AndEqz(4463, 4802), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9295PolyExtStep::AndCond(4462, 4000, 4464), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9296PolyExtStep::AndEqz(4465, 3976), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9297PolyExtStep::AndEqz(4466, 3977), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9298PolyExtStep::Sub(571, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9299PolyExtStep::AndEqz(4467, 4803), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9300PolyExtStep::AndEqz(4468, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9301PolyExtStep::AndEqz(4469, 4745), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9302PolyExtStep::AndEqz(4470, 3983), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9303PolyExtStep::AndEqz(4471, 3984), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9304PolyExtStep::AndEqz(4472, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9305PolyExtStep::AndEqz(4473, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9306PolyExtStep::Sub(984, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9307PolyExtStep::AndEqz(4474, 4804), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9308PolyExtStep::Sub(4117, 588), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9309PolyExtStep::Mul(4805, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9310PolyExtStep::Sub(987, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9311PolyExtStep::AndEqz(4475, 4807), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9312PolyExtStep::Sub(739, 4806), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9313PolyExtStep::AndEqz(4476, 4808), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9314PolyExtStep::AndEqz(4477, 4003), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9315PolyExtStep::Sub(70, 739), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9316PolyExtStep::AndEqz(0, 588), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9317PolyExtStep::AndEqz(4479, 2061), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9318PolyExtStep::Sub(993, 4809), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9319PolyExtStep::AndEqz(4480, 4810), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9320PolyExtStep::AndCond(4478, 2745, 4481), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9321PolyExtStep::Sub(69, 739), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9322PolyExtStep::AndEqz(0, 2061), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9323PolyExtStep::Sub(993, 4811), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9324PolyExtStep::AndEqz(4483, 4812), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9325PolyExtStep::AndCond(4482, 4002, 4484), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9326PolyExtStep::AndEqz(4485, 1652), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9327PolyExtStep::AndEqz(4486, 1658), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9328PolyExtStep::Sub(587, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9329PolyExtStep::AndEqz(4487, 4813), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9330PolyExtStep::AndEqz(4488, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9331PolyExtStep::AndEqz(4489, 4747), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9332PolyExtStep::AndEqz(4490, 3992), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9333PolyExtStep::AndEqz(4491, 3993), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9334PolyExtStep::AndEqz(4492, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9335PolyExtStep::AndEqz(4493, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9336PolyExtStep::Sub(996, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9337PolyExtStep::AndEqz(4494, 4814), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9338PolyExtStep::Sub(4118, 747), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9339PolyExtStep::Mul(4815, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9340PolyExtStep::Sub(999, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9341PolyExtStep::AndEqz(4495, 4817), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9342PolyExtStep::Sub(760, 4816), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9343PolyExtStep::AndEqz(4496, 4818), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9344PolyExtStep::AndEqz(4497, 4009), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9345PolyExtStep::Sub(70, 760), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9346PolyExtStep::AndEqz(0, 747), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9347PolyExtStep::Sub(1002, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9348PolyExtStep::AndEqz(4499, 4820), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9349PolyExtStep::Sub(1005, 4819), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9350PolyExtStep::AndEqz(4500, 4821), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9351PolyExtStep::AndCond(4498, 2750, 4501), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9352PolyExtStep::Sub(69, 760), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9353PolyExtStep::AndEqz(0, 4820), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9354PolyExtStep::Sub(1005, 4822), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9355PolyExtStep::AndEqz(4503, 4823), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9356PolyExtStep::AndCond(4502, 4008, 4504), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9357PolyExtStep::AndEqz(4505, 4056), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9358PolyExtStep::AndEqz(4506, 754), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9359PolyExtStep::Sub(746, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9360PolyExtStep::AndEqz(4507, 4824), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9361PolyExtStep::AndEqz(4508, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9362PolyExtStep::AndEqz(4509, 4749), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9363PolyExtStep::AndEqz(4510, 4060), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9364PolyExtStep::AndEqz(4511, 4061), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9365PolyExtStep::AndEqz(4512, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9366PolyExtStep::AndEqz(4513, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9367PolyExtStep::Sub(1008, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9368PolyExtStep::AndEqz(4514, 4825), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9369PolyExtStep::Sub(4119, 772), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9370PolyExtStep::Mul(4826, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9371PolyExtStep::Sub(1011, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9372PolyExtStep::AndEqz(4515, 4828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9373PolyExtStep::Sub(756, 4827), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9374PolyExtStep::AndEqz(4516, 4829), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9375PolyExtStep::AndEqz(4517, 4150), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9376PolyExtStep::Sub(70, 756), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9377PolyExtStep::AndEqz(0, 772), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9378PolyExtStep::Sub(1014, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9379PolyExtStep::AndEqz(4519, 4831), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9380PolyExtStep::Sub(1017, 4830), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9381PolyExtStep::AndEqz(4520, 4832), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9382PolyExtStep::AndCond(4518, 2751, 4521), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9383PolyExtStep::Sub(69, 756), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9384PolyExtStep::AndEqz(0, 4831), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9385PolyExtStep::Sub(1017, 4833), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9386PolyExtStep::AndEqz(4523, 4834), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9387PolyExtStep::AndCond(4522, 4149, 4524), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9388PolyExtStep::AndEqz(4525, 4065), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9389PolyExtStep::AndEqz(4526, 779), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9390PolyExtStep::Sub(771, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9391PolyExtStep::AndEqz(4527, 4835), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9392PolyExtStep::AndEqz(4528, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9393PolyExtStep::AndEqz(4529, 4751), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9394PolyExtStep::AndEqz(4530, 4069), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9395PolyExtStep::AndEqz(4531, 4070), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9396PolyExtStep::AndEqz(4532, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9397PolyExtStep::AndEqz(4533, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9398PolyExtStep::Sub(1051, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9399PolyExtStep::AndEqz(4534, 4836), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9400PolyExtStep::Sub(4120, 800), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9401PolyExtStep::Mul(4837, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9402PolyExtStep::Sub(1054, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9403PolyExtStep::AndEqz(4535, 4839), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9404PolyExtStep::Sub(802, 4838), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9405PolyExtStep::AndEqz(4536, 4840), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9406PolyExtStep::AndEqz(4537, 2755), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9407PolyExtStep::Sub(70, 802), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9408PolyExtStep::AndEqz(0, 800), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9409PolyExtStep::Sub(1057, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9410PolyExtStep::AndEqz(4539, 4842), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9411PolyExtStep::Sub(1060, 4841), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9412PolyExtStep::AndEqz(4540, 4843), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9413PolyExtStep::AndCond(4538, 2753, 4541), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9414PolyExtStep::Sub(69, 802), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9415PolyExtStep::AndEqz(0, 4842), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9416PolyExtStep::Sub(1060, 4844), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9417PolyExtStep::AndEqz(4543, 4845), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9418PolyExtStep::AndCond(4542, 2754, 4544), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9419PolyExtStep::AndEqz(4545, 4074), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9420PolyExtStep::AndEqz(4546, 3020), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9421PolyExtStep::Sub(798, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9422PolyExtStep::AndEqz(4547, 4846), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9423PolyExtStep::AndEqz(4548, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9424PolyExtStep::AndEqz(4549, 4753), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9425PolyExtStep::AndEqz(4550, 4081), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9426PolyExtStep::AndEqz(4551, 4082), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9427PolyExtStep::AndEqz(4552, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9428PolyExtStep::AndEqz(4553, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9429PolyExtStep::Sub(1063, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9430PolyExtStep::AndEqz(4554, 4847), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9431PolyExtStep::Sub(4121, 832), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9432PolyExtStep::Mul(4848, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9433PolyExtStep::Sub(1066, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9434PolyExtStep::AndEqz(4555, 4850), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9435PolyExtStep::Sub(835, 4849), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9436PolyExtStep::AndEqz(4556, 4851), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9437PolyExtStep::Sub(1, 2760), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9438PolyExtStep::Mul(2760, 4852), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
9439PolyExtStep::AndEqz(4557, 4853), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9440PolyExtStep::Sub(70, 835), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9441PolyExtStep::AndEqz(0, 832), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9442PolyExtStep::Sub(1069, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9443PolyExtStep::AndEqz(4559, 4855), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9444PolyExtStep::Sub(1072, 4854), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9445PolyExtStep::AndEqz(4560, 4856), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9446PolyExtStep::AndCond(4558, 2760, 4561), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9447PolyExtStep::Sub(69, 835), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9448PolyExtStep::AndEqz(0, 4855), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9449PolyExtStep::Sub(1072, 4857), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9450PolyExtStep::AndEqz(4563, 4858), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9451PolyExtStep::AndCond(4562, 4852, 4564), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9452PolyExtStep::AndEqz(4565, 4086), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9453PolyExtStep::AndEqz(4566, 4087), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9454PolyExtStep::Sub(829, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9455PolyExtStep::AndEqz(4567, 4859), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9456PolyExtStep::AndEqz(4568, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9457PolyExtStep::AndEqz(4569, 4755), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9458PolyExtStep::AndEqz(4570, 4093), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9459PolyExtStep::AndEqz(4571, 4094), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9460PolyExtStep::AndEqz(4572, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9461PolyExtStep::AndEqz(4573, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9462PolyExtStep::Sub(1, 2761), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9463PolyExtStep::Mul(2761, 4860), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9464PolyExtStep::AndEqz(4574, 4861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9465PolyExtStep::Mul(4036, 2763), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9466PolyExtStep::Sub(4862, 4860), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9467PolyExtStep::AndEqz(4575, 4863), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9468PolyExtStep::Mul(2761, 4036), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9469PolyExtStep::AndEqz(4576, 4864), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9470PolyExtStep::Mul(2761, 2763), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9471PolyExtStep::AndEqz(4577, 4865), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9472PolyExtStep::Mul(2761, 13), // loc(callsite( builtin Mul at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :308:16) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9473PolyExtStep::Mul(4860, 57), // loc(callsite( builtin Mul at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :308:56) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9474PolyExtStep::Add(4866, 4867), // loc(callsite( builtin Add at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :308:39) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9475PolyExtStep::Mul(4740, 4868), // loc(callsite( builtin Mul at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :311:25) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9476PolyExtStep::Add(4739, 4869), // loc(callsite( builtin Add at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :310:46) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9477PolyExtStep::AndEqz(4578, 4095), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9478PolyExtStep::AndEqz(4579, 4096), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9479PolyExtStep::AndEqz(4580, 4097), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9480PolyExtStep::AndEqz(4581, 4098), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9481PolyExtStep::AndEqz(4582, 4099), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9482PolyExtStep::AndEqz(4583, 4100), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9483PolyExtStep::Sub(4870, 810), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9484PolyExtStep::AndEqz(4584, 4871), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9485PolyExtStep::AndEqz(4585, 3918), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9486PolyExtStep::AndEqz(4586, 3919), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9487PolyExtStep::AndEqz(4587, 3920), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9488PolyExtStep::AndEqz(4588, 4104), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9489PolyExtStep::AndEqz(4589, 4766), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9490PolyExtStep::AndEqz(4590, 4767), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9491PolyExtStep::AndEqz(4591, 4768), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9492PolyExtStep::AndEqz(4592, 4769), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9493PolyExtStep::AndEqz(4593, 4770), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9494PolyExtStep::AndEqz(4594, 4771), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9495PolyExtStep::AndEqz(4595, 4772), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9496PolyExtStep::AndEqz(4596, 4773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9497PolyExtStep::AndEqz(4597, 4594), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9498PolyExtStep::AndEqz(4598, 4595), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9499PolyExtStep::AndEqz(4599, 4596), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9500PolyExtStep::AndEqz(4600, 4597), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9501PolyExtStep::AndEqz(4601, 4598), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9502PolyExtStep::AndEqz(4602, 4599), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9503PolyExtStep::AndEqz(4603, 4600), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9504PolyExtStep::AndEqz(4604, 4601), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9505PolyExtStep::AndEqz(4605, 4602), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9506PolyExtStep::AndEqz(4606, 4603), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9507PolyExtStep::AndEqz(4607, 4604), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9508PolyExtStep::AndEqz(4608, 4605), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9509PolyExtStep::AndEqz(4609, 4606), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9510PolyExtStep::AndEqz(4610, 4607), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9511PolyExtStep::AndEqz(4611, 4608), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9512PolyExtStep::AndEqz(4612, 4609), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9513PolyExtStep::AndEqz(4613, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9514PolyExtStep::AndCond(4414, 4731, 4614), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9515PolyExtStep::AndEqz(4615, 1075), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9516PolyExtStep::AndEqz(4616, 1081), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9517PolyExtStep::AndCond(4273, 392, 4617), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9518PolyExtStep::Sub(54, 4033), // loc(callsite( builtin Sub at callsite( NodeAddrToIdx ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :337:40) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :442:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9519PolyExtStep::Mul(4872, 71), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( NodeAddrToIdx ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :337:57) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :442:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9520PolyExtStep::AndEqz(0, 4001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9521PolyExtStep::AndEqz(4619, 4003), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9522PolyExtStep::AndEqz(4620, 4009), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9523PolyExtStep::AndEqz(4621, 4150), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9524PolyExtStep::AndEqz(4622, 2755), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9525PolyExtStep::AndEqz(4623, 4853), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9526PolyExtStep::Add(2744, 2745), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9527PolyExtStep::Add(4874, 2750), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9528PolyExtStep::Add(4875, 2751), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9529PolyExtStep::Add(4876, 2753), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9530PolyExtStep::Add(4877, 2760), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9531PolyExtStep::Sub(4878, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9532PolyExtStep::AndEqz(4624, 4879), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9533PolyExtStep::Mul(2750, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9534PolyExtStep::Mul(2751, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9535PolyExtStep::Mul(2753, 5), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9536PolyExtStep::Mul(2760, 4), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9537PolyExtStep::Add(2745, 4880), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9538PolyExtStep::Add(4884, 4881), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9539PolyExtStep::Add(4885, 4882), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9540PolyExtStep::Add(4886, 4883), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9541PolyExtStep::Sub(4887, 2737), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9542PolyExtStep::AndEqz(4625, 4888), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9543PolyExtStep::AndEqz(4626, 4774), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :341:25) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9544PolyExtStep::Sub(2736, 629), // loc(callsite( builtin Sub at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:11) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9545PolyExtStep::Mul(4889, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:20) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9546PolyExtStep::Sub(1075, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :26:22) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9547PolyExtStep::AndEqz(4627, 4891), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :26:22) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9548PolyExtStep::Sub(1078, 4890), // loc(callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :27:8) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9549PolyExtStep::AndEqz(4628, 4892), // loc(callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :27:8) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9550PolyExtStep::Sub(1, 4875), // loc(callsite( builtin Sub at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :449:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9551PolyExtStep::Add(4873, 1), // loc(callsite( builtin Add at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :451:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9552PolyExtStep::Sub(2736, 4894), // loc(callsite( builtin Sub at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :451:12) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9553PolyExtStep::AndEqz(0, 4777), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :341:25) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :451:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9554PolyExtStep::Sub(4895, 632), // loc(callsite( builtin Sub at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:11) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :451:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9555PolyExtStep::Mul(4896, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:20) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :451:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9556PolyExtStep::Sub(1081, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :26:22) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :451:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9557PolyExtStep::AndEqz(4630, 4898), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :26:22) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :451:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9558PolyExtStep::Sub(1084, 4897), // loc(callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :27:8) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :451:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9559PolyExtStep::AndEqz(4631, 4899), // loc(callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :27:8) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :451:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9560PolyExtStep::AndCond(4629, 4875, 4632), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :449:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9561PolyExtStep::Sub(4873, 1), // loc(callsite( builtin Sub at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :454:12) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9562PolyExtStep::Sub(4900, 2736), // loc(callsite( builtin Sub at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :454:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9563PolyExtStep::Sub(4901, 632), // loc(callsite( builtin Sub at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:11) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :454:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9564PolyExtStep::Mul(4902, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:20) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :454:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9565PolyExtStep::Sub(1084, 4903), // loc(callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :27:8) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :454:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9566PolyExtStep::AndEqz(4631, 4904), // loc(callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :27:8) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :454:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9567PolyExtStep::AndCond(4633, 4893, 4634), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :449:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9568PolyExtStep::Sub(2737, 374), // loc(callsite( builtin Sub at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9569PolyExtStep::AndEqz(4635, 4861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:10) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9570PolyExtStep::Sub(4905, 2761), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:10) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9571PolyExtStep::AndEqz(4636, 4906), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:10) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9572PolyExtStep::Mul(2736, 12), // loc(callsite( builtin Mul at callsite( NodeIdxToAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :338:51) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :349:34) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9573PolyExtStep::Sub(54, 4907), // loc(callsite( builtin Sub at callsite( NodeIdxToAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :338:38) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :349:34) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9574PolyExtStep::Mul(2736, 7), // loc(callsite( builtin Mul at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :358:34) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9575PolyExtStep::Add(4909, 1), // loc(callsite( builtin Add at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :358:38) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9576PolyExtStep::Mul(4910, 12), // loc(callsite( builtin Mul at callsite( NodeIdxToAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :338:51) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :358:33) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9577PolyExtStep::Sub(54, 4911), // loc(callsite( builtin Sub at callsite( NodeIdxToAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :338:38) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :358:33) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9578PolyExtStep::Sub(4908, 808), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9579PolyExtStep::AndEqz(3637, 4913), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9580PolyExtStep::AndEqz(4638, 3914), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9581PolyExtStep::AndEqz(4639, 3915), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9582PolyExtStep::AndEqz(4640, 3916), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9583PolyExtStep::AndEqz(4641, 4101), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9584PolyExtStep::AndEqz(4642, 3918), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9585PolyExtStep::Sub(4912, 811), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9586PolyExtStep::AndEqz(4643, 4914), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9587PolyExtStep::Sub(1, 1160), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9588PolyExtStep::AndEqz(4644, 4915), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9589PolyExtStep::AndEqz(4645, 4730), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9590PolyExtStep::AndEqz(4646, 3922), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9591PolyExtStep::AndEqz(4647, 3923), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9592PolyExtStep::AndEqz(4648, 3924), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9593PolyExtStep::AndEqz(4649, 3925), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9594PolyExtStep::AndEqz(4650, 3926), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9595PolyExtStep::AndEqz(4651, 3927), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9596PolyExtStep::AndEqz(4652, 3928), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9597PolyExtStep::AndEqz(4653, 3929), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9598PolyExtStep::AndEqz(4654, 3930), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9599PolyExtStep::AndEqz(4655, 3931), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9600PolyExtStep::AndEqz(4656, 3932), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9601PolyExtStep::AndEqz(4657, 3933), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9602PolyExtStep::AndEqz(4658, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9603PolyExtStep::AndEqz(4659, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9604PolyExtStep::AndEqz(4660, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9605PolyExtStep::AndEqz(4661, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9606PolyExtStep::AndEqz(4662, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9607PolyExtStep::AndEqz(4663, 3939), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9608PolyExtStep::AndEqz(4664, 3940), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9609PolyExtStep::AndEqz(4665, 3941), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9610PolyExtStep::AndEqz(4666, 3942), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9611PolyExtStep::AndEqz(4667, 3943), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9612PolyExtStep::AndEqz(4668, 3944), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9613PolyExtStep::AndEqz(4669, 3945), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9614PolyExtStep::AndEqz(4670, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9615PolyExtStep::AndCond(4637, 2744, 4671), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9616PolyExtStep::Sub(2736, 72), // loc(callsite( builtin Sub at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :367:13) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9617PolyExtStep::Mul(4916, 20), // loc(callsite( builtin Mul at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :380:20) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9618PolyExtStep::AndEqz(4638, 4727), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9619PolyExtStep::AndEqz(4673, 3915), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9620PolyExtStep::AndEqz(4674, 3916), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9621PolyExtStep::AndEqz(4675, 4101), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9622PolyExtStep::AndEqz(4676, 3918), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9623PolyExtStep::Sub(4917, 811), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9624PolyExtStep::AndEqz(4677, 4918), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9625PolyExtStep::Sub(24, 1160), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9626PolyExtStep::AndEqz(4678, 4919), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9627PolyExtStep::Sub(1, 1372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9628PolyExtStep::AndEqz(4679, 4920), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9629PolyExtStep::AndEqz(4680, 3922), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9630PolyExtStep::AndEqz(4681, 3923), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9631PolyExtStep::AndEqz(4682, 3924), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9632PolyExtStep::AndEqz(4683, 3925), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9633PolyExtStep::AndEqz(4684, 3926), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9634PolyExtStep::AndEqz(4685, 3927), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9635PolyExtStep::AndEqz(4686, 3928), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9636PolyExtStep::AndEqz(4687, 3929), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9637PolyExtStep::AndEqz(4688, 3930), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9638PolyExtStep::AndEqz(4689, 3931), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9639PolyExtStep::AndEqz(4690, 3932), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9640PolyExtStep::AndEqz(4691, 3933), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9641PolyExtStep::AndEqz(4692, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9642PolyExtStep::AndEqz(4693, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9643PolyExtStep::AndEqz(4694, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9644PolyExtStep::AndEqz(4695, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9645PolyExtStep::AndEqz(4696, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9646PolyExtStep::AndEqz(4697, 3939), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9647PolyExtStep::AndEqz(4698, 3940), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9648PolyExtStep::AndEqz(4699, 3941), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9649PolyExtStep::AndEqz(4700, 3942), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9650PolyExtStep::AndEqz(4701, 3943), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9651PolyExtStep::AndEqz(4702, 3944), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9652PolyExtStep::AndEqz(4703, 3945), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9653PolyExtStep::AndEqz(4704, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9654PolyExtStep::AndCond(4672, 2745, 4705), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9655PolyExtStep::Sub(55, 808), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9656PolyExtStep::AndEqz(3637, 4921), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9657PolyExtStep::AndEqz(4707, 4727), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9658PolyExtStep::AndEqz(4708, 4728), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9659PolyExtStep::AndEqz(4709, 4027), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9660PolyExtStep::Sub(1, 810), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9661PolyExtStep::AndEqz(4710, 4922), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9662PolyExtStep::AndEqz(4711, 3918), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9663PolyExtStep::AndEqz(4712, 3919), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9664PolyExtStep::AndEqz(4713, 3920), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9665PolyExtStep::Sub(7, 1372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9666PolyExtStep::AndEqz(4714, 4923), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9667PolyExtStep::AndEqz(4715, 3922), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9668PolyExtStep::AndEqz(4716, 3923), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9669PolyExtStep::AndEqz(4717, 3924), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9670PolyExtStep::AndEqz(4718, 3925), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9671PolyExtStep::AndEqz(4719, 3926), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9672PolyExtStep::AndEqz(4720, 3927), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9673PolyExtStep::AndEqz(4721, 3928), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9674PolyExtStep::AndEqz(4722, 3929), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9675PolyExtStep::AndEqz(4723, 3930), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9676PolyExtStep::AndEqz(4724, 3931), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9677PolyExtStep::AndEqz(4725, 3932), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9678PolyExtStep::AndEqz(4726, 3933), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9679PolyExtStep::AndEqz(4727, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9680PolyExtStep::AndEqz(4728, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9681PolyExtStep::AndEqz(4729, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9682PolyExtStep::AndEqz(4730, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9683PolyExtStep::AndEqz(4731, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9684PolyExtStep::AndEqz(4732, 3939), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9685PolyExtStep::AndEqz(4733, 3940), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9686PolyExtStep::AndEqz(4734, 3941), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9687PolyExtStep::AndEqz(4735, 3942), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9688PolyExtStep::AndEqz(4736, 3943), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9689PolyExtStep::AndEqz(4737, 3944), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9690PolyExtStep::AndEqz(4738, 3945), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9691PolyExtStep::AndEqz(4739, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9692PolyExtStep::AndCond(4706, 2750, 4740), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9693PolyExtStep::AndEqz(4673, 4728), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9694PolyExtStep::Sub(7, 1148), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9695PolyExtStep::AndEqz(4742, 4924), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9696PolyExtStep::AndEqz(4743, 4101), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9697PolyExtStep::AndEqz(4744, 3918), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9698PolyExtStep::AndEqz(4745, 4918), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9699PolyExtStep::AndEqz(4746, 4919), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9700PolyExtStep::Sub(6, 1372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9701PolyExtStep::AndEqz(4747, 4925), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9702PolyExtStep::AndEqz(4748, 3922), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9703PolyExtStep::AndEqz(4749, 3923), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9704PolyExtStep::AndEqz(4750, 3924), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9705PolyExtStep::AndEqz(4751, 3925), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9706PolyExtStep::AndEqz(4752, 3926), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9707PolyExtStep::AndEqz(4753, 3927), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9708PolyExtStep::AndEqz(4754, 3928), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9709PolyExtStep::AndEqz(4755, 3929), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9710PolyExtStep::AndEqz(4756, 3930), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9711PolyExtStep::AndEqz(4757, 3931), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9712PolyExtStep::AndEqz(4758, 3932), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9713PolyExtStep::AndEqz(4759, 3933), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9714PolyExtStep::AndEqz(4760, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9715PolyExtStep::AndEqz(4761, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9716PolyExtStep::AndEqz(4762, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9717PolyExtStep::AndEqz(4763, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9718PolyExtStep::AndEqz(4764, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9719PolyExtStep::AndEqz(4765, 3939), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9720PolyExtStep::AndEqz(4766, 3940), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9721PolyExtStep::AndEqz(4767, 3941), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9722PolyExtStep::AndEqz(4768, 3942), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9723PolyExtStep::AndEqz(4769, 3943), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9724PolyExtStep::AndEqz(4770, 3944), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9725PolyExtStep::AndEqz(4771, 3945), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9726PolyExtStep::AndEqz(4772, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9727PolyExtStep::AndCond(4741, 2751, 4773), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9728PolyExtStep::AndEqz(4639, 4728), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9729PolyExtStep::AndEqz(4775, 4924), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9730PolyExtStep::AndEqz(4776, 4101), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9731PolyExtStep::AndEqz(4777, 3918), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9732PolyExtStep::AndEqz(4778, 4914), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9733PolyExtStep::AndEqz(4779, 4915), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9734PolyExtStep::Sub(5, 1372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9735PolyExtStep::AndEqz(4780, 4926), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9736PolyExtStep::AndEqz(4781, 3922), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9737PolyExtStep::AndEqz(4782, 3923), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9738PolyExtStep::AndEqz(4783, 3924), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9739PolyExtStep::AndEqz(4784, 3925), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9740PolyExtStep::AndEqz(4785, 3926), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9741PolyExtStep::AndEqz(4786, 3927), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9742PolyExtStep::AndEqz(4787, 3928), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9743PolyExtStep::AndEqz(4788, 3929), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9744PolyExtStep::AndEqz(4789, 3930), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9745PolyExtStep::AndEqz(4790, 3931), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9746PolyExtStep::AndEqz(4791, 3932), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9747PolyExtStep::AndEqz(4792, 3933), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9748PolyExtStep::AndEqz(4793, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9749PolyExtStep::AndEqz(4794, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9750PolyExtStep::AndEqz(4795, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9751PolyExtStep::AndEqz(4796, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9752PolyExtStep::AndEqz(4797, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9753PolyExtStep::AndEqz(4798, 3939), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9754PolyExtStep::AndEqz(4799, 3940), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9755PolyExtStep::AndEqz(4800, 3941), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9756PolyExtStep::AndEqz(4801, 3942), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9757PolyExtStep::AndEqz(4802, 3943), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9758PolyExtStep::AndEqz(4803, 3944), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9759PolyExtStep::AndEqz(4804, 3945), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9760PolyExtStep::AndEqz(4805, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9761PolyExtStep::AndCond(4774, 2753, 4806), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9762PolyExtStep::Sub(54, 808), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9763PolyExtStep::AndEqz(3637, 4927), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9764PolyExtStep::AndEqz(4808, 4727), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9765PolyExtStep::AndEqz(4809, 4728), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9766PolyExtStep::AndEqz(4810, 4027), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9767PolyExtStep::Sub(4, 810), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9768PolyExtStep::AndEqz(4811, 4928), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9769PolyExtStep::AndEqz(4812, 3918), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9770PolyExtStep::AndEqz(4813, 3919), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9771PolyExtStep::AndEqz(4814, 3920), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9772PolyExtStep::Sub(4, 1372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9773PolyExtStep::AndEqz(4815, 4929), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9774PolyExtStep::AndEqz(4816, 3922), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9775PolyExtStep::AndEqz(4817, 3923), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9776PolyExtStep::AndEqz(4818, 3924), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9777PolyExtStep::AndEqz(4819, 3925), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9778PolyExtStep::AndEqz(4820, 3926), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9779PolyExtStep::AndEqz(4821, 3927), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9780PolyExtStep::AndEqz(4822, 3928), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9781PolyExtStep::AndEqz(4823, 3929), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9782PolyExtStep::AndEqz(4824, 3930), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9783PolyExtStep::AndEqz(4825, 3931), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9784PolyExtStep::AndEqz(4826, 3932), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9785PolyExtStep::AndEqz(4827, 3933), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9786PolyExtStep::AndEqz(4828, 3934), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9787PolyExtStep::AndEqz(4829, 3935), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9788PolyExtStep::AndEqz(4830, 3936), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9789PolyExtStep::AndEqz(4831, 3937), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9790PolyExtStep::AndEqz(4832, 3938), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9791PolyExtStep::AndEqz(4833, 3939), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9792PolyExtStep::AndEqz(4834, 3940), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9793PolyExtStep::AndEqz(4835, 3941), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9794PolyExtStep::AndEqz(4836, 3942), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9795PolyExtStep::AndEqz(4837, 3943), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9796PolyExtStep::AndEqz(4838, 3944), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9797PolyExtStep::AndEqz(4839, 3945), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9798PolyExtStep::AndEqz(4840, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
9799PolyExtStep::AndCond(4807, 2760, 4841), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
9800PolyExtStep::AndEqz(4842, 539), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9801PolyExtStep::AndEqz(4843, 615), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9802PolyExtStep::AndEqz(4844, 639), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9803PolyExtStep::AndEqz(4845, 666), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9804PolyExtStep::AndEqz(4846, 551), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9805PolyExtStep::AndEqz(4847, 564), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9806PolyExtStep::AndEqz(4848, 573), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9807PolyExtStep::AndEqz(4849, 578), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9808PolyExtStep::AndEqz(4850, 740), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9809PolyExtStep::AndEqz(4851, 745), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9810PolyExtStep::AndEqz(4852, 766), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9811PolyExtStep::AndEqz(4853, 770), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9812PolyExtStep::AndEqz(4854, 757), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9813PolyExtStep::AndEqz(4855, 764), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9814PolyExtStep::AndEqz(4856, 804), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9815PolyExtStep::AndEqz(4857, 826), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9816PolyExtStep::AndEqz(4858, 838), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9817PolyExtStep::AndEqz(4859, 844), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9818PolyExtStep::AndEqz(4860, 850), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9819PolyExtStep::AndEqz(4861, 856), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9820PolyExtStep::AndEqz(4862, 893), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9821PolyExtStep::AndEqz(4863, 899), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9822PolyExtStep::AndEqz(4864, 905), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9823PolyExtStep::AndEqz(4865, 911), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9824PolyExtStep::AndEqz(4866, 923), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9825PolyExtStep::AndEqz(4867, 929), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9826PolyExtStep::AndEqz(4868, 932), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9827PolyExtStep::AndEqz(4869, 935), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9828PolyExtStep::AndEqz(4870, 972), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9829PolyExtStep::AndEqz(4871, 975), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9830PolyExtStep::AndEqz(4872, 978), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9831PolyExtStep::AndEqz(4873, 984), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9832PolyExtStep::AndEqz(4874, 987), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9833PolyExtStep::AndEqz(4875, 990), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9834PolyExtStep::AndEqz(4876, 996), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9835PolyExtStep::AndEqz(4877, 999), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9836PolyExtStep::AndEqz(4878, 1002), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9837PolyExtStep::AndEqz(4879, 1008), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9838PolyExtStep::AndEqz(4880, 1011), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9839PolyExtStep::AndEqz(4881, 1014), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9840PolyExtStep::AndEqz(4882, 1051), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9841PolyExtStep::AndEqz(4883, 1054), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9842PolyExtStep::AndEqz(4884, 1057), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9843PolyExtStep::AndEqz(4885, 1063), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9844PolyExtStep::AndEqz(4886, 1066), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9845PolyExtStep::AndEqz(4887, 1069), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9846PolyExtStep::AndCond(4618, 395, 4888), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
9847PolyExtStep::Sub(4130, 629), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9848PolyExtStep::Mul(4930, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9849PolyExtStep::Sub(632, 4931), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9850PolyExtStep::AndEqz(4416, 4932), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9851PolyExtStep::AndEqz(4890, 3995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9852PolyExtStep::AndCond(4891, 2736, 4421), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9853PolyExtStep::AndCond(4892, 3994, 4424), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9854PolyExtStep::AndEqz(4893, 3953), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9855PolyExtStep::AndEqz(4894, 2294), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9856PolyExtStep::AndEqz(4895, 4784), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9857PolyExtStep::AndEqz(4896, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9858PolyExtStep::AndEqz(4897, 4040), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9859PolyExtStep::AndEqz(4898, 2228), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9860PolyExtStep::AndEqz(4899, 3960), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9861PolyExtStep::AndEqz(4900, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9862PolyExtStep::AndEqz(4901, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9863PolyExtStep::AndEqz(4902, 4785), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9864PolyExtStep::Sub(4131, 676), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9865PolyExtStep::Mul(4933, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9866PolyExtStep::AndEqz(4903, 2047), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9867PolyExtStep::Sub(544, 4934), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9868PolyExtStep::AndEqz(4904, 4935), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9869PolyExtStep::AndEqz(4905, 4190), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9870PolyExtStep::AndCond(4906, 2737, 4441), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9871PolyExtStep::AndCond(4907, 4189, 4444), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9872PolyExtStep::AndEqz(4908, 3964), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9873PolyExtStep::AndEqz(4909, 3965), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9874PolyExtStep::AndEqz(4910, 4793), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9875PolyExtStep::AndEqz(4911, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9876PolyExtStep::AndEqz(4912, 4044), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9877PolyExtStep::AndEqz(4913, 3971), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9878PolyExtStep::AndEqz(4914, 3972), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9879PolyExtStep::AndEqz(4915, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9880PolyExtStep::AndEqz(4916, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9881PolyExtStep::AndEqz(4917, 4794), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9882PolyExtStep::Sub(4132, 570), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9883PolyExtStep::Mul(4936, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9884PolyExtStep::AndEqz(4918, 2052), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9885PolyExtStep::Sub(572, 4937), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9886PolyExtStep::AndEqz(4919, 4938), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9887PolyExtStep::AndEqz(4920, 4001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9888PolyExtStep::AndCond(4921, 2744, 4461), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9889PolyExtStep::AndCond(4922, 4000, 4464), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9890PolyExtStep::AndEqz(4923, 3976), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9891PolyExtStep::AndEqz(4924, 3977), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9892PolyExtStep::AndEqz(4925, 4803), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9893PolyExtStep::AndEqz(4926, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9894PolyExtStep::AndEqz(4927, 4048), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9895PolyExtStep::AndEqz(4928, 3983), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9896PolyExtStep::AndEqz(4929, 3984), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9897PolyExtStep::AndEqz(4930, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9898PolyExtStep::AndEqz(4931, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9899PolyExtStep::AndEqz(4932, 4804), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9900PolyExtStep::Sub(4133, 588), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9901PolyExtStep::Mul(4939, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9902PolyExtStep::AndEqz(4933, 4807), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9903PolyExtStep::Sub(739, 4940), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9904PolyExtStep::AndEqz(4934, 4941), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9905PolyExtStep::AndEqz(4935, 4003), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9906PolyExtStep::AndCond(4936, 2745, 4481), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9907PolyExtStep::AndCond(4937, 4002, 4484), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9908PolyExtStep::AndEqz(4938, 1652), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9909PolyExtStep::AndEqz(4939, 1658), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9910PolyExtStep::AndEqz(4940, 4813), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9911PolyExtStep::AndEqz(4941, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9912PolyExtStep::AndEqz(4942, 4052), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9913PolyExtStep::AndEqz(4943, 3992), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9914PolyExtStep::AndEqz(4944, 3993), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9915PolyExtStep::AndEqz(4945, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9916PolyExtStep::AndEqz(4946, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9917PolyExtStep::AndEqz(4947, 4814), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9918PolyExtStep::Sub(4134, 747), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9919PolyExtStep::Mul(4942, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9920PolyExtStep::AndEqz(4948, 4817), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9921PolyExtStep::Sub(760, 4943), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9922PolyExtStep::AndEqz(4949, 4944), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9923PolyExtStep::AndEqz(4950, 4009), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9924PolyExtStep::AndCond(4951, 2750, 4501), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9925PolyExtStep::AndCond(4952, 4008, 4504), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9926PolyExtStep::AndEqz(4953, 4056), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9927PolyExtStep::AndEqz(4954, 754), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9928PolyExtStep::AndEqz(4955, 4824), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9929PolyExtStep::AndEqz(4956, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9930PolyExtStep::AndEqz(4957, 4058), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9931PolyExtStep::AndEqz(4958, 4060), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9932PolyExtStep::AndEqz(4959, 4061), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9933PolyExtStep::AndEqz(4960, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9934PolyExtStep::AndEqz(4961, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9935PolyExtStep::AndEqz(4962, 4825), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9936PolyExtStep::Sub(4135, 772), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9937PolyExtStep::Mul(4945, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9938PolyExtStep::AndEqz(4963, 4828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9939PolyExtStep::Sub(756, 4946), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9940PolyExtStep::AndEqz(4964, 4947), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9941PolyExtStep::AndEqz(4965, 4150), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9942PolyExtStep::AndCond(4966, 2751, 4521), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9943PolyExtStep::AndCond(4967, 4149, 4524), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9944PolyExtStep::AndEqz(4968, 4065), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9945PolyExtStep::AndEqz(4969, 779), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9946PolyExtStep::AndEqz(4970, 4835), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9947PolyExtStep::AndEqz(4971, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9948PolyExtStep::AndEqz(4972, 4067), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9949PolyExtStep::AndEqz(4973, 4069), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9950PolyExtStep::AndEqz(4974, 4070), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9951PolyExtStep::AndEqz(4975, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9952PolyExtStep::AndEqz(4976, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9953PolyExtStep::AndEqz(4977, 4836), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9954PolyExtStep::Sub(4136, 800), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9955PolyExtStep::Mul(4948, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9956PolyExtStep::AndEqz(4978, 4839), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9957PolyExtStep::Sub(802, 4949), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9958PolyExtStep::AndEqz(4979, 4950), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9959PolyExtStep::AndEqz(4980, 2755), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9960PolyExtStep::AndCond(4981, 2753, 4541), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9961PolyExtStep::AndCond(4982, 2754, 4544), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9962PolyExtStep::AndEqz(4983, 4074), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9963PolyExtStep::AndEqz(4984, 3020), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9964PolyExtStep::AndEqz(4985, 4846), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9965PolyExtStep::AndEqz(4986, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9966PolyExtStep::AndEqz(4987, 4076), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9967PolyExtStep::AndEqz(4988, 4081), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9968PolyExtStep::AndEqz(4989, 4082), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9969PolyExtStep::AndEqz(4990, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9970PolyExtStep::AndEqz(4991, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9971PolyExtStep::AndEqz(4992, 4847), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9972PolyExtStep::Sub(4137, 832), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9973PolyExtStep::Mul(4951, 49), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9974PolyExtStep::AndEqz(4993, 4850), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9975PolyExtStep::Sub(835, 4952), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9976PolyExtStep::AndEqz(4994, 4953), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9977PolyExtStep::AndEqz(4995, 4853), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9978PolyExtStep::AndCond(4996, 2760, 4561), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9979PolyExtStep::AndCond(4997, 4852, 4564), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9980PolyExtStep::AndEqz(4998, 4086), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9981PolyExtStep::AndEqz(4999, 4087), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9982PolyExtStep::AndEqz(5000, 4859), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9983PolyExtStep::AndEqz(5001, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9984PolyExtStep::AndEqz(5002, 4089), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9985PolyExtStep::AndEqz(5003, 4093), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9986PolyExtStep::AndEqz(5004, 4094), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
9987PolyExtStep::AndEqz(5005, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9988PolyExtStep::AndEqz(5006, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
9989PolyExtStep::AndEqz(5007, 4095), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9990PolyExtStep::AndEqz(5008, 4096), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9991PolyExtStep::AndEqz(5009, 4097), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9992PolyExtStep::AndEqz(5010, 4098), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9993PolyExtStep::AndEqz(5011, 4099), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9994PolyExtStep::AndEqz(5012, 4100), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9995PolyExtStep::Sub(13, 810), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9996PolyExtStep::AndEqz(5013, 4954), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9997PolyExtStep::AndEqz(5014, 3918), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9998PolyExtStep::AndEqz(5015, 3919), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
9999PolyExtStep::AndEqz(5016, 3920), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10000PolyExtStep::AndEqz(5017, 4104), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10001PolyExtStep::AndEqz(5018, 4766), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10002PolyExtStep::AndEqz(5019, 4767), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10003PolyExtStep::AndEqz(5020, 4768), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10004PolyExtStep::AndEqz(5021, 4769), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10005PolyExtStep::AndEqz(5022, 4770), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10006PolyExtStep::AndEqz(5023, 4771), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10007PolyExtStep::AndEqz(5024, 4772), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10008PolyExtStep::AndEqz(5025, 4773), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10009PolyExtStep::AndEqz(5026, 4594), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10010PolyExtStep::AndEqz(5027, 4595), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10011PolyExtStep::AndEqz(5028, 4596), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10012PolyExtStep::AndEqz(5029, 4597), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10013PolyExtStep::AndEqz(5030, 4598), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10014PolyExtStep::AndEqz(5031, 4599), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10015PolyExtStep::AndEqz(5032, 4600), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10016PolyExtStep::AndEqz(5033, 4601), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10017PolyExtStep::AndEqz(5034, 4602), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10018PolyExtStep::AndEqz(5035, 4603), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10019PolyExtStep::AndEqz(5036, 4604), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10020PolyExtStep::AndEqz(5037, 4605), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10021PolyExtStep::AndEqz(5038, 4606), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10022PolyExtStep::AndEqz(5039, 4607), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10023PolyExtStep::AndEqz(5040, 4608), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10024PolyExtStep::AndEqz(5041, 4609), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10025PolyExtStep::AndEqz(5042, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10026PolyExtStep::AndEqz(5043, 1075), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
10027PolyExtStep::AndEqz(5044, 1081), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
10028PolyExtStep::AndCond(4889, 398, 5045), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
10029PolyExtStep::AndCond(3628, 449, 5046), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
10030PolyExtStep::Add(376, 68), // loc(callsite( builtin Add at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :487:45) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
10031PolyExtStep::Sub(371, 4955), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :487:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
10032PolyExtStep::Sub(591, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :486:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
10033PolyExtStep::AndEqz(0, 4957), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :486:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
10034PolyExtStep::AndEqz(5048, 3320), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :486:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
10035PolyExtStep::AndEqz(5049, 4956), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :487:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
10036PolyExtStep::Sub(4113, 6), // loc(callsite( builtin Sub at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10037PolyExtStep::AndEqz(0, 610), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10038PolyExtStep::Mul(4958, 615), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10039PolyExtStep::Sub(4959, 609), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10040PolyExtStep::AndEqz(5051, 4960), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10041PolyExtStep::Mul(608, 4958), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10042PolyExtStep::AndEqz(5052, 4961), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10043PolyExtStep::Mul(608, 615), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10044PolyExtStep::AndEqz(5053, 4962), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10045PolyExtStep::Sub(4113, 2), // loc(callsite( builtin Sub at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10046PolyExtStep::AndEqz(5054, 624), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10047PolyExtStep::Mul(4963, 629), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10048PolyExtStep::Sub(4964, 623), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10049PolyExtStep::AndEqz(5055, 4965), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10050PolyExtStep::Mul(622, 4963), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10051PolyExtStep::AndEqz(5056, 4966), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10052PolyExtStep::Mul(622, 629), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10053PolyExtStep::AndEqz(5057, 4967), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10054PolyExtStep::Sub(4038, 1), // loc(callsite( builtin Sub at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :243:21) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10055PolyExtStep::AndEqz(5058, 634), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10056PolyExtStep::Mul(4968, 639), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10057PolyExtStep::Sub(4969, 633), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10058PolyExtStep::AndEqz(5059, 4970), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10059PolyExtStep::Mul(632, 4968), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10060PolyExtStep::AndEqz(5060, 4971), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10061PolyExtStep::Mul(632, 639), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10062PolyExtStep::AndEqz(5061, 4972), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10063PolyExtStep::Sub(4038, 622), // loc(callsite( builtin Sub at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :245:21) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10064PolyExtStep::Mul(608, 73), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :247:6) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10065PolyExtStep::Sub(609, 622), // loc(callsite( builtin Sub at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :248:11) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10066PolyExtStep::Mul(4975, 68), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :248:30) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10067PolyExtStep::Add(4974, 4976), // loc(callsite( builtin Add at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :247:40) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10068PolyExtStep::Mul(622, 633), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :249:6) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10069PolyExtStep::Mul(4978, 60), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :249:31) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10070PolyExtStep::Add(4977, 4979), // loc(callsite( builtin Add at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :248:56) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10071PolyExtStep::Mul(622, 632), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :250:6) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10072PolyExtStep::Mul(4981, 61), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :250:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10073PolyExtStep::Add(4980, 4982), // loc(callsite( builtin Add at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :249:55) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10074PolyExtStep::Add(4113, 1), // loc(callsite( builtin Add at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :251:54) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10075PolyExtStep::Mul(4975, 4984), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :251:44) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
10076PolyExtStep::Sub(1, 737), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10077PolyExtStep::Mul(737, 4986), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10078PolyExtStep::AndEqz(5062, 4987), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10079PolyExtStep::AndEqz(5063, 1735), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10080PolyExtStep::Sub(1, 798), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10081PolyExtStep::Mul(798, 4988), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10082PolyExtStep::AndEqz(5064, 4989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10083PolyExtStep::AndEqz(5065, 3022), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10084PolyExtStep::Sub(1, 802), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10085PolyExtStep::Mul(802, 4990), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10086PolyExtStep::AndEqz(5066, 4991), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10087PolyExtStep::AndEqz(5067, 3872), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10088PolyExtStep::AndEqz(5068, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10089PolyExtStep::AndEqz(5069, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10090PolyExtStep::Add(737, 764), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10091PolyExtStep::Add(4992, 798), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10092PolyExtStep::Add(4993, 800), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10093PolyExtStep::Add(4994, 802), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10094PolyExtStep::Add(4995, 804), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10095PolyExtStep::Add(4996, 814), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10096PolyExtStep::Add(4997, 817), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10097PolyExtStep::Sub(4998, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10098PolyExtStep::AndEqz(5070, 4999), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10099PolyExtStep::Mul(798, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10100PolyExtStep::Mul(800, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10101PolyExtStep::Mul(802, 5), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10102PolyExtStep::Mul(804, 4), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10103PolyExtStep::Mul(814, 3), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10104PolyExtStep::Mul(817, 2), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10105PolyExtStep::Add(764, 5000), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10106PolyExtStep::Add(5006, 5001), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10107PolyExtStep::Add(5007, 5002), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10108PolyExtStep::Add(5008, 5003), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10109PolyExtStep::Add(5009, 5004), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10110PolyExtStep::Add(5010, 5005), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10111PolyExtStep::Sub(5011, 4113), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10112PolyExtStep::AndEqz(5071, 5012), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10113PolyExtStep::Mul(737, 74), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10114PolyExtStep::Mul(737, 75), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10115PolyExtStep::Mul(737, 76), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10116PolyExtStep::Mul(737, 77), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10117PolyExtStep::Mul(737, 78), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10118PolyExtStep::Mul(737, 79), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10119PolyExtStep::Mul(737, 80), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10120PolyExtStep::Mul(737, 81), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10121PolyExtStep::Mul(737, 82), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10122PolyExtStep::Mul(737, 83), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10123PolyExtStep::Mul(737, 84), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10124PolyExtStep::Mul(737, 85), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10125PolyExtStep::Mul(737, 86), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10126PolyExtStep::Mul(737, 87), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10127PolyExtStep::Mul(737, 88), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10128PolyExtStep::Mul(737, 89), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10129PolyExtStep::Mul(737, 90), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10130PolyExtStep::Mul(737, 91), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10131PolyExtStep::Mul(737, 92), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10132PolyExtStep::Mul(737, 93), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10133PolyExtStep::Mul(737, 94), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10134PolyExtStep::Mul(737, 95), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10135PolyExtStep::Mul(737, 96), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10136PolyExtStep::Mul(737, 97), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10137PolyExtStep::Mul(764, 121), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10138PolyExtStep::Mul(764, 120), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10139PolyExtStep::Mul(764, 119), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10140PolyExtStep::Mul(764, 118), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10141PolyExtStep::Mul(764, 117), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10142PolyExtStep::Mul(764, 116), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10143PolyExtStep::Mul(764, 115), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10144PolyExtStep::Mul(764, 114), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10145PolyExtStep::Mul(764, 113), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10146PolyExtStep::Mul(764, 112), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10147PolyExtStep::Mul(764, 111), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10148PolyExtStep::Mul(764, 110), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10149PolyExtStep::Mul(764, 109), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10150PolyExtStep::Mul(764, 108), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10151PolyExtStep::Mul(764, 107), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10152PolyExtStep::Mul(764, 106), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10153PolyExtStep::Mul(764, 105), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10154PolyExtStep::Mul(764, 104), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10155PolyExtStep::Mul(764, 103), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10156PolyExtStep::Mul(764, 102), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10157PolyExtStep::Mul(764, 101), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10158PolyExtStep::Mul(764, 100), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10159PolyExtStep::Mul(764, 99), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10160PolyExtStep::Mul(764, 98), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10161PolyExtStep::Mul(798, 145), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10162PolyExtStep::Mul(798, 144), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10163PolyExtStep::Mul(798, 143), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10164PolyExtStep::Mul(798, 142), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10165PolyExtStep::Mul(798, 141), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10166PolyExtStep::Mul(798, 140), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10167PolyExtStep::Mul(798, 139), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10168PolyExtStep::Mul(798, 138), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10169PolyExtStep::Mul(798, 137), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10170PolyExtStep::Mul(798, 136), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10171PolyExtStep::Mul(798, 135), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10172PolyExtStep::Mul(798, 134), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10173PolyExtStep::Mul(798, 133), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10174PolyExtStep::Mul(798, 132), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10175PolyExtStep::Mul(798, 131), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10176PolyExtStep::Mul(798, 130), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10177PolyExtStep::Mul(798, 129), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10178PolyExtStep::Mul(798, 128), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10179PolyExtStep::Mul(798, 127), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10180PolyExtStep::Mul(798, 126), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10181PolyExtStep::Mul(798, 125), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10182PolyExtStep::Mul(798, 124), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10183PolyExtStep::Mul(798, 123), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10184PolyExtStep::Mul(798, 122), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10185PolyExtStep::Mul(800, 169), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10186PolyExtStep::Mul(800, 168), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10187PolyExtStep::Mul(800, 167), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10188PolyExtStep::Mul(800, 166), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10189PolyExtStep::Mul(800, 165), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10190PolyExtStep::Mul(800, 164), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10191PolyExtStep::Mul(800, 163), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10192PolyExtStep::Mul(800, 162), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10193PolyExtStep::Mul(800, 161), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10194PolyExtStep::Mul(800, 160), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10195PolyExtStep::Mul(800, 159), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10196PolyExtStep::Mul(800, 158), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10197PolyExtStep::Mul(800, 157), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10198PolyExtStep::Mul(800, 156), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10199PolyExtStep::Mul(800, 155), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10200PolyExtStep::Mul(800, 154), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10201PolyExtStep::Mul(800, 153), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10202PolyExtStep::Mul(800, 152), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10203PolyExtStep::Mul(800, 151), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10204PolyExtStep::Mul(800, 150), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10205PolyExtStep::Mul(800, 149), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10206PolyExtStep::Mul(800, 148), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10207PolyExtStep::Mul(800, 147), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10208PolyExtStep::Mul(800, 146), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10209PolyExtStep::Mul(802, 193), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10210PolyExtStep::Mul(802, 192), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10211PolyExtStep::Mul(802, 191), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10212PolyExtStep::Mul(802, 190), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10213PolyExtStep::Mul(802, 189), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10214PolyExtStep::Mul(802, 188), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10215PolyExtStep::Mul(802, 187), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10216PolyExtStep::Mul(802, 186), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10217PolyExtStep::Mul(802, 185), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10218PolyExtStep::Mul(802, 184), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10219PolyExtStep::Mul(802, 183), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10220PolyExtStep::Mul(802, 182), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10221PolyExtStep::Mul(802, 181), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10222PolyExtStep::Mul(802, 180), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10223PolyExtStep::Mul(802, 179), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10224PolyExtStep::Mul(802, 178), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10225PolyExtStep::Mul(802, 177), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10226PolyExtStep::Mul(802, 176), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10227PolyExtStep::Mul(802, 175), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10228PolyExtStep::Mul(802, 174), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10229PolyExtStep::Mul(802, 173), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10230PolyExtStep::Mul(802, 172), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10231PolyExtStep::Mul(802, 171), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10232PolyExtStep::Mul(802, 170), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10233PolyExtStep::Mul(804, 217), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10234PolyExtStep::Mul(804, 216), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10235PolyExtStep::Mul(804, 215), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10236PolyExtStep::Mul(804, 214), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10237PolyExtStep::Mul(804, 213), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10238PolyExtStep::Mul(804, 212), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10239PolyExtStep::Mul(804, 211), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10240PolyExtStep::Mul(804, 210), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10241PolyExtStep::Mul(804, 209), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10242PolyExtStep::Mul(804, 208), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10243PolyExtStep::Mul(804, 207), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10244PolyExtStep::Mul(804, 206), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10245PolyExtStep::Mul(804, 205), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10246PolyExtStep::Mul(804, 204), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10247PolyExtStep::Mul(804, 203), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10248PolyExtStep::Mul(804, 202), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10249PolyExtStep::Mul(804, 201), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10250PolyExtStep::Mul(804, 200), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10251PolyExtStep::Mul(804, 199), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10252PolyExtStep::Mul(804, 198), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10253PolyExtStep::Mul(804, 197), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10254PolyExtStep::Mul(804, 196), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10255PolyExtStep::Mul(804, 195), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10256PolyExtStep::Mul(804, 194), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10257PolyExtStep::Mul(814, 241), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10258PolyExtStep::Mul(814, 240), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10259PolyExtStep::Mul(814, 239), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10260PolyExtStep::Mul(814, 238), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10261PolyExtStep::Mul(814, 237), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10262PolyExtStep::Mul(814, 236), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10263PolyExtStep::Mul(814, 235), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10264PolyExtStep::Mul(814, 234), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10265PolyExtStep::Mul(814, 233), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10266PolyExtStep::Mul(814, 232), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10267PolyExtStep::Mul(814, 231), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10268PolyExtStep::Mul(814, 230), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10269PolyExtStep::Mul(814, 229), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10270PolyExtStep::Mul(814, 228), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10271PolyExtStep::Mul(814, 227), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10272PolyExtStep::Mul(814, 226), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10273PolyExtStep::Mul(814, 225), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10274PolyExtStep::Mul(814, 224), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10275PolyExtStep::Mul(814, 223), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10276PolyExtStep::Mul(814, 222), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10277PolyExtStep::Mul(814, 221), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10278PolyExtStep::Mul(814, 220), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10279PolyExtStep::Mul(814, 219), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10280PolyExtStep::Mul(814, 218), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10281PolyExtStep::Mul(817, 265), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10282PolyExtStep::Mul(817, 264), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10283PolyExtStep::Mul(817, 263), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10284PolyExtStep::Mul(817, 262), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10285PolyExtStep::Mul(817, 261), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10286PolyExtStep::Mul(817, 260), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10287PolyExtStep::Mul(817, 259), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10288PolyExtStep::Mul(817, 258), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10289PolyExtStep::Mul(817, 257), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10290PolyExtStep::Mul(817, 256), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10291PolyExtStep::Mul(817, 255), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10292PolyExtStep::Mul(817, 254), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10293PolyExtStep::Mul(817, 253), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10294PolyExtStep::Mul(817, 252), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10295PolyExtStep::Mul(817, 251), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10296PolyExtStep::Mul(817, 250), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10297PolyExtStep::Mul(817, 249), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10298PolyExtStep::Mul(817, 248), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10299PolyExtStep::Mul(817, 247), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10300PolyExtStep::Mul(817, 246), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10301PolyExtStep::Mul(817, 245), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10302PolyExtStep::Mul(817, 244), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10303PolyExtStep::Mul(817, 243), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10304PolyExtStep::Mul(817, 242), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10305PolyExtStep::Add(5013, 5037), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10306PolyExtStep::Add(5014, 5038), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10307PolyExtStep::Add(5015, 5039), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10308PolyExtStep::Add(5016, 5040), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10309PolyExtStep::Add(5017, 5041), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10310PolyExtStep::Add(5018, 5042), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10311PolyExtStep::Add(5019, 5043), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10312PolyExtStep::Add(5020, 5044), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10313PolyExtStep::Add(5021, 5045), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10314PolyExtStep::Add(5022, 5046), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10315PolyExtStep::Add(5023, 5047), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10316PolyExtStep::Add(5024, 5048), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10317PolyExtStep::Add(5025, 5049), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10318PolyExtStep::Add(5026, 5050), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10319PolyExtStep::Add(5027, 5051), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10320PolyExtStep::Add(5028, 5052), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10321PolyExtStep::Add(5029, 5053), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10322PolyExtStep::Add(5030, 5054), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10323PolyExtStep::Add(5031, 5055), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10324PolyExtStep::Add(5032, 5056), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10325PolyExtStep::Add(5033, 5057), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10326PolyExtStep::Add(5034, 5058), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10327PolyExtStep::Add(5035, 5059), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10328PolyExtStep::Add(5036, 5060), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10329PolyExtStep::Add(5205, 5061), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10330PolyExtStep::Add(5206, 5062), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10331PolyExtStep::Add(5207, 5063), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10332PolyExtStep::Add(5208, 5064), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10333PolyExtStep::Add(5209, 5065), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10334PolyExtStep::Add(5210, 5066), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10335PolyExtStep::Add(5211, 5067), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10336PolyExtStep::Add(5212, 5068), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10337PolyExtStep::Add(5213, 5069), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10338PolyExtStep::Add(5214, 5070), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10339PolyExtStep::Add(5215, 5071), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10340PolyExtStep::Add(5216, 5072), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10341PolyExtStep::Add(5217, 5073), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10342PolyExtStep::Add(5218, 5074), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10343PolyExtStep::Add(5219, 5075), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10344PolyExtStep::Add(5220, 5076), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10345PolyExtStep::Add(5221, 5077), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10346PolyExtStep::Add(5222, 5078), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10347PolyExtStep::Add(5223, 5079), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10348PolyExtStep::Add(5224, 5080), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10349PolyExtStep::Add(5225, 5081), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10350PolyExtStep::Add(5226, 5082), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10351PolyExtStep::Add(5227, 5083), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10352PolyExtStep::Add(5228, 5084), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10353PolyExtStep::Add(5229, 5085), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10354PolyExtStep::Add(5230, 5086), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10355PolyExtStep::Add(5231, 5087), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10356PolyExtStep::Add(5232, 5088), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10357PolyExtStep::Add(5233, 5089), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10358PolyExtStep::Add(5234, 5090), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10359PolyExtStep::Add(5235, 5091), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10360PolyExtStep::Add(5236, 5092), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10361PolyExtStep::Add(5237, 5093), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10362PolyExtStep::Add(5238, 5094), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10363PolyExtStep::Add(5239, 5095), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10364PolyExtStep::Add(5240, 5096), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10365PolyExtStep::Add(5241, 5097), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10366PolyExtStep::Add(5242, 5098), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10367PolyExtStep::Add(5243, 5099), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10368PolyExtStep::Add(5244, 5100), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10369PolyExtStep::Add(5245, 5101), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10370PolyExtStep::Add(5246, 5102), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10371PolyExtStep::Add(5247, 5103), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10372PolyExtStep::Add(5248, 5104), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10373PolyExtStep::Add(5249, 5105), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10374PolyExtStep::Add(5250, 5106), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10375PolyExtStep::Add(5251, 5107), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10376PolyExtStep::Add(5252, 5108), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10377PolyExtStep::Add(5253, 5109), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10378PolyExtStep::Add(5254, 5110), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10379PolyExtStep::Add(5255, 5111), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10380PolyExtStep::Add(5256, 5112), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10381PolyExtStep::Add(5257, 5113), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10382PolyExtStep::Add(5258, 5114), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10383PolyExtStep::Add(5259, 5115), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10384PolyExtStep::Add(5260, 5116), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10385PolyExtStep::Add(5261, 5117), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10386PolyExtStep::Add(5262, 5118), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10387PolyExtStep::Add(5263, 5119), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10388PolyExtStep::Add(5264, 5120), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10389PolyExtStep::Add(5265, 5121), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10390PolyExtStep::Add(5266, 5122), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10391PolyExtStep::Add(5267, 5123), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10392PolyExtStep::Add(5268, 5124), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10393PolyExtStep::Add(5269, 5125), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10394PolyExtStep::Add(5270, 5126), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10395PolyExtStep::Add(5271, 5127), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10396PolyExtStep::Add(5272, 5128), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10397PolyExtStep::Add(5273, 5129), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10398PolyExtStep::Add(5274, 5130), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10399PolyExtStep::Add(5275, 5131), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10400PolyExtStep::Add(5276, 5132), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10401PolyExtStep::Add(5277, 5133), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10402PolyExtStep::Add(5278, 5134), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10403PolyExtStep::Add(5279, 5135), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10404PolyExtStep::Add(5280, 5136), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10405PolyExtStep::Add(5281, 5137), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10406PolyExtStep::Add(5282, 5138), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10407PolyExtStep::Add(5283, 5139), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10408PolyExtStep::Add(5284, 5140), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10409PolyExtStep::Add(5285, 5141), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10410PolyExtStep::Add(5286, 5142), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10411PolyExtStep::Add(5287, 5143), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10412PolyExtStep::Add(5288, 5144), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10413PolyExtStep::Add(5289, 5145), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10414PolyExtStep::Add(5290, 5146), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10415PolyExtStep::Add(5291, 5147), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10416PolyExtStep::Add(5292, 5148), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10417PolyExtStep::Add(5293, 5149), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10418PolyExtStep::Add(5294, 5150), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10419PolyExtStep::Add(5295, 5151), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10420PolyExtStep::Add(5296, 5152), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10421PolyExtStep::Add(5297, 5153), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10422PolyExtStep::Add(5298, 5154), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10423PolyExtStep::Add(5299, 5155), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10424PolyExtStep::Add(5300, 5156), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10425PolyExtStep::Add(5301, 5157), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10426PolyExtStep::Add(5302, 5158), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10427PolyExtStep::Add(5303, 5159), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10428PolyExtStep::Add(5304, 5160), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10429PolyExtStep::Add(5305, 5161), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10430PolyExtStep::Add(5306, 5162), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10431PolyExtStep::Add(5307, 5163), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10432PolyExtStep::Add(5308, 5164), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10433PolyExtStep::Add(5309, 5165), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10434PolyExtStep::Add(5310, 5166), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10435PolyExtStep::Add(5311, 5167), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10436PolyExtStep::Add(5312, 5168), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10437PolyExtStep::Add(5313, 5169), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10438PolyExtStep::Add(5314, 5170), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10439PolyExtStep::Add(5315, 5171), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10440PolyExtStep::Add(5316, 5172), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10441PolyExtStep::Add(5317, 5173), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10442PolyExtStep::Add(5318, 5174), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10443PolyExtStep::Add(5319, 5175), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10444PolyExtStep::Add(5320, 5176), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10445PolyExtStep::Add(5321, 5177), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10446PolyExtStep::Add(5322, 5178), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10447PolyExtStep::Add(5323, 5179), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10448PolyExtStep::Add(5324, 5180), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10449PolyExtStep::Add(5325, 5181), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10450PolyExtStep::Add(5326, 5182), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10451PolyExtStep::Add(5327, 5183), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10452PolyExtStep::Add(5328, 5184), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10453PolyExtStep::Add(5329, 5185), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10454PolyExtStep::Add(5330, 5186), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10455PolyExtStep::Add(5331, 5187), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10456PolyExtStep::Add(5332, 5188), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10457PolyExtStep::Add(5333, 5189), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10458PolyExtStep::Add(5334, 5190), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10459PolyExtStep::Add(5335, 5191), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10460PolyExtStep::Add(5336, 5192), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10461PolyExtStep::Add(5337, 5193), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10462PolyExtStep::Add(5338, 5194), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10463PolyExtStep::Add(5339, 5195), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10464PolyExtStep::Add(5340, 5196), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10465PolyExtStep::Add(5341, 5197), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10466PolyExtStep::Add(5342, 5198), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10467PolyExtStep::Add(5343, 5199), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10468PolyExtStep::Add(5344, 5200), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10469PolyExtStep::Add(5345, 5201), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10470PolyExtStep::Add(5346, 5202), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10471PolyExtStep::Add(5347, 5203), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10472PolyExtStep::Add(5348, 5204), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10473PolyExtStep::Add(4114, 5349), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10474PolyExtStep::Mul(5373, 5373), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10475PolyExtStep::Mul(5374, 5373), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10476PolyExtStep::Sub(5375, 649), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10477PolyExtStep::AndEqz(5072, 5376), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10478PolyExtStep::Mul(649, 649), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10479PolyExtStep::Mul(5377, 5373), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10480PolyExtStep::Sub(5378, 646), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10481PolyExtStep::AndEqz(5073, 5379), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10482PolyExtStep::Add(4115, 5350), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10483PolyExtStep::Mul(5380, 5380), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10484PolyExtStep::Mul(5381, 5380), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10485PolyExtStep::Sub(5382, 659), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10486PolyExtStep::AndEqz(5074, 5383), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10487PolyExtStep::Mul(659, 659), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10488PolyExtStep::Mul(5384, 5380), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10489PolyExtStep::Sub(5385, 652), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10490PolyExtStep::AndEqz(5075, 5386), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10491PolyExtStep::Add(4116, 5351), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10492PolyExtStep::Mul(5387, 5387), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10493PolyExtStep::Mul(5388, 5387), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10494PolyExtStep::Sub(5389, 673), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10495PolyExtStep::AndEqz(5076, 5390), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10496PolyExtStep::Mul(673, 673), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10497PolyExtStep::Mul(5391, 5387), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10498PolyExtStep::Sub(5392, 666), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10499PolyExtStep::AndEqz(5077, 5393), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10500PolyExtStep::Add(4117, 5352), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10501PolyExtStep::Mul(5394, 5394), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10502PolyExtStep::Mul(5395, 5394), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10503PolyExtStep::Sub(5396, 544), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10504PolyExtStep::AndEqz(5078, 5397), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10505PolyExtStep::Mul(544, 544), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10506PolyExtStep::Mul(5398, 5394), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10507PolyExtStep::Sub(5399, 676), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10508PolyExtStep::AndEqz(5079, 5400), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10509PolyExtStep::Add(4118, 5353), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10510PolyExtStep::Mul(5401, 5401), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10511PolyExtStep::Mul(5402, 5401), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10512PolyExtStep::Sub(5403, 552), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10513PolyExtStep::AndEqz(5080, 5404), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10514PolyExtStep::Mul(552, 552), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10515PolyExtStep::Mul(5405, 5401), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10516PolyExtStep::Sub(5406, 551), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10517PolyExtStep::AndEqz(5081, 5407), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10518PolyExtStep::Add(4119, 5354), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10519PolyExtStep::Mul(5408, 5408), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10520PolyExtStep::Mul(5409, 5408), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10521PolyExtStep::Sub(5410, 556), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10522PolyExtStep::AndEqz(5082, 5411), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10523PolyExtStep::Mul(556, 556), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10524PolyExtStep::Mul(5412, 5408), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10525PolyExtStep::Sub(5413, 555), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10526PolyExtStep::AndEqz(5083, 5414), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10527PolyExtStep::Add(4120, 5355), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10528PolyExtStep::Mul(5415, 5415), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10529PolyExtStep::Mul(5416, 5415), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10530PolyExtStep::Sub(5417, 564), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10531PolyExtStep::AndEqz(5084, 5418), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10532PolyExtStep::Mul(564, 564), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10533PolyExtStep::Mul(5419, 5415), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10534PolyExtStep::Sub(5420, 563), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10535PolyExtStep::AndEqz(5085, 5421), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10536PolyExtStep::Add(4121, 5356), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10537PolyExtStep::Mul(5422, 5422), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10538PolyExtStep::Mul(5423, 5422), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10539PolyExtStep::Sub(5424, 570), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10540PolyExtStep::AndEqz(5086, 5425), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10541PolyExtStep::Mul(570, 570), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10542PolyExtStep::Mul(5426, 5422), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10543PolyExtStep::Sub(5427, 571), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10544PolyExtStep::AndEqz(5087, 5428), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10545PolyExtStep::Add(4122, 5357), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10546PolyExtStep::Mul(5429, 5429), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10547PolyExtStep::Mul(5430, 5429), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10548PolyExtStep::Sub(5431, 573), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10549PolyExtStep::AndEqz(5088, 5432), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10550PolyExtStep::Mul(573, 573), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10551PolyExtStep::Mul(5433, 5429), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10552PolyExtStep::Sub(5434, 572), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10553PolyExtStep::AndEqz(5089, 5435), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10554PolyExtStep::Add(4123, 5358), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10555PolyExtStep::Mul(5436, 5436), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10556PolyExtStep::Mul(5437, 5436), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10557PolyExtStep::Sub(5438, 575), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10558PolyExtStep::AndEqz(5090, 5439), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10559PolyExtStep::Mul(575, 575), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10560PolyExtStep::Mul(5440, 5436), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10561PolyExtStep::Sub(5441, 574), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10562PolyExtStep::AndEqz(5091, 5442), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10563PolyExtStep::Add(4124, 5359), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10564PolyExtStep::Mul(5443, 5443), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10565PolyExtStep::Mul(5444, 5443), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10566PolyExtStep::Sub(5445, 577), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10567PolyExtStep::AndEqz(5092, 5446), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10568PolyExtStep::Mul(577, 577), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10569PolyExtStep::Mul(5447, 5443), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10570PolyExtStep::Sub(5448, 576), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10571PolyExtStep::AndEqz(5093, 5449), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10572PolyExtStep::Add(4125, 5360), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10573PolyExtStep::Mul(5450, 5450), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10574PolyExtStep::Mul(5451, 5450), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10575PolyExtStep::Sub(5452, 587), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10576PolyExtStep::AndEqz(5094, 5453), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10577PolyExtStep::Mul(587, 587), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10578PolyExtStep::Mul(5454, 5450), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10579PolyExtStep::Sub(5455, 578), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10580PolyExtStep::AndEqz(5095, 5456), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10581PolyExtStep::Add(4126, 5361), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10582PolyExtStep::Mul(5457, 5457), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10583PolyExtStep::Mul(5458, 5457), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10584PolyExtStep::Sub(5459, 739), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10585PolyExtStep::AndEqz(5096, 5460), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10586PolyExtStep::Mul(739, 739), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10587PolyExtStep::Mul(5461, 5457), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10588PolyExtStep::Sub(5462, 588), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10589PolyExtStep::AndEqz(5097, 5463), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10590PolyExtStep::Add(4127, 5362), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10591PolyExtStep::Mul(5464, 5464), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10592PolyExtStep::Mul(5465, 5464), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10593PolyExtStep::Sub(5466, 741), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10594PolyExtStep::AndEqz(5098, 5467), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10595PolyExtStep::Mul(741, 741), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10596PolyExtStep::Mul(5468, 5464), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10597PolyExtStep::Sub(5469, 740), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10598PolyExtStep::AndEqz(5099, 5470), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10599PolyExtStep::Add(4128, 5363), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10600PolyExtStep::Mul(5471, 5471), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10601PolyExtStep::Mul(5472, 5471), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10602PolyExtStep::Sub(5473, 743), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10603PolyExtStep::AndEqz(5100, 5474), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10604PolyExtStep::Mul(743, 743), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10605PolyExtStep::Mul(5475, 5471), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10606PolyExtStep::Sub(5476, 742), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10607PolyExtStep::AndEqz(5101, 5477), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10608PolyExtStep::Add(4129, 5364), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10609PolyExtStep::Mul(5478, 5478), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10610PolyExtStep::Mul(5479, 5478), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10611PolyExtStep::Sub(5480, 745), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10612PolyExtStep::AndEqz(5102, 5481), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10613PolyExtStep::Mul(745, 745), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10614PolyExtStep::Mul(5482, 5478), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10615PolyExtStep::Sub(5483, 744), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10616PolyExtStep::AndEqz(5103, 5484), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10617PolyExtStep::Add(4130, 5365), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10618PolyExtStep::Mul(5485, 5485), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10619PolyExtStep::Mul(5486, 5485), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10620PolyExtStep::Sub(5487, 747), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10621PolyExtStep::AndEqz(5104, 5488), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10622PolyExtStep::Mul(747, 747), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10623PolyExtStep::Mul(5489, 5485), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10624PolyExtStep::Sub(5490, 746), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10625PolyExtStep::AndEqz(5105, 5491), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10626PolyExtStep::Add(4131, 5366), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10627PolyExtStep::Mul(5492, 5492), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10628PolyExtStep::Mul(5493, 5492), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10629PolyExtStep::Sub(5494, 766), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10630PolyExtStep::AndEqz(5106, 5495), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10631PolyExtStep::Mul(766, 766), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10632PolyExtStep::Mul(5496, 5492), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10633PolyExtStep::Sub(5497, 760), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10634PolyExtStep::AndEqz(5107, 5498), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10635PolyExtStep::Add(4132, 5367), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10636PolyExtStep::Mul(5499, 5499), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10637PolyExtStep::Mul(5500, 5499), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10638PolyExtStep::Sub(5501, 768), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10639PolyExtStep::AndEqz(5108, 5502), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10640PolyExtStep::Mul(768, 768), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10641PolyExtStep::Mul(5503, 5499), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10642PolyExtStep::Sub(5504, 767), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10643PolyExtStep::AndEqz(5109, 5505), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10644PolyExtStep::Add(4133, 5368), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10645PolyExtStep::Mul(5506, 5506), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10646PolyExtStep::Mul(5507, 5506), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10647PolyExtStep::Sub(5508, 761), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10648PolyExtStep::AndEqz(5110, 5509), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10649PolyExtStep::Mul(761, 761), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10650PolyExtStep::Mul(5510, 5506), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10651PolyExtStep::Sub(5511, 769), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10652PolyExtStep::AndEqz(5111, 5512), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10653PolyExtStep::Add(4134, 5369), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10654PolyExtStep::Mul(5513, 5513), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10655PolyExtStep::Mul(5514, 5513), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10656PolyExtStep::Sub(5515, 771), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10657PolyExtStep::AndEqz(5112, 5516), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10658PolyExtStep::Mul(771, 771), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10659PolyExtStep::Mul(5517, 5513), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10660PolyExtStep::Sub(5518, 770), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10661PolyExtStep::AndEqz(5113, 5519), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10662PolyExtStep::Add(4135, 5370), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10663PolyExtStep::Mul(5520, 5520), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10664PolyExtStep::Mul(5521, 5520), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10665PolyExtStep::Sub(5522, 756), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10666PolyExtStep::AndEqz(5114, 5523), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10667PolyExtStep::Mul(756, 756), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10668PolyExtStep::Mul(5524, 5520), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10669PolyExtStep::Sub(5525, 772), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10670PolyExtStep::AndEqz(5115, 5526), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10671PolyExtStep::Add(4136, 5371), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10672PolyExtStep::Mul(5527, 5527), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10673PolyExtStep::Mul(5528, 5527), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10674PolyExtStep::Sub(5529, 762), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10675PolyExtStep::AndEqz(5116, 5530), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10676PolyExtStep::Mul(762, 762), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10677PolyExtStep::Mul(5531, 5527), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10678PolyExtStep::Sub(5532, 757), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10679PolyExtStep::AndEqz(5117, 5533), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10680PolyExtStep::Add(4137, 5372), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10681PolyExtStep::Mul(5534, 5534), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10682PolyExtStep::Mul(5535, 5534), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10683PolyExtStep::Sub(5536, 732), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10684PolyExtStep::AndEqz(5118, 5537), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10685PolyExtStep::Mul(732, 732), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10686PolyExtStep::Mul(5538, 5534), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10687PolyExtStep::Sub(5539, 781), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10688PolyExtStep::AndEqz(5119, 5540), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10689PolyExtStep::Add(646, 652), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10690PolyExtStep::Add(666, 676), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10691PolyExtStep::Mul(652, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10692PolyExtStep::Add(5543, 5542), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10693PolyExtStep::Add(1723, 5541), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10694PolyExtStep::Mul(5542, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10695PolyExtStep::Add(5546, 5545), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10696PolyExtStep::Mul(5541, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10697PolyExtStep::Add(5548, 5544), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10698PolyExtStep::Add(5545, 5549), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10699PolyExtStep::Add(5544, 5547), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10700PolyExtStep::Add(551, 555), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10701PolyExtStep::Add(563, 571), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10702PolyExtStep::Mul(555, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10703PolyExtStep::Add(5554, 5553), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10704PolyExtStep::Mul(571, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10705PolyExtStep::Add(5556, 5552), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10706PolyExtStep::Mul(5553, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10707PolyExtStep::Add(5558, 5557), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10708PolyExtStep::Mul(5552, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10709PolyExtStep::Add(5560, 5555), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10710PolyExtStep::Add(5557, 5561), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10711PolyExtStep::Add(5555, 5559), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10712PolyExtStep::Add(572, 574), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10713PolyExtStep::Add(576, 578), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10714PolyExtStep::Add(2193, 5565), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10715PolyExtStep::Mul(578, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10716PolyExtStep::Add(5567, 5564), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10717PolyExtStep::Mul(5565, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10718PolyExtStep::Add(5569, 5568), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10719PolyExtStep::Mul(5564, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10720PolyExtStep::Add(5571, 5566), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10721PolyExtStep::Add(5568, 5572), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10722PolyExtStep::Add(5566, 5570), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10723PolyExtStep::Add(588, 740), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10724PolyExtStep::Add(742, 744), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10725PolyExtStep::Add(2197, 5576), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10726PolyExtStep::Mul(744, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10727PolyExtStep::Add(5578, 5575), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10728PolyExtStep::Mul(5576, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10729PolyExtStep::Add(5580, 5579), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10730PolyExtStep::Mul(5575, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10731PolyExtStep::Add(5582, 5577), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10732PolyExtStep::Add(5579, 5583), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10733PolyExtStep::Add(5577, 5581), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10734PolyExtStep::Add(746, 760), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10735PolyExtStep::Add(767, 769), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10736PolyExtStep::Mul(760, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10737PolyExtStep::Add(5588, 5587), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10738PolyExtStep::Mul(769, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10739PolyExtStep::Add(5590, 5586), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10740PolyExtStep::Mul(5587, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10741PolyExtStep::Add(5592, 5591), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10742PolyExtStep::Mul(5586, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10743PolyExtStep::Add(5594, 5589), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10744PolyExtStep::Add(5591, 5595), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10745PolyExtStep::Add(5589, 5593), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10746PolyExtStep::Add(770, 772), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10747PolyExtStep::Add(757, 781), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10748PolyExtStep::Mul(772, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10749PolyExtStep::Add(5600, 5599), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10750PolyExtStep::Mul(781, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10751PolyExtStep::Add(5602, 5598), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10752PolyExtStep::Mul(5599, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10753PolyExtStep::Add(5604, 5603), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10754PolyExtStep::Mul(5598, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10755PolyExtStep::Add(5606, 5601), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10756PolyExtStep::Add(5603, 5607), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10757PolyExtStep::Add(5601, 5605), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10758PolyExtStep::Add(5550, 5562), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10759PolyExtStep::Add(5549, 5561), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10760PolyExtStep::Add(5551, 5563), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10761PolyExtStep::Add(5547, 5559), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10762PolyExtStep::Add(5610, 5573), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10763PolyExtStep::Add(5611, 5572), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10764PolyExtStep::Add(5612, 5574), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10765PolyExtStep::Add(5613, 5570), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10766PolyExtStep::Add(5614, 5584), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10767PolyExtStep::Add(5615, 5583), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10768PolyExtStep::Add(5616, 5585), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10769PolyExtStep::Add(5617, 5581), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10770PolyExtStep::Add(5618, 5596), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10771PolyExtStep::Add(5619, 5595), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10772PolyExtStep::Add(5620, 5597), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10773PolyExtStep::Add(5621, 5593), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10774PolyExtStep::Add(5622, 5608), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10775PolyExtStep::Add(5623, 5607), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10776PolyExtStep::Add(5624, 5609), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10777PolyExtStep::Add(5625, 5605), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
10778PolyExtStep::Add(5550, 5626), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10779PolyExtStep::Add(5549, 5627), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10780PolyExtStep::Add(5551, 5628), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10781PolyExtStep::Add(5547, 5629), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10782PolyExtStep::Add(5562, 5626), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10783PolyExtStep::Add(5561, 5627), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10784PolyExtStep::Add(5563, 5628), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10785PolyExtStep::Add(5559, 5629), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10786PolyExtStep::Add(5573, 5626), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10787PolyExtStep::Add(5572, 5627), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10788PolyExtStep::Add(5574, 5628), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10789PolyExtStep::Add(5570, 5629), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10790PolyExtStep::Add(5584, 5626), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10791PolyExtStep::Add(5583, 5627), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10792PolyExtStep::Add(5585, 5628), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10793PolyExtStep::Add(5581, 5629), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10794PolyExtStep::Add(5596, 5626), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10795PolyExtStep::Add(5595, 5627), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10796PolyExtStep::Add(5597, 5628), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10797PolyExtStep::Add(5593, 5629), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10798PolyExtStep::Add(5608, 5626), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10799PolyExtStep::Add(5607, 5627), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10800PolyExtStep::Add(5609, 5628), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10801PolyExtStep::Add(5605, 5629), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10802PolyExtStep::AndEqz(5120, 4095), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10803PolyExtStep::AndEqz(5121, 4096), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10804PolyExtStep::AndEqz(5122, 4097), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10805PolyExtStep::AndEqz(5123, 4098), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10806PolyExtStep::AndEqz(5124, 4099), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10807PolyExtStep::AndEqz(5125, 4100), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10808PolyExtStep::Sub(4983, 810), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10809PolyExtStep::AndEqz(5126, 5654), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10810PolyExtStep::Sub(4985, 1154), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10811PolyExtStep::AndEqz(5127, 5655), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10812PolyExtStep::AndEqz(5128, 4102), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10813PolyExtStep::Sub(4973, 1160), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10814PolyExtStep::AndEqz(5129, 5656), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10815PolyExtStep::AndEqz(5130, 4104), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10816PolyExtStep::Sub(5630, 1373), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10817PolyExtStep::AndEqz(5131, 5657), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10818PolyExtStep::Sub(5631, 1375), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10819PolyExtStep::AndEqz(5132, 5658), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10820PolyExtStep::Sub(5632, 1382), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10821PolyExtStep::AndEqz(5133, 5659), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10822PolyExtStep::Sub(5633, 1383), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10823PolyExtStep::AndEqz(5134, 5660), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10824PolyExtStep::Sub(5634, 1385), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10825PolyExtStep::AndEqz(5135, 5661), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10826PolyExtStep::Sub(5635, 1391), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10827PolyExtStep::AndEqz(5136, 5662), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10828PolyExtStep::Sub(5636, 1392), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10829PolyExtStep::AndEqz(5137, 5663), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10830PolyExtStep::Sub(5637, 1394), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10831PolyExtStep::AndEqz(5138, 5664), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10832PolyExtStep::Sub(5638, 1401), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10833PolyExtStep::AndEqz(5139, 5665), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10834PolyExtStep::Sub(5639, 1402), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10835PolyExtStep::AndEqz(5140, 5666), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10836PolyExtStep::Sub(5640, 1404), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10837PolyExtStep::AndEqz(5141, 5667), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10838PolyExtStep::Sub(5641, 1410), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10839PolyExtStep::AndEqz(5142, 5668), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10840PolyExtStep::Sub(5642, 1411), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10841PolyExtStep::AndEqz(5143, 5669), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10842PolyExtStep::Sub(5643, 1424), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10843PolyExtStep::AndEqz(5144, 5670), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10844PolyExtStep::Sub(5644, 1427), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10845PolyExtStep::AndEqz(5145, 5671), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10846PolyExtStep::Sub(5645, 1426), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10847PolyExtStep::AndEqz(5146, 5672), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10848PolyExtStep::Sub(5646, 1428), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10849PolyExtStep::AndEqz(5147, 5673), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10850PolyExtStep::Sub(5647, 1829), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10851PolyExtStep::AndEqz(5148, 5674), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10852PolyExtStep::Sub(5648, 1830), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10853PolyExtStep::AndEqz(5149, 5675), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10854PolyExtStep::Sub(5649, 1429), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10855PolyExtStep::AndEqz(5150, 5676), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10856PolyExtStep::Sub(5650, 1430), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10857PolyExtStep::AndEqz(5151, 5677), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10858PolyExtStep::Sub(5651, 1431), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10859PolyExtStep::AndEqz(5152, 5678), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10860PolyExtStep::Sub(5652, 1432), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10861PolyExtStep::AndEqz(5153, 5679), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10862PolyExtStep::Sub(5653, 1439), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10863PolyExtStep::AndEqz(5154, 5680), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
10864PolyExtStep::Sub(3951, 4147), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10865PolyExtStep::AndEqz(5155, 5681), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10866PolyExtStep::AndCond(5050, 377, 5156), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
10867PolyExtStep::Add(4114, 266), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10868PolyExtStep::Mul(5682, 5682), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10869PolyExtStep::Mul(5683, 5682), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10870PolyExtStep::Sub(5684, 615), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10871PolyExtStep::AndEqz(0, 5685), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10872PolyExtStep::Mul(615, 615), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10873PolyExtStep::Mul(5686, 5682), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10874PolyExtStep::Sub(5687, 608), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10875PolyExtStep::AndEqz(5158, 5688), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10876PolyExtStep::Add(608, 4115), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10877PolyExtStep::Add(5689, 4116), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10878PolyExtStep::Add(5690, 4117), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10879PolyExtStep::Add(5691, 4118), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10880PolyExtStep::Add(5692, 4119), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10881PolyExtStep::Add(5693, 4120), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10882PolyExtStep::Add(5694, 4121), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10883PolyExtStep::Add(5695, 4122), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10884PolyExtStep::Add(5696, 4123), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10885PolyExtStep::Add(5697, 4124), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10886PolyExtStep::Add(5698, 4125), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10887PolyExtStep::Add(5699, 4126), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10888PolyExtStep::Add(5700, 4127), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10889PolyExtStep::Add(5701, 4128), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10890PolyExtStep::Add(5702, 4129), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10891PolyExtStep::Add(5703, 4130), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10892PolyExtStep::Add(5704, 4131), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10893PolyExtStep::Add(5705, 4132), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10894PolyExtStep::Add(5706, 4133), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10895PolyExtStep::Add(5707, 4134), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10896PolyExtStep::Add(5708, 4135), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10897PolyExtStep::Add(5709, 4136), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10898PolyExtStep::Add(5710, 4137), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10899PolyExtStep::Mul(608, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10900PolyExtStep::Add(5711, 5712), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10901PolyExtStep::Mul(4115, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10902PolyExtStep::Add(5711, 5714), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10903PolyExtStep::Mul(4116, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10904PolyExtStep::Add(5711, 5716), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10905PolyExtStep::Mul(4117, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10906PolyExtStep::Add(5711, 5718), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10907PolyExtStep::Mul(4118, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10908PolyExtStep::Add(5711, 5720), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10909PolyExtStep::Mul(4119, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10910PolyExtStep::Add(5711, 5722), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10911PolyExtStep::Mul(4120, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10912PolyExtStep::Add(5711, 5724), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10913PolyExtStep::Mul(4121, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10914PolyExtStep::Add(5711, 5726), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10915PolyExtStep::Mul(4122, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10916PolyExtStep::Add(5711, 5728), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10917PolyExtStep::Mul(4123, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10918PolyExtStep::Add(5711, 5730), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10919PolyExtStep::Mul(4124, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10920PolyExtStep::Add(5711, 5732), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10921PolyExtStep::Mul(4125, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10922PolyExtStep::Add(5711, 5734), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10923PolyExtStep::Mul(4126, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10924PolyExtStep::Add(5711, 5736), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10925PolyExtStep::Mul(4127, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10926PolyExtStep::Add(5711, 5738), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10927PolyExtStep::Mul(4128, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10928PolyExtStep::Add(5711, 5740), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10929PolyExtStep::Mul(4129, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10930PolyExtStep::Add(5711, 5742), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10931PolyExtStep::Mul(4130, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10932PolyExtStep::Add(5711, 5744), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10933PolyExtStep::Mul(4131, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10934PolyExtStep::Add(5711, 5746), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10935PolyExtStep::Mul(4132, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10936PolyExtStep::Add(5711, 5748), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10937PolyExtStep::Mul(4133, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10938PolyExtStep::Add(5711, 5750), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10939PolyExtStep::Mul(4134, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10940PolyExtStep::Add(5711, 5752), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10941PolyExtStep::Mul(4135, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10942PolyExtStep::Add(5711, 5754), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10943PolyExtStep::Mul(4136, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10944PolyExtStep::Add(5711, 5756), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10945PolyExtStep::Mul(4137, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10946PolyExtStep::Add(5711, 5758), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10947PolyExtStep::Add(5713, 267), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
10948PolyExtStep::Mul(5760, 5760), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10949PolyExtStep::Mul(5761, 5760), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10950PolyExtStep::Sub(5762, 629), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10951PolyExtStep::AndEqz(5159, 5763), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10952PolyExtStep::Mul(629, 629), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10953PolyExtStep::Mul(5764, 5760), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10954PolyExtStep::Sub(5765, 622), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10955PolyExtStep::AndEqz(5160, 5766), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10956PolyExtStep::Add(622, 5715), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10957PolyExtStep::Add(5767, 5717), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10958PolyExtStep::Add(5768, 5719), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10959PolyExtStep::Add(5769, 5721), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10960PolyExtStep::Add(5770, 5723), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10961PolyExtStep::Add(5771, 5725), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10962PolyExtStep::Add(5772, 5727), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10963PolyExtStep::Add(5773, 5729), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10964PolyExtStep::Add(5774, 5731), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10965PolyExtStep::Add(5775, 5733), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10966PolyExtStep::Add(5776, 5735), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10967PolyExtStep::Add(5777, 5737), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10968PolyExtStep::Add(5778, 5739), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10969PolyExtStep::Add(5779, 5741), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10970PolyExtStep::Add(5780, 5743), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10971PolyExtStep::Add(5781, 5745), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10972PolyExtStep::Add(5782, 5747), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10973PolyExtStep::Add(5783, 5749), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10974PolyExtStep::Add(5784, 5751), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10975PolyExtStep::Add(5785, 5753), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10976PolyExtStep::Add(5786, 5755), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10977PolyExtStep::Add(5787, 5757), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10978PolyExtStep::Add(5788, 5759), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10979PolyExtStep::Mul(622, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10980PolyExtStep::Add(5789, 5790), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10981PolyExtStep::Mul(5715, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10982PolyExtStep::Add(5789, 5792), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10983PolyExtStep::Mul(5717, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10984PolyExtStep::Add(5789, 5794), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10985PolyExtStep::Mul(5719, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10986PolyExtStep::Add(5789, 5796), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10987PolyExtStep::Mul(5721, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10988PolyExtStep::Add(5789, 5798), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10989PolyExtStep::Mul(5723, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10990PolyExtStep::Add(5789, 5800), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10991PolyExtStep::Mul(5725, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10992PolyExtStep::Add(5789, 5802), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10993PolyExtStep::Mul(5727, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10994PolyExtStep::Add(5789, 5804), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10995PolyExtStep::Mul(5729, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10996PolyExtStep::Add(5789, 5806), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10997PolyExtStep::Mul(5731, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10998PolyExtStep::Add(5789, 5808), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
10999PolyExtStep::Mul(5733, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11000PolyExtStep::Add(5789, 5810), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11001PolyExtStep::Mul(5735, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11002PolyExtStep::Add(5789, 5812), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11003PolyExtStep::Mul(5737, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11004PolyExtStep::Add(5789, 5814), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11005PolyExtStep::Mul(5739, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11006PolyExtStep::Add(5789, 5816), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11007PolyExtStep::Mul(5741, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11008PolyExtStep::Add(5789, 5818), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11009PolyExtStep::Mul(5743, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11010PolyExtStep::Add(5789, 5820), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11011PolyExtStep::Mul(5745, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11012PolyExtStep::Add(5789, 5822), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11013PolyExtStep::Mul(5747, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11014PolyExtStep::Add(5789, 5824), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11015PolyExtStep::Mul(5749, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11016PolyExtStep::Add(5789, 5826), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11017PolyExtStep::Mul(5751, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11018PolyExtStep::Add(5789, 5828), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11019PolyExtStep::Mul(5753, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11020PolyExtStep::Add(5789, 5830), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11021PolyExtStep::Mul(5755, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11022PolyExtStep::Add(5789, 5832), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11023PolyExtStep::Mul(5757, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11024PolyExtStep::Add(5789, 5834), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11025PolyExtStep::Mul(5759, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11026PolyExtStep::Add(5789, 5836), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11027PolyExtStep::Add(5791, 268), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11028PolyExtStep::Mul(5838, 5838), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11029PolyExtStep::Mul(5839, 5838), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11030PolyExtStep::Sub(5840, 639), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11031PolyExtStep::AndEqz(5161, 5841), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11032PolyExtStep::Mul(639, 639), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11033PolyExtStep::Mul(5842, 5838), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11034PolyExtStep::Sub(5843, 632), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11035PolyExtStep::AndEqz(5162, 5844), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11036PolyExtStep::Add(632, 5793), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11037PolyExtStep::Add(5845, 5795), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11038PolyExtStep::Add(5846, 5797), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11039PolyExtStep::Add(5847, 5799), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11040PolyExtStep::Add(5848, 5801), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11041PolyExtStep::Add(5849, 5803), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11042PolyExtStep::Add(5850, 5805), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11043PolyExtStep::Add(5851, 5807), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11044PolyExtStep::Add(5852, 5809), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11045PolyExtStep::Add(5853, 5811), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11046PolyExtStep::Add(5854, 5813), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11047PolyExtStep::Add(5855, 5815), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11048PolyExtStep::Add(5856, 5817), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11049PolyExtStep::Add(5857, 5819), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11050PolyExtStep::Add(5858, 5821), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11051PolyExtStep::Add(5859, 5823), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11052PolyExtStep::Add(5860, 5825), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11053PolyExtStep::Add(5861, 5827), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11054PolyExtStep::Add(5862, 5829), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11055PolyExtStep::Add(5863, 5831), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11056PolyExtStep::Add(5864, 5833), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11057PolyExtStep::Add(5865, 5835), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11058PolyExtStep::Add(5866, 5837), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11059PolyExtStep::Mul(632, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11060PolyExtStep::Add(5867, 5868), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11061PolyExtStep::Mul(5793, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11062PolyExtStep::Add(5867, 5870), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11063PolyExtStep::Mul(5795, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11064PolyExtStep::Add(5867, 5872), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11065PolyExtStep::Mul(5797, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11066PolyExtStep::Add(5867, 5874), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11067PolyExtStep::Mul(5799, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11068PolyExtStep::Add(5867, 5876), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11069PolyExtStep::Mul(5801, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11070PolyExtStep::Add(5867, 5878), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11071PolyExtStep::Mul(5803, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11072PolyExtStep::Add(5867, 5880), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11073PolyExtStep::Mul(5805, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11074PolyExtStep::Add(5867, 5882), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11075PolyExtStep::Mul(5807, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11076PolyExtStep::Add(5867, 5884), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11077PolyExtStep::Mul(5809, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11078PolyExtStep::Add(5867, 5886), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11079PolyExtStep::Mul(5811, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11080PolyExtStep::Add(5867, 5888), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11081PolyExtStep::Mul(5813, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11082PolyExtStep::Add(5867, 5890), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11083PolyExtStep::Mul(5815, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11084PolyExtStep::Add(5867, 5892), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11085PolyExtStep::Mul(5817, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11086PolyExtStep::Add(5867, 5894), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11087PolyExtStep::Mul(5819, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11088PolyExtStep::Add(5867, 5896), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11089PolyExtStep::Mul(5821, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11090PolyExtStep::Add(5867, 5898), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11091PolyExtStep::Mul(5823, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11092PolyExtStep::Add(5867, 5900), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11093PolyExtStep::Mul(5825, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11094PolyExtStep::Add(5867, 5902), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11095PolyExtStep::Mul(5827, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11096PolyExtStep::Add(5867, 5904), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11097PolyExtStep::Mul(5829, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11098PolyExtStep::Add(5867, 5906), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11099PolyExtStep::Mul(5831, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11100PolyExtStep::Add(5867, 5908), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11101PolyExtStep::Mul(5833, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11102PolyExtStep::Add(5867, 5910), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11103PolyExtStep::Mul(5835, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11104PolyExtStep::Add(5867, 5912), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11105PolyExtStep::Mul(5837, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11106PolyExtStep::Add(5867, 5914), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11107PolyExtStep::Add(5869, 269), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11108PolyExtStep::Mul(5916, 5916), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11109PolyExtStep::Mul(5917, 5916), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11110PolyExtStep::Sub(5918, 649), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11111PolyExtStep::AndEqz(5163, 5919), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11112PolyExtStep::Mul(5377, 5916), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11113PolyExtStep::Sub(5920, 646), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11114PolyExtStep::AndEqz(5164, 5921), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11115PolyExtStep::Add(646, 5871), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11116PolyExtStep::Add(5922, 5873), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11117PolyExtStep::Add(5923, 5875), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11118PolyExtStep::Add(5924, 5877), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11119PolyExtStep::Add(5925, 5879), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11120PolyExtStep::Add(5926, 5881), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11121PolyExtStep::Add(5927, 5883), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11122PolyExtStep::Add(5928, 5885), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11123PolyExtStep::Add(5929, 5887), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11124PolyExtStep::Add(5930, 5889), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11125PolyExtStep::Add(5931, 5891), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11126PolyExtStep::Add(5932, 5893), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11127PolyExtStep::Add(5933, 5895), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11128PolyExtStep::Add(5934, 5897), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11129PolyExtStep::Add(5935, 5899), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11130PolyExtStep::Add(5936, 5901), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11131PolyExtStep::Add(5937, 5903), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11132PolyExtStep::Add(5938, 5905), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11133PolyExtStep::Add(5939, 5907), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11134PolyExtStep::Add(5940, 5909), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11135PolyExtStep::Add(5941, 5911), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11136PolyExtStep::Add(5942, 5913), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11137PolyExtStep::Add(5943, 5915), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11138PolyExtStep::Mul(646, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11139PolyExtStep::Add(5944, 5945), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11140PolyExtStep::Mul(5871, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11141PolyExtStep::Add(5944, 5947), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11142PolyExtStep::Mul(5873, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11143PolyExtStep::Add(5944, 5949), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11144PolyExtStep::Mul(5875, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11145PolyExtStep::Add(5944, 5951), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11146PolyExtStep::Mul(5877, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11147PolyExtStep::Add(5944, 5953), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11148PolyExtStep::Mul(5879, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11149PolyExtStep::Add(5944, 5955), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11150PolyExtStep::Mul(5881, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11151PolyExtStep::Add(5944, 5957), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11152PolyExtStep::Mul(5883, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11153PolyExtStep::Add(5944, 5959), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11154PolyExtStep::Mul(5885, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11155PolyExtStep::Add(5944, 5961), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11156PolyExtStep::Mul(5887, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11157PolyExtStep::Add(5944, 5963), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11158PolyExtStep::Mul(5889, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11159PolyExtStep::Add(5944, 5965), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11160PolyExtStep::Mul(5891, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11161PolyExtStep::Add(5944, 5967), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11162PolyExtStep::Mul(5893, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11163PolyExtStep::Add(5944, 5969), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11164PolyExtStep::Mul(5895, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11165PolyExtStep::Add(5944, 5971), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11166PolyExtStep::Mul(5897, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11167PolyExtStep::Add(5944, 5973), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11168PolyExtStep::Mul(5899, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11169PolyExtStep::Add(5944, 5975), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11170PolyExtStep::Mul(5901, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11171PolyExtStep::Add(5944, 5977), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11172PolyExtStep::Mul(5903, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11173PolyExtStep::Add(5944, 5979), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11174PolyExtStep::Mul(5905, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11175PolyExtStep::Add(5944, 5981), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11176PolyExtStep::Mul(5907, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11177PolyExtStep::Add(5944, 5983), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11178PolyExtStep::Mul(5909, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11179PolyExtStep::Add(5944, 5985), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11180PolyExtStep::Mul(5911, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11181PolyExtStep::Add(5944, 5987), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11182PolyExtStep::Mul(5913, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11183PolyExtStep::Add(5944, 5989), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11184PolyExtStep::Mul(5915, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11185PolyExtStep::Add(5944, 5991), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11186PolyExtStep::Add(5946, 270), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11187PolyExtStep::Mul(5993, 5993), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11188PolyExtStep::Mul(5994, 5993), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11189PolyExtStep::Sub(5995, 659), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11190PolyExtStep::AndEqz(5165, 5996), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11191PolyExtStep::Mul(5384, 5993), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11192PolyExtStep::Sub(5997, 652), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11193PolyExtStep::AndEqz(5166, 5998), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11194PolyExtStep::Add(652, 5948), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11195PolyExtStep::Add(5999, 5950), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11196PolyExtStep::Add(6000, 5952), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11197PolyExtStep::Add(6001, 5954), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11198PolyExtStep::Add(6002, 5956), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11199PolyExtStep::Add(6003, 5958), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11200PolyExtStep::Add(6004, 5960), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11201PolyExtStep::Add(6005, 5962), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11202PolyExtStep::Add(6006, 5964), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11203PolyExtStep::Add(6007, 5966), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11204PolyExtStep::Add(6008, 5968), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11205PolyExtStep::Add(6009, 5970), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11206PolyExtStep::Add(6010, 5972), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11207PolyExtStep::Add(6011, 5974), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11208PolyExtStep::Add(6012, 5976), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11209PolyExtStep::Add(6013, 5978), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11210PolyExtStep::Add(6014, 5980), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11211PolyExtStep::Add(6015, 5982), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11212PolyExtStep::Add(6016, 5984), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11213PolyExtStep::Add(6017, 5986), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11214PolyExtStep::Add(6018, 5988), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11215PolyExtStep::Add(6019, 5990), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11216PolyExtStep::Add(6020, 5992), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11217PolyExtStep::Mul(652, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11218PolyExtStep::Add(6021, 6022), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11219PolyExtStep::Mul(5948, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11220PolyExtStep::Add(6021, 6024), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11221PolyExtStep::Mul(5950, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11222PolyExtStep::Add(6021, 6026), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11223PolyExtStep::Mul(5952, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11224PolyExtStep::Add(6021, 6028), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11225PolyExtStep::Mul(5954, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11226PolyExtStep::Add(6021, 6030), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11227PolyExtStep::Mul(5956, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11228PolyExtStep::Add(6021, 6032), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11229PolyExtStep::Mul(5958, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11230PolyExtStep::Add(6021, 6034), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11231PolyExtStep::Mul(5960, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11232PolyExtStep::Add(6021, 6036), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11233PolyExtStep::Mul(5962, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11234PolyExtStep::Add(6021, 6038), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11235PolyExtStep::Mul(5964, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11236PolyExtStep::Add(6021, 6040), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11237PolyExtStep::Mul(5966, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11238PolyExtStep::Add(6021, 6042), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11239PolyExtStep::Mul(5968, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11240PolyExtStep::Add(6021, 6044), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11241PolyExtStep::Mul(5970, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11242PolyExtStep::Add(6021, 6046), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11243PolyExtStep::Mul(5972, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11244PolyExtStep::Add(6021, 6048), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11245PolyExtStep::Mul(5974, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11246PolyExtStep::Add(6021, 6050), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11247PolyExtStep::Mul(5976, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11248PolyExtStep::Add(6021, 6052), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11249PolyExtStep::Mul(5978, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11250PolyExtStep::Add(6021, 6054), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11251PolyExtStep::Mul(5980, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11252PolyExtStep::Add(6021, 6056), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11253PolyExtStep::Mul(5982, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11254PolyExtStep::Add(6021, 6058), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11255PolyExtStep::Mul(5984, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11256PolyExtStep::Add(6021, 6060), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11257PolyExtStep::Mul(5986, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11258PolyExtStep::Add(6021, 6062), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11259PolyExtStep::Mul(5988, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11260PolyExtStep::Add(6021, 6064), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11261PolyExtStep::Mul(5990, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11262PolyExtStep::Add(6021, 6066), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11263PolyExtStep::Mul(5992, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11264PolyExtStep::Add(6021, 6068), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11265PolyExtStep::Add(6023, 271), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11266PolyExtStep::Mul(6070, 6070), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11267PolyExtStep::Mul(6071, 6070), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11268PolyExtStep::Sub(6072, 673), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11269PolyExtStep::AndEqz(5167, 6073), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11270PolyExtStep::Mul(5391, 6070), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11271PolyExtStep::Sub(6074, 666), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11272PolyExtStep::AndEqz(5168, 6075), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11273PolyExtStep::Add(666, 6025), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11274PolyExtStep::Add(6076, 6027), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11275PolyExtStep::Add(6077, 6029), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11276PolyExtStep::Add(6078, 6031), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11277PolyExtStep::Add(6079, 6033), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11278PolyExtStep::Add(6080, 6035), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11279PolyExtStep::Add(6081, 6037), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11280PolyExtStep::Add(6082, 6039), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11281PolyExtStep::Add(6083, 6041), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11282PolyExtStep::Add(6084, 6043), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11283PolyExtStep::Add(6085, 6045), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11284PolyExtStep::Add(6086, 6047), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11285PolyExtStep::Add(6087, 6049), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11286PolyExtStep::Add(6088, 6051), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11287PolyExtStep::Add(6089, 6053), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11288PolyExtStep::Add(6090, 6055), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11289PolyExtStep::Add(6091, 6057), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11290PolyExtStep::Add(6092, 6059), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11291PolyExtStep::Add(6093, 6061), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11292PolyExtStep::Add(6094, 6063), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11293PolyExtStep::Add(6095, 6065), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11294PolyExtStep::Add(6096, 6067), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11295PolyExtStep::Add(6097, 6069), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11296PolyExtStep::Mul(666, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11297PolyExtStep::Add(6098, 6099), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11298PolyExtStep::Mul(6025, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11299PolyExtStep::Add(6098, 6101), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11300PolyExtStep::Mul(6027, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11301PolyExtStep::Add(6098, 6103), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11302PolyExtStep::Mul(6029, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11303PolyExtStep::Add(6098, 6105), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11304PolyExtStep::Mul(6031, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11305PolyExtStep::Add(6098, 6107), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11306PolyExtStep::Mul(6033, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11307PolyExtStep::Add(6098, 6109), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11308PolyExtStep::Mul(6035, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11309PolyExtStep::Add(6098, 6111), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11310PolyExtStep::Mul(6037, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11311PolyExtStep::Add(6098, 6113), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11312PolyExtStep::Mul(6039, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11313PolyExtStep::Add(6098, 6115), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11314PolyExtStep::Mul(6041, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11315PolyExtStep::Add(6098, 6117), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11316PolyExtStep::Mul(6043, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11317PolyExtStep::Add(6098, 6119), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11318PolyExtStep::Mul(6045, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11319PolyExtStep::Add(6098, 6121), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11320PolyExtStep::Mul(6047, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11321PolyExtStep::Add(6098, 6123), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11322PolyExtStep::Mul(6049, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11323PolyExtStep::Add(6098, 6125), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11324PolyExtStep::Mul(6051, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11325PolyExtStep::Add(6098, 6127), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11326PolyExtStep::Mul(6053, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11327PolyExtStep::Add(6098, 6129), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11328PolyExtStep::Mul(6055, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11329PolyExtStep::Add(6098, 6131), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11330PolyExtStep::Mul(6057, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11331PolyExtStep::Add(6098, 6133), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11332PolyExtStep::Mul(6059, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11333PolyExtStep::Add(6098, 6135), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11334PolyExtStep::Mul(6061, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11335PolyExtStep::Add(6098, 6137), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11336PolyExtStep::Mul(6063, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11337PolyExtStep::Add(6098, 6139), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11338PolyExtStep::Mul(6065, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11339PolyExtStep::Add(6098, 6141), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11340PolyExtStep::Mul(6067, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11341PolyExtStep::Add(6098, 6143), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11342PolyExtStep::Mul(6069, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11343PolyExtStep::Add(6098, 6145), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11344PolyExtStep::Add(6100, 272), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11345PolyExtStep::Mul(6147, 6147), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11346PolyExtStep::Mul(6148, 6147), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11347PolyExtStep::Sub(6149, 544), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11348PolyExtStep::AndEqz(5169, 6150), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11349PolyExtStep::Mul(5398, 6147), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11350PolyExtStep::Sub(6151, 676), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11351PolyExtStep::AndEqz(5170, 6152), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11352PolyExtStep::Add(676, 6102), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11353PolyExtStep::Add(6153, 6104), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11354PolyExtStep::Add(6154, 6106), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11355PolyExtStep::Add(6155, 6108), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11356PolyExtStep::Add(6156, 6110), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11357PolyExtStep::Add(6157, 6112), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11358PolyExtStep::Add(6158, 6114), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11359PolyExtStep::Add(6159, 6116), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11360PolyExtStep::Add(6160, 6118), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11361PolyExtStep::Add(6161, 6120), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11362PolyExtStep::Add(6162, 6122), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11363PolyExtStep::Add(6163, 6124), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11364PolyExtStep::Add(6164, 6126), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11365PolyExtStep::Add(6165, 6128), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11366PolyExtStep::Add(6166, 6130), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11367PolyExtStep::Add(6167, 6132), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11368PolyExtStep::Add(6168, 6134), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11369PolyExtStep::Add(6169, 6136), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11370PolyExtStep::Add(6170, 6138), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11371PolyExtStep::Add(6171, 6140), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11372PolyExtStep::Add(6172, 6142), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11373PolyExtStep::Add(6173, 6144), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11374PolyExtStep::Add(6174, 6146), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11375PolyExtStep::Mul(676, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11376PolyExtStep::Add(6175, 6176), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11377PolyExtStep::Mul(6102, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11378PolyExtStep::Add(6175, 6178), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11379PolyExtStep::Mul(6104, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11380PolyExtStep::Add(6175, 6180), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11381PolyExtStep::Mul(6106, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11382PolyExtStep::Add(6175, 6182), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11383PolyExtStep::Mul(6108, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11384PolyExtStep::Add(6175, 6184), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11385PolyExtStep::Mul(6110, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11386PolyExtStep::Add(6175, 6186), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11387PolyExtStep::Mul(6112, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11388PolyExtStep::Add(6175, 6188), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11389PolyExtStep::Mul(6114, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11390PolyExtStep::Add(6175, 6190), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11391PolyExtStep::Mul(6116, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11392PolyExtStep::Add(6175, 6192), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11393PolyExtStep::Mul(6118, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11394PolyExtStep::Add(6175, 6194), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11395PolyExtStep::Mul(6120, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11396PolyExtStep::Add(6175, 6196), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11397PolyExtStep::Mul(6122, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11398PolyExtStep::Add(6175, 6198), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11399PolyExtStep::Mul(6124, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11400PolyExtStep::Add(6175, 6200), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11401PolyExtStep::Mul(6126, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11402PolyExtStep::Add(6175, 6202), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11403PolyExtStep::Mul(6128, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11404PolyExtStep::Add(6175, 6204), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11405PolyExtStep::Mul(6130, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11406PolyExtStep::Add(6175, 6206), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11407PolyExtStep::Mul(6132, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11408PolyExtStep::Add(6175, 6208), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11409PolyExtStep::Mul(6134, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11410PolyExtStep::Add(6175, 6210), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11411PolyExtStep::Mul(6136, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11412PolyExtStep::Add(6175, 6212), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11413PolyExtStep::Mul(6138, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11414PolyExtStep::Add(6175, 6214), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11415PolyExtStep::Mul(6140, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11416PolyExtStep::Add(6175, 6216), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11417PolyExtStep::Mul(6142, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11418PolyExtStep::Add(6175, 6218), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11419PolyExtStep::Mul(6144, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11420PolyExtStep::Add(6175, 6220), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11421PolyExtStep::Mul(6146, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11422PolyExtStep::Add(6175, 6222), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11423PolyExtStep::Add(6177, 273), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11424PolyExtStep::Mul(6224, 6224), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11425PolyExtStep::Mul(6225, 6224), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11426PolyExtStep::Sub(6226, 552), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11427PolyExtStep::AndEqz(5171, 6227), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11428PolyExtStep::Mul(5405, 6224), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11429PolyExtStep::Sub(6228, 551), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11430PolyExtStep::AndEqz(5172, 6229), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11431PolyExtStep::Add(551, 6179), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11432PolyExtStep::Add(6230, 6181), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11433PolyExtStep::Add(6231, 6183), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11434PolyExtStep::Add(6232, 6185), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11435PolyExtStep::Add(6233, 6187), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11436PolyExtStep::Add(6234, 6189), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11437PolyExtStep::Add(6235, 6191), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11438PolyExtStep::Add(6236, 6193), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11439PolyExtStep::Add(6237, 6195), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11440PolyExtStep::Add(6238, 6197), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11441PolyExtStep::Add(6239, 6199), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11442PolyExtStep::Add(6240, 6201), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11443PolyExtStep::Add(6241, 6203), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11444PolyExtStep::Add(6242, 6205), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11445PolyExtStep::Add(6243, 6207), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11446PolyExtStep::Add(6244, 6209), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11447PolyExtStep::Add(6245, 6211), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11448PolyExtStep::Add(6246, 6213), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11449PolyExtStep::Add(6247, 6215), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11450PolyExtStep::Add(6248, 6217), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11451PolyExtStep::Add(6249, 6219), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11452PolyExtStep::Add(6250, 6221), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11453PolyExtStep::Add(6251, 6223), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11454PolyExtStep::Mul(551, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11455PolyExtStep::Add(6252, 6253), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11456PolyExtStep::Mul(6179, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11457PolyExtStep::Add(6252, 6255), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11458PolyExtStep::Mul(6181, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11459PolyExtStep::Add(6252, 6257), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11460PolyExtStep::Mul(6183, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11461PolyExtStep::Add(6252, 6259), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11462PolyExtStep::Mul(6185, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11463PolyExtStep::Add(6252, 6261), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11464PolyExtStep::Mul(6187, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11465PolyExtStep::Add(6252, 6263), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11466PolyExtStep::Mul(6189, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11467PolyExtStep::Add(6252, 6265), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11468PolyExtStep::Mul(6191, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11469PolyExtStep::Add(6252, 6267), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11470PolyExtStep::Mul(6193, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11471PolyExtStep::Add(6252, 6269), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11472PolyExtStep::Mul(6195, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11473PolyExtStep::Add(6252, 6271), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11474PolyExtStep::Mul(6197, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11475PolyExtStep::Add(6252, 6273), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11476PolyExtStep::Mul(6199, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11477PolyExtStep::Add(6252, 6275), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11478PolyExtStep::Mul(6201, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11479PolyExtStep::Add(6252, 6277), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11480PolyExtStep::Mul(6203, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11481PolyExtStep::Add(6252, 6279), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11482PolyExtStep::Mul(6205, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11483PolyExtStep::Add(6252, 6281), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11484PolyExtStep::Mul(6207, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11485PolyExtStep::Add(6252, 6283), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11486PolyExtStep::Mul(6209, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11487PolyExtStep::Add(6252, 6285), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11488PolyExtStep::Mul(6211, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11489PolyExtStep::Add(6252, 6287), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11490PolyExtStep::Mul(6213, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11491PolyExtStep::Add(6252, 6289), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11492PolyExtStep::Mul(6215, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11493PolyExtStep::Add(6252, 6291), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11494PolyExtStep::Mul(6217, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11495PolyExtStep::Add(6252, 6293), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11496PolyExtStep::Mul(6219, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11497PolyExtStep::Add(6252, 6295), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11498PolyExtStep::Mul(6221, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11499PolyExtStep::Add(6252, 6297), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11500PolyExtStep::Mul(6223, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11501PolyExtStep::Add(6252, 6299), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11502PolyExtStep::Add(6254, 274), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11503PolyExtStep::Mul(6301, 6301), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11504PolyExtStep::Mul(6302, 6301), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11505PolyExtStep::Sub(6303, 556), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11506PolyExtStep::AndEqz(5173, 6304), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11507PolyExtStep::Mul(5412, 6301), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11508PolyExtStep::Sub(6305, 555), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11509PolyExtStep::AndEqz(5174, 6306), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11510PolyExtStep::Add(555, 6256), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11511PolyExtStep::Add(6307, 6258), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11512PolyExtStep::Add(6308, 6260), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11513PolyExtStep::Add(6309, 6262), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11514PolyExtStep::Add(6310, 6264), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11515PolyExtStep::Add(6311, 6266), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11516PolyExtStep::Add(6312, 6268), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11517PolyExtStep::Add(6313, 6270), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11518PolyExtStep::Add(6314, 6272), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11519PolyExtStep::Add(6315, 6274), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11520PolyExtStep::Add(6316, 6276), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11521PolyExtStep::Add(6317, 6278), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11522PolyExtStep::Add(6318, 6280), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11523PolyExtStep::Add(6319, 6282), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11524PolyExtStep::Add(6320, 6284), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11525PolyExtStep::Add(6321, 6286), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11526PolyExtStep::Add(6322, 6288), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11527PolyExtStep::Add(6323, 6290), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11528PolyExtStep::Add(6324, 6292), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11529PolyExtStep::Add(6325, 6294), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11530PolyExtStep::Add(6326, 6296), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11531PolyExtStep::Add(6327, 6298), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11532PolyExtStep::Add(6328, 6300), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11533PolyExtStep::Mul(555, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11534PolyExtStep::Add(6329, 6330), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11535PolyExtStep::Mul(6256, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11536PolyExtStep::Add(6329, 6332), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11537PolyExtStep::Mul(6258, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11538PolyExtStep::Add(6329, 6334), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11539PolyExtStep::Mul(6260, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11540PolyExtStep::Add(6329, 6336), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11541PolyExtStep::Mul(6262, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11542PolyExtStep::Add(6329, 6338), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11543PolyExtStep::Mul(6264, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11544PolyExtStep::Add(6329, 6340), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11545PolyExtStep::Mul(6266, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11546PolyExtStep::Add(6329, 6342), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11547PolyExtStep::Mul(6268, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11548PolyExtStep::Add(6329, 6344), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11549PolyExtStep::Mul(6270, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11550PolyExtStep::Add(6329, 6346), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11551PolyExtStep::Mul(6272, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11552PolyExtStep::Add(6329, 6348), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11553PolyExtStep::Mul(6274, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11554PolyExtStep::Add(6329, 6350), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11555PolyExtStep::Mul(6276, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11556PolyExtStep::Add(6329, 6352), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11557PolyExtStep::Mul(6278, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11558PolyExtStep::Add(6329, 6354), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11559PolyExtStep::Mul(6280, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11560PolyExtStep::Add(6329, 6356), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11561PolyExtStep::Mul(6282, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11562PolyExtStep::Add(6329, 6358), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11563PolyExtStep::Mul(6284, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11564PolyExtStep::Add(6329, 6360), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11565PolyExtStep::Mul(6286, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11566PolyExtStep::Add(6329, 6362), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11567PolyExtStep::Mul(6288, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11568PolyExtStep::Add(6329, 6364), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11569PolyExtStep::Mul(6290, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11570PolyExtStep::Add(6329, 6366), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11571PolyExtStep::Mul(6292, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11572PolyExtStep::Add(6329, 6368), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11573PolyExtStep::Mul(6294, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11574PolyExtStep::Add(6329, 6370), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11575PolyExtStep::Mul(6296, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11576PolyExtStep::Add(6329, 6372), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11577PolyExtStep::Mul(6298, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11578PolyExtStep::Add(6329, 6374), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11579PolyExtStep::Mul(6300, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11580PolyExtStep::Add(6329, 6376), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11581PolyExtStep::Add(6331, 275), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11582PolyExtStep::Mul(6378, 6378), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11583PolyExtStep::Mul(6379, 6378), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11584PolyExtStep::Sub(6380, 564), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11585PolyExtStep::AndEqz(5175, 6381), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11586PolyExtStep::Mul(5419, 6378), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11587PolyExtStep::Sub(6382, 563), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11588PolyExtStep::AndEqz(5176, 6383), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11589PolyExtStep::Add(563, 6333), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11590PolyExtStep::Add(6384, 6335), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11591PolyExtStep::Add(6385, 6337), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11592PolyExtStep::Add(6386, 6339), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11593PolyExtStep::Add(6387, 6341), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11594PolyExtStep::Add(6388, 6343), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11595PolyExtStep::Add(6389, 6345), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11596PolyExtStep::Add(6390, 6347), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11597PolyExtStep::Add(6391, 6349), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11598PolyExtStep::Add(6392, 6351), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11599PolyExtStep::Add(6393, 6353), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11600PolyExtStep::Add(6394, 6355), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11601PolyExtStep::Add(6395, 6357), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11602PolyExtStep::Add(6396, 6359), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11603PolyExtStep::Add(6397, 6361), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11604PolyExtStep::Add(6398, 6363), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11605PolyExtStep::Add(6399, 6365), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11606PolyExtStep::Add(6400, 6367), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11607PolyExtStep::Add(6401, 6369), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11608PolyExtStep::Add(6402, 6371), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11609PolyExtStep::Add(6403, 6373), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11610PolyExtStep::Add(6404, 6375), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11611PolyExtStep::Add(6405, 6377), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11612PolyExtStep::Mul(563, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11613PolyExtStep::Add(6406, 6407), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11614PolyExtStep::Mul(6333, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11615PolyExtStep::Add(6406, 6409), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11616PolyExtStep::Mul(6335, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11617PolyExtStep::Add(6406, 6411), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11618PolyExtStep::Mul(6337, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11619PolyExtStep::Add(6406, 6413), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11620PolyExtStep::Mul(6339, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11621PolyExtStep::Add(6406, 6415), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11622PolyExtStep::Mul(6341, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11623PolyExtStep::Add(6406, 6417), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11624PolyExtStep::Mul(6343, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11625PolyExtStep::Add(6406, 6419), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11626PolyExtStep::Mul(6345, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11627PolyExtStep::Add(6406, 6421), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11628PolyExtStep::Mul(6347, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11629PolyExtStep::Add(6406, 6423), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11630PolyExtStep::Mul(6349, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11631PolyExtStep::Add(6406, 6425), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11632PolyExtStep::Mul(6351, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11633PolyExtStep::Add(6406, 6427), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11634PolyExtStep::Mul(6353, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11635PolyExtStep::Add(6406, 6429), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11636PolyExtStep::Mul(6355, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11637PolyExtStep::Add(6406, 6431), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11638PolyExtStep::Mul(6357, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11639PolyExtStep::Add(6406, 6433), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11640PolyExtStep::Mul(6359, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11641PolyExtStep::Add(6406, 6435), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11642PolyExtStep::Mul(6361, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11643PolyExtStep::Add(6406, 6437), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11644PolyExtStep::Mul(6363, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11645PolyExtStep::Add(6406, 6439), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11646PolyExtStep::Mul(6365, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11647PolyExtStep::Add(6406, 6441), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11648PolyExtStep::Mul(6367, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11649PolyExtStep::Add(6406, 6443), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11650PolyExtStep::Mul(6369, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11651PolyExtStep::Add(6406, 6445), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11652PolyExtStep::Mul(6371, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11653PolyExtStep::Add(6406, 6447), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11654PolyExtStep::Mul(6373, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11655PolyExtStep::Add(6406, 6449), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11656PolyExtStep::Mul(6375, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11657PolyExtStep::Add(6406, 6451), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11658PolyExtStep::Mul(6377, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11659PolyExtStep::Add(6406, 6453), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11660PolyExtStep::Add(6408, 276), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11661PolyExtStep::Mul(6455, 6455), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11662PolyExtStep::Mul(6456, 6455), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11663PolyExtStep::Sub(6457, 570), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11664PolyExtStep::AndEqz(5177, 6458), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11665PolyExtStep::Mul(5426, 6455), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11666PolyExtStep::Sub(6459, 571), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11667PolyExtStep::AndEqz(5178, 6460), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11668PolyExtStep::Add(571, 6410), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11669PolyExtStep::Add(6461, 6412), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11670PolyExtStep::Add(6462, 6414), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11671PolyExtStep::Add(6463, 6416), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11672PolyExtStep::Add(6464, 6418), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11673PolyExtStep::Add(6465, 6420), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11674PolyExtStep::Add(6466, 6422), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11675PolyExtStep::Add(6467, 6424), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11676PolyExtStep::Add(6468, 6426), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11677PolyExtStep::Add(6469, 6428), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11678PolyExtStep::Add(6470, 6430), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11679PolyExtStep::Add(6471, 6432), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11680PolyExtStep::Add(6472, 6434), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11681PolyExtStep::Add(6473, 6436), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11682PolyExtStep::Add(6474, 6438), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11683PolyExtStep::Add(6475, 6440), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11684PolyExtStep::Add(6476, 6442), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11685PolyExtStep::Add(6477, 6444), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11686PolyExtStep::Add(6478, 6446), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11687PolyExtStep::Add(6479, 6448), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11688PolyExtStep::Add(6480, 6450), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11689PolyExtStep::Add(6481, 6452), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11690PolyExtStep::Add(6482, 6454), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11691PolyExtStep::Mul(571, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11692PolyExtStep::Add(6483, 6484), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11693PolyExtStep::Mul(6410, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11694PolyExtStep::Add(6483, 6486), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11695PolyExtStep::Mul(6412, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11696PolyExtStep::Add(6483, 6488), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11697PolyExtStep::Mul(6414, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11698PolyExtStep::Add(6483, 6490), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11699PolyExtStep::Mul(6416, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11700PolyExtStep::Add(6483, 6492), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11701PolyExtStep::Mul(6418, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11702PolyExtStep::Add(6483, 6494), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11703PolyExtStep::Mul(6420, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11704PolyExtStep::Add(6483, 6496), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11705PolyExtStep::Mul(6422, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11706PolyExtStep::Add(6483, 6498), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11707PolyExtStep::Mul(6424, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11708PolyExtStep::Add(6483, 6500), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11709PolyExtStep::Mul(6426, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11710PolyExtStep::Add(6483, 6502), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11711PolyExtStep::Mul(6428, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11712PolyExtStep::Add(6483, 6504), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11713PolyExtStep::Mul(6430, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11714PolyExtStep::Add(6483, 6506), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11715PolyExtStep::Mul(6432, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11716PolyExtStep::Add(6483, 6508), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11717PolyExtStep::Mul(6434, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11718PolyExtStep::Add(6483, 6510), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11719PolyExtStep::Mul(6436, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11720PolyExtStep::Add(6483, 6512), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11721PolyExtStep::Mul(6438, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11722PolyExtStep::Add(6483, 6514), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11723PolyExtStep::Mul(6440, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11724PolyExtStep::Add(6483, 6516), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11725PolyExtStep::Mul(6442, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11726PolyExtStep::Add(6483, 6518), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11727PolyExtStep::Mul(6444, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11728PolyExtStep::Add(6483, 6520), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11729PolyExtStep::Mul(6446, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11730PolyExtStep::Add(6483, 6522), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11731PolyExtStep::Mul(6448, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11732PolyExtStep::Add(6483, 6524), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11733PolyExtStep::Mul(6450, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11734PolyExtStep::Add(6483, 6526), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11735PolyExtStep::Mul(6452, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11736PolyExtStep::Add(6483, 6528), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11737PolyExtStep::Mul(6454, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11738PolyExtStep::Add(6483, 6530), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11739PolyExtStep::Add(6485, 277), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11740PolyExtStep::Mul(6532, 6532), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11741PolyExtStep::Mul(6533, 6532), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11742PolyExtStep::Sub(6534, 573), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11743PolyExtStep::AndEqz(5179, 6535), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11744PolyExtStep::Mul(5433, 6532), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11745PolyExtStep::Sub(6536, 572), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11746PolyExtStep::AndEqz(5180, 6537), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11747PolyExtStep::Add(572, 6487), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11748PolyExtStep::Add(6538, 6489), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11749PolyExtStep::Add(6539, 6491), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11750PolyExtStep::Add(6540, 6493), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11751PolyExtStep::Add(6541, 6495), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11752PolyExtStep::Add(6542, 6497), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11753PolyExtStep::Add(6543, 6499), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11754PolyExtStep::Add(6544, 6501), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11755PolyExtStep::Add(6545, 6503), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11756PolyExtStep::Add(6546, 6505), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11757PolyExtStep::Add(6547, 6507), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11758PolyExtStep::Add(6548, 6509), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11759PolyExtStep::Add(6549, 6511), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11760PolyExtStep::Add(6550, 6513), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11761PolyExtStep::Add(6551, 6515), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11762PolyExtStep::Add(6552, 6517), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11763PolyExtStep::Add(6553, 6519), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11764PolyExtStep::Add(6554, 6521), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11765PolyExtStep::Add(6555, 6523), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11766PolyExtStep::Add(6556, 6525), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11767PolyExtStep::Add(6557, 6527), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11768PolyExtStep::Add(6558, 6529), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11769PolyExtStep::Add(6559, 6531), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11770PolyExtStep::Mul(572, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11771PolyExtStep::Add(6560, 6561), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11772PolyExtStep::Mul(6487, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11773PolyExtStep::Add(6560, 6563), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11774PolyExtStep::Mul(6489, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11775PolyExtStep::Add(6560, 6565), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11776PolyExtStep::Mul(6491, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11777PolyExtStep::Add(6560, 6567), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11778PolyExtStep::Mul(6493, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11779PolyExtStep::Add(6560, 6569), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11780PolyExtStep::Mul(6495, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11781PolyExtStep::Add(6560, 6571), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11782PolyExtStep::Mul(6497, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11783PolyExtStep::Add(6560, 6573), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11784PolyExtStep::Mul(6499, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11785PolyExtStep::Add(6560, 6575), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11786PolyExtStep::Mul(6501, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11787PolyExtStep::Add(6560, 6577), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11788PolyExtStep::Mul(6503, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11789PolyExtStep::Add(6560, 6579), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11790PolyExtStep::Mul(6505, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11791PolyExtStep::Add(6560, 6581), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11792PolyExtStep::Mul(6507, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11793PolyExtStep::Add(6560, 6583), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11794PolyExtStep::Mul(6509, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11795PolyExtStep::Add(6560, 6585), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11796PolyExtStep::Mul(6511, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11797PolyExtStep::Add(6560, 6587), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11798PolyExtStep::Mul(6513, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11799PolyExtStep::Add(6560, 6589), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11800PolyExtStep::Mul(6515, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11801PolyExtStep::Add(6560, 6591), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11802PolyExtStep::Mul(6517, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11803PolyExtStep::Add(6560, 6593), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11804PolyExtStep::Mul(6519, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11805PolyExtStep::Add(6560, 6595), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11806PolyExtStep::Mul(6521, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11807PolyExtStep::Add(6560, 6597), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11808PolyExtStep::Mul(6523, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11809PolyExtStep::Add(6560, 6599), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11810PolyExtStep::Mul(6525, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11811PolyExtStep::Add(6560, 6601), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11812PolyExtStep::Mul(6527, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11813PolyExtStep::Add(6560, 6603), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11814PolyExtStep::Mul(6529, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11815PolyExtStep::Add(6560, 6605), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11816PolyExtStep::Mul(6531, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11817PolyExtStep::Add(6560, 6607), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11818PolyExtStep::Add(6562, 278), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11819PolyExtStep::Mul(6609, 6609), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11820PolyExtStep::Mul(6610, 6609), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11821PolyExtStep::Sub(6611, 575), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11822PolyExtStep::AndEqz(5181, 6612), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11823PolyExtStep::Mul(5440, 6609), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11824PolyExtStep::Sub(6613, 574), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11825PolyExtStep::AndEqz(5182, 6614), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11826PolyExtStep::Add(574, 6564), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11827PolyExtStep::Add(6615, 6566), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11828PolyExtStep::Add(6616, 6568), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11829PolyExtStep::Add(6617, 6570), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11830PolyExtStep::Add(6618, 6572), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11831PolyExtStep::Add(6619, 6574), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11832PolyExtStep::Add(6620, 6576), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11833PolyExtStep::Add(6621, 6578), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11834PolyExtStep::Add(6622, 6580), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11835PolyExtStep::Add(6623, 6582), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11836PolyExtStep::Add(6624, 6584), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11837PolyExtStep::Add(6625, 6586), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11838PolyExtStep::Add(6626, 6588), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11839PolyExtStep::Add(6627, 6590), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11840PolyExtStep::Add(6628, 6592), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11841PolyExtStep::Add(6629, 6594), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11842PolyExtStep::Add(6630, 6596), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11843PolyExtStep::Add(6631, 6598), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11844PolyExtStep::Add(6632, 6600), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11845PolyExtStep::Add(6633, 6602), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11846PolyExtStep::Add(6634, 6604), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11847PolyExtStep::Add(6635, 6606), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11848PolyExtStep::Add(6636, 6608), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11849PolyExtStep::Mul(574, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11850PolyExtStep::Add(6637, 6638), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11851PolyExtStep::Mul(6564, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11852PolyExtStep::Add(6637, 6640), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11853PolyExtStep::Mul(6566, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11854PolyExtStep::Add(6637, 6642), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11855PolyExtStep::Mul(6568, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11856PolyExtStep::Add(6637, 6644), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11857PolyExtStep::Mul(6570, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11858PolyExtStep::Add(6637, 6646), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11859PolyExtStep::Mul(6572, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11860PolyExtStep::Add(6637, 6648), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11861PolyExtStep::Mul(6574, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11862PolyExtStep::Add(6637, 6650), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11863PolyExtStep::Mul(6576, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11864PolyExtStep::Add(6637, 6652), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11865PolyExtStep::Mul(6578, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11866PolyExtStep::Add(6637, 6654), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11867PolyExtStep::Mul(6580, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11868PolyExtStep::Add(6637, 6656), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11869PolyExtStep::Mul(6582, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11870PolyExtStep::Add(6637, 6658), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11871PolyExtStep::Mul(6584, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11872PolyExtStep::Add(6637, 6660), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11873PolyExtStep::Mul(6586, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11874PolyExtStep::Add(6637, 6662), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11875PolyExtStep::Mul(6588, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11876PolyExtStep::Add(6637, 6664), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11877PolyExtStep::Mul(6590, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11878PolyExtStep::Add(6637, 6666), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11879PolyExtStep::Mul(6592, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11880PolyExtStep::Add(6637, 6668), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11881PolyExtStep::Mul(6594, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11882PolyExtStep::Add(6637, 6670), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11883PolyExtStep::Mul(6596, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11884PolyExtStep::Add(6637, 6672), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11885PolyExtStep::Mul(6598, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11886PolyExtStep::Add(6637, 6674), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11887PolyExtStep::Mul(6600, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11888PolyExtStep::Add(6637, 6676), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11889PolyExtStep::Mul(6602, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11890PolyExtStep::Add(6637, 6678), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11891PolyExtStep::Mul(6604, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11892PolyExtStep::Add(6637, 6680), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11893PolyExtStep::Mul(6606, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11894PolyExtStep::Add(6637, 6682), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11895PolyExtStep::Mul(6608, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11896PolyExtStep::Add(6637, 6684), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11897PolyExtStep::Add(6639, 279), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11898PolyExtStep::Mul(6686, 6686), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11899PolyExtStep::Mul(6687, 6686), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11900PolyExtStep::Sub(6688, 577), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11901PolyExtStep::AndEqz(5183, 6689), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11902PolyExtStep::Mul(5447, 6686), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11903PolyExtStep::Sub(6690, 576), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11904PolyExtStep::AndEqz(5184, 6691), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11905PolyExtStep::Add(576, 6641), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11906PolyExtStep::Add(6692, 6643), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11907PolyExtStep::Add(6693, 6645), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11908PolyExtStep::Add(6694, 6647), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11909PolyExtStep::Add(6695, 6649), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11910PolyExtStep::Add(6696, 6651), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11911PolyExtStep::Add(6697, 6653), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11912PolyExtStep::Add(6698, 6655), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11913PolyExtStep::Add(6699, 6657), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11914PolyExtStep::Add(6700, 6659), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11915PolyExtStep::Add(6701, 6661), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11916PolyExtStep::Add(6702, 6663), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11917PolyExtStep::Add(6703, 6665), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11918PolyExtStep::Add(6704, 6667), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11919PolyExtStep::Add(6705, 6669), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11920PolyExtStep::Add(6706, 6671), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11921PolyExtStep::Add(6707, 6673), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11922PolyExtStep::Add(6708, 6675), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11923PolyExtStep::Add(6709, 6677), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11924PolyExtStep::Add(6710, 6679), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11925PolyExtStep::Add(6711, 6681), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11926PolyExtStep::Add(6712, 6683), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11927PolyExtStep::Add(6713, 6685), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11928PolyExtStep::Mul(576, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11929PolyExtStep::Add(6714, 6715), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11930PolyExtStep::Mul(6641, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11931PolyExtStep::Add(6714, 6717), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11932PolyExtStep::Mul(6643, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11933PolyExtStep::Add(6714, 6719), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11934PolyExtStep::Mul(6645, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11935PolyExtStep::Add(6714, 6721), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11936PolyExtStep::Mul(6647, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11937PolyExtStep::Add(6714, 6723), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11938PolyExtStep::Mul(6649, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11939PolyExtStep::Add(6714, 6725), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11940PolyExtStep::Mul(6651, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11941PolyExtStep::Add(6714, 6727), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11942PolyExtStep::Mul(6653, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11943PolyExtStep::Add(6714, 6729), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11944PolyExtStep::Mul(6655, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11945PolyExtStep::Add(6714, 6731), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11946PolyExtStep::Mul(6657, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11947PolyExtStep::Add(6714, 6733), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11948PolyExtStep::Mul(6659, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11949PolyExtStep::Add(6714, 6735), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11950PolyExtStep::Mul(6661, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11951PolyExtStep::Add(6714, 6737), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11952PolyExtStep::Mul(6663, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11953PolyExtStep::Add(6714, 6739), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11954PolyExtStep::Mul(6665, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11955PolyExtStep::Add(6714, 6741), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11956PolyExtStep::Mul(6667, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11957PolyExtStep::Add(6714, 6743), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11958PolyExtStep::Mul(6669, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11959PolyExtStep::Add(6714, 6745), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11960PolyExtStep::Mul(6671, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11961PolyExtStep::Add(6714, 6747), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11962PolyExtStep::Mul(6673, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11963PolyExtStep::Add(6714, 6749), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11964PolyExtStep::Mul(6675, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11965PolyExtStep::Add(6714, 6751), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11966PolyExtStep::Mul(6677, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11967PolyExtStep::Add(6714, 6753), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11968PolyExtStep::Mul(6679, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11969PolyExtStep::Add(6714, 6755), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11970PolyExtStep::Mul(6681, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11971PolyExtStep::Add(6714, 6757), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11972PolyExtStep::Mul(6683, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11973PolyExtStep::Add(6714, 6759), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11974PolyExtStep::Mul(6685, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11975PolyExtStep::Add(6714, 6761), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11976PolyExtStep::Add(6716, 280), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
11977PolyExtStep::Mul(6763, 6763), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11978PolyExtStep::Mul(6764, 6763), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11979PolyExtStep::Sub(6765, 587), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11980PolyExtStep::AndEqz(5185, 6766), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11981PolyExtStep::Mul(5454, 6763), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11982PolyExtStep::Sub(6767, 578), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11983PolyExtStep::AndEqz(5186, 6768), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11984PolyExtStep::Add(578, 6718), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11985PolyExtStep::Add(6769, 6720), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11986PolyExtStep::Add(6770, 6722), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11987PolyExtStep::Add(6771, 6724), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11988PolyExtStep::Add(6772, 6726), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11989PolyExtStep::Add(6773, 6728), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11990PolyExtStep::Add(6774, 6730), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11991PolyExtStep::Add(6775, 6732), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11992PolyExtStep::Add(6776, 6734), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11993PolyExtStep::Add(6777, 6736), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11994PolyExtStep::Add(6778, 6738), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11995PolyExtStep::Add(6779, 6740), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11996PolyExtStep::Add(6780, 6742), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11997PolyExtStep::Add(6781, 6744), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11998PolyExtStep::Add(6782, 6746), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
11999PolyExtStep::Add(6783, 6748), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12000PolyExtStep::Add(6784, 6750), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12001PolyExtStep::Add(6785, 6752), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12002PolyExtStep::Add(6786, 6754), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12003PolyExtStep::Add(6787, 6756), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12004PolyExtStep::Add(6788, 6758), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12005PolyExtStep::Add(6789, 6760), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12006PolyExtStep::Add(6790, 6762), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12007PolyExtStep::Mul(578, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12008PolyExtStep::Add(6791, 6792), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12009PolyExtStep::Mul(6718, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12010PolyExtStep::Add(6791, 6794), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12011PolyExtStep::Mul(6720, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12012PolyExtStep::Add(6791, 6796), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12013PolyExtStep::Mul(6722, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12014PolyExtStep::Add(6791, 6798), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12015PolyExtStep::Mul(6724, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12016PolyExtStep::Add(6791, 6800), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12017PolyExtStep::Mul(6726, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12018PolyExtStep::Add(6791, 6802), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12019PolyExtStep::Mul(6728, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12020PolyExtStep::Add(6791, 6804), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12021PolyExtStep::Mul(6730, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12022PolyExtStep::Add(6791, 6806), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12023PolyExtStep::Mul(6732, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12024PolyExtStep::Add(6791, 6808), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12025PolyExtStep::Mul(6734, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12026PolyExtStep::Add(6791, 6810), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12027PolyExtStep::Mul(6736, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12028PolyExtStep::Add(6791, 6812), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12029PolyExtStep::Mul(6738, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12030PolyExtStep::Add(6791, 6814), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12031PolyExtStep::Mul(6740, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12032PolyExtStep::Add(6791, 6816), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12033PolyExtStep::Mul(6742, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12034PolyExtStep::Add(6791, 6818), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12035PolyExtStep::Mul(6744, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12036PolyExtStep::Add(6791, 6820), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12037PolyExtStep::Mul(6746, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12038PolyExtStep::Add(6791, 6822), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12039PolyExtStep::Mul(6748, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12040PolyExtStep::Add(6791, 6824), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12041PolyExtStep::Mul(6750, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12042PolyExtStep::Add(6791, 6826), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12043PolyExtStep::Mul(6752, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12044PolyExtStep::Add(6791, 6828), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12045PolyExtStep::Mul(6754, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12046PolyExtStep::Add(6791, 6830), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12047PolyExtStep::Mul(6756, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12048PolyExtStep::Add(6791, 6832), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12049PolyExtStep::Mul(6758, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12050PolyExtStep::Add(6791, 6834), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12051PolyExtStep::Mul(6760, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12052PolyExtStep::Add(6791, 6836), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12053PolyExtStep::Mul(6762, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12054PolyExtStep::Add(6791, 6838), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12055PolyExtStep::Add(6793, 281), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12056PolyExtStep::Mul(6840, 6840), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12057PolyExtStep::Mul(6841, 6840), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12058PolyExtStep::Sub(6842, 739), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12059PolyExtStep::AndEqz(5187, 6843), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12060PolyExtStep::Mul(5461, 6840), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12061PolyExtStep::Sub(6844, 588), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12062PolyExtStep::AndEqz(5188, 6845), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12063PolyExtStep::Add(588, 6795), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12064PolyExtStep::Add(6846, 6797), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12065PolyExtStep::Add(6847, 6799), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12066PolyExtStep::Add(6848, 6801), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12067PolyExtStep::Add(6849, 6803), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12068PolyExtStep::Add(6850, 6805), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12069PolyExtStep::Add(6851, 6807), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12070PolyExtStep::Add(6852, 6809), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12071PolyExtStep::Add(6853, 6811), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12072PolyExtStep::Add(6854, 6813), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12073PolyExtStep::Add(6855, 6815), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12074PolyExtStep::Add(6856, 6817), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12075PolyExtStep::Add(6857, 6819), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12076PolyExtStep::Add(6858, 6821), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12077PolyExtStep::Add(6859, 6823), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12078PolyExtStep::Add(6860, 6825), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12079PolyExtStep::Add(6861, 6827), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12080PolyExtStep::Add(6862, 6829), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12081PolyExtStep::Add(6863, 6831), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12082PolyExtStep::Add(6864, 6833), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12083PolyExtStep::Add(6865, 6835), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12084PolyExtStep::Add(6866, 6837), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12085PolyExtStep::Add(6867, 6839), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12086PolyExtStep::Mul(588, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12087PolyExtStep::Add(6868, 6869), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12088PolyExtStep::Mul(6795, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12089PolyExtStep::Add(6868, 6871), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12090PolyExtStep::Mul(6797, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12091PolyExtStep::Add(6868, 6873), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12092PolyExtStep::Mul(6799, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12093PolyExtStep::Add(6868, 6875), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12094PolyExtStep::Mul(6801, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12095PolyExtStep::Add(6868, 6877), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12096PolyExtStep::Mul(6803, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12097PolyExtStep::Add(6868, 6879), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12098PolyExtStep::Mul(6805, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12099PolyExtStep::Add(6868, 6881), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12100PolyExtStep::Mul(6807, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12101PolyExtStep::Add(6868, 6883), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12102PolyExtStep::Mul(6809, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12103PolyExtStep::Add(6868, 6885), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12104PolyExtStep::Mul(6811, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12105PolyExtStep::Add(6868, 6887), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12106PolyExtStep::Mul(6813, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12107PolyExtStep::Add(6868, 6889), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12108PolyExtStep::Mul(6815, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12109PolyExtStep::Add(6868, 6891), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12110PolyExtStep::Mul(6817, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12111PolyExtStep::Add(6868, 6893), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12112PolyExtStep::Mul(6819, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12113PolyExtStep::Add(6868, 6895), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12114PolyExtStep::Mul(6821, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12115PolyExtStep::Add(6868, 6897), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12116PolyExtStep::Mul(6823, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12117PolyExtStep::Add(6868, 6899), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12118PolyExtStep::Mul(6825, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12119PolyExtStep::Add(6868, 6901), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12120PolyExtStep::Mul(6827, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12121PolyExtStep::Add(6868, 6903), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12122PolyExtStep::Mul(6829, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12123PolyExtStep::Add(6868, 6905), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12124PolyExtStep::Mul(6831, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12125PolyExtStep::Add(6868, 6907), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12126PolyExtStep::Mul(6833, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12127PolyExtStep::Add(6868, 6909), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12128PolyExtStep::Mul(6835, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12129PolyExtStep::Add(6868, 6911), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12130PolyExtStep::Mul(6837, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12131PolyExtStep::Add(6868, 6913), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12132PolyExtStep::Mul(6839, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12133PolyExtStep::Add(6868, 6915), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12134PolyExtStep::Add(6870, 282), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12135PolyExtStep::Mul(6917, 6917), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12136PolyExtStep::Mul(6918, 6917), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12137PolyExtStep::Sub(6919, 741), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12138PolyExtStep::AndEqz(5189, 6920), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12139PolyExtStep::Mul(5468, 6917), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12140PolyExtStep::Sub(6921, 740), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12141PolyExtStep::AndEqz(5190, 6922), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12142PolyExtStep::Add(740, 6872), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12143PolyExtStep::Add(6923, 6874), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12144PolyExtStep::Add(6924, 6876), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12145PolyExtStep::Add(6925, 6878), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12146PolyExtStep::Add(6926, 6880), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12147PolyExtStep::Add(6927, 6882), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12148PolyExtStep::Add(6928, 6884), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12149PolyExtStep::Add(6929, 6886), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12150PolyExtStep::Add(6930, 6888), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12151PolyExtStep::Add(6931, 6890), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12152PolyExtStep::Add(6932, 6892), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12153PolyExtStep::Add(6933, 6894), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12154PolyExtStep::Add(6934, 6896), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12155PolyExtStep::Add(6935, 6898), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12156PolyExtStep::Add(6936, 6900), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12157PolyExtStep::Add(6937, 6902), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12158PolyExtStep::Add(6938, 6904), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12159PolyExtStep::Add(6939, 6906), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12160PolyExtStep::Add(6940, 6908), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12161PolyExtStep::Add(6941, 6910), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12162PolyExtStep::Add(6942, 6912), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12163PolyExtStep::Add(6943, 6914), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12164PolyExtStep::Add(6944, 6916), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12165PolyExtStep::Mul(740, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12166PolyExtStep::Add(6945, 6946), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12167PolyExtStep::Mul(6872, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12168PolyExtStep::Add(6945, 6948), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12169PolyExtStep::Mul(6874, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12170PolyExtStep::Add(6945, 6950), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12171PolyExtStep::Mul(6876, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12172PolyExtStep::Add(6945, 6952), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12173PolyExtStep::Mul(6878, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12174PolyExtStep::Add(6945, 6954), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12175PolyExtStep::Mul(6880, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12176PolyExtStep::Add(6945, 6956), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12177PolyExtStep::Mul(6882, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12178PolyExtStep::Add(6945, 6958), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12179PolyExtStep::Mul(6884, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12180PolyExtStep::Add(6945, 6960), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12181PolyExtStep::Mul(6886, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12182PolyExtStep::Add(6945, 6962), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12183PolyExtStep::Mul(6888, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12184PolyExtStep::Add(6945, 6964), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12185PolyExtStep::Mul(6890, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12186PolyExtStep::Add(6945, 6966), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12187PolyExtStep::Mul(6892, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12188PolyExtStep::Add(6945, 6968), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12189PolyExtStep::Mul(6894, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12190PolyExtStep::Add(6945, 6970), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12191PolyExtStep::Mul(6896, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12192PolyExtStep::Add(6945, 6972), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12193PolyExtStep::Mul(6898, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12194PolyExtStep::Add(6945, 6974), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12195PolyExtStep::Mul(6900, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12196PolyExtStep::Add(6945, 6976), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12197PolyExtStep::Mul(6902, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12198PolyExtStep::Add(6945, 6978), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12199PolyExtStep::Mul(6904, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12200PolyExtStep::Add(6945, 6980), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12201PolyExtStep::Mul(6906, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12202PolyExtStep::Add(6945, 6982), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12203PolyExtStep::Mul(6908, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12204PolyExtStep::Add(6945, 6984), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12205PolyExtStep::Mul(6910, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12206PolyExtStep::Add(6945, 6986), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12207PolyExtStep::Mul(6912, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12208PolyExtStep::Add(6945, 6988), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12209PolyExtStep::Mul(6914, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12210PolyExtStep::Add(6945, 6990), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12211PolyExtStep::Mul(6916, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12212PolyExtStep::Add(6945, 6992), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12213PolyExtStep::Add(6947, 283), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12214PolyExtStep::Mul(6994, 6994), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12215PolyExtStep::Mul(6995, 6994), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12216PolyExtStep::Sub(6996, 743), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12217PolyExtStep::AndEqz(5191, 6997), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12218PolyExtStep::Mul(5475, 6994), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12219PolyExtStep::Sub(6998, 742), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12220PolyExtStep::AndEqz(5192, 6999), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12221PolyExtStep::Add(742, 6949), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12222PolyExtStep::Add(7000, 6951), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12223PolyExtStep::Add(7001, 6953), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12224PolyExtStep::Add(7002, 6955), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12225PolyExtStep::Add(7003, 6957), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12226PolyExtStep::Add(7004, 6959), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12227PolyExtStep::Add(7005, 6961), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12228PolyExtStep::Add(7006, 6963), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12229PolyExtStep::Add(7007, 6965), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12230PolyExtStep::Add(7008, 6967), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12231PolyExtStep::Add(7009, 6969), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12232PolyExtStep::Add(7010, 6971), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12233PolyExtStep::Add(7011, 6973), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12234PolyExtStep::Add(7012, 6975), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12235PolyExtStep::Add(7013, 6977), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12236PolyExtStep::Add(7014, 6979), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12237PolyExtStep::Add(7015, 6981), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12238PolyExtStep::Add(7016, 6983), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12239PolyExtStep::Add(7017, 6985), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12240PolyExtStep::Add(7018, 6987), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12241PolyExtStep::Add(7019, 6989), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12242PolyExtStep::Add(7020, 6991), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12243PolyExtStep::Add(7021, 6993), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12244PolyExtStep::Mul(742, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12245PolyExtStep::Add(7022, 7023), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12246PolyExtStep::Mul(6949, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12247PolyExtStep::Add(7022, 7025), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12248PolyExtStep::Mul(6951, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12249PolyExtStep::Add(7022, 7027), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12250PolyExtStep::Mul(6953, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12251PolyExtStep::Add(7022, 7029), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12252PolyExtStep::Mul(6955, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12253PolyExtStep::Add(7022, 7031), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12254PolyExtStep::Mul(6957, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12255PolyExtStep::Add(7022, 7033), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12256PolyExtStep::Mul(6959, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12257PolyExtStep::Add(7022, 7035), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12258PolyExtStep::Mul(6961, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12259PolyExtStep::Add(7022, 7037), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12260PolyExtStep::Mul(6963, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12261PolyExtStep::Add(7022, 7039), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12262PolyExtStep::Mul(6965, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12263PolyExtStep::Add(7022, 7041), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12264PolyExtStep::Mul(6967, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12265PolyExtStep::Add(7022, 7043), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12266PolyExtStep::Mul(6969, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12267PolyExtStep::Add(7022, 7045), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12268PolyExtStep::Mul(6971, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12269PolyExtStep::Add(7022, 7047), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12270PolyExtStep::Mul(6973, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12271PolyExtStep::Add(7022, 7049), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12272PolyExtStep::Mul(6975, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12273PolyExtStep::Add(7022, 7051), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12274PolyExtStep::Mul(6977, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12275PolyExtStep::Add(7022, 7053), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12276PolyExtStep::Mul(6979, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12277PolyExtStep::Add(7022, 7055), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12278PolyExtStep::Mul(6981, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12279PolyExtStep::Add(7022, 7057), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12280PolyExtStep::Mul(6983, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12281PolyExtStep::Add(7022, 7059), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12282PolyExtStep::Mul(6985, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12283PolyExtStep::Add(7022, 7061), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12284PolyExtStep::Mul(6987, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12285PolyExtStep::Add(7022, 7063), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12286PolyExtStep::Mul(6989, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12287PolyExtStep::Add(7022, 7065), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12288PolyExtStep::Mul(6991, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12289PolyExtStep::Add(7022, 7067), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12290PolyExtStep::Mul(6993, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12291PolyExtStep::Add(7022, 7069), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12292PolyExtStep::Add(7024, 284), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12293PolyExtStep::Mul(7071, 7071), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12294PolyExtStep::Mul(7072, 7071), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12295PolyExtStep::Sub(7073, 745), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12296PolyExtStep::AndEqz(5193, 7074), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12297PolyExtStep::Mul(5482, 7071), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12298PolyExtStep::Sub(7075, 744), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12299PolyExtStep::AndEqz(5194, 7076), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12300PolyExtStep::Add(744, 7026), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12301PolyExtStep::Add(7077, 7028), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12302PolyExtStep::Add(7078, 7030), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12303PolyExtStep::Add(7079, 7032), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12304PolyExtStep::Add(7080, 7034), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12305PolyExtStep::Add(7081, 7036), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12306PolyExtStep::Add(7082, 7038), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12307PolyExtStep::Add(7083, 7040), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12308PolyExtStep::Add(7084, 7042), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12309PolyExtStep::Add(7085, 7044), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12310PolyExtStep::Add(7086, 7046), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12311PolyExtStep::Add(7087, 7048), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12312PolyExtStep::Add(7088, 7050), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12313PolyExtStep::Add(7089, 7052), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12314PolyExtStep::Add(7090, 7054), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12315PolyExtStep::Add(7091, 7056), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12316PolyExtStep::Add(7092, 7058), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12317PolyExtStep::Add(7093, 7060), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12318PolyExtStep::Add(7094, 7062), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12319PolyExtStep::Add(7095, 7064), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12320PolyExtStep::Add(7096, 7066), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12321PolyExtStep::Add(7097, 7068), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12322PolyExtStep::Add(7098, 7070), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12323PolyExtStep::Mul(744, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12324PolyExtStep::Add(7099, 7100), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12325PolyExtStep::Mul(7026, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12326PolyExtStep::Add(7099, 7102), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12327PolyExtStep::Mul(7028, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12328PolyExtStep::Add(7099, 7104), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12329PolyExtStep::Mul(7030, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12330PolyExtStep::Add(7099, 7106), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12331PolyExtStep::Mul(7032, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12332PolyExtStep::Add(7099, 7108), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12333PolyExtStep::Mul(7034, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12334PolyExtStep::Add(7099, 7110), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12335PolyExtStep::Mul(7036, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12336PolyExtStep::Add(7099, 7112), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12337PolyExtStep::Mul(7038, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12338PolyExtStep::Add(7099, 7114), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12339PolyExtStep::Mul(7040, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12340PolyExtStep::Add(7099, 7116), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12341PolyExtStep::Mul(7042, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12342PolyExtStep::Add(7099, 7118), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12343PolyExtStep::Mul(7044, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12344PolyExtStep::Add(7099, 7120), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12345PolyExtStep::Mul(7046, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12346PolyExtStep::Add(7099, 7122), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12347PolyExtStep::Mul(7048, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12348PolyExtStep::Add(7099, 7124), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12349PolyExtStep::Mul(7050, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12350PolyExtStep::Add(7099, 7126), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12351PolyExtStep::Mul(7052, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12352PolyExtStep::Add(7099, 7128), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12353PolyExtStep::Mul(7054, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12354PolyExtStep::Add(7099, 7130), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12355PolyExtStep::Mul(7056, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12356PolyExtStep::Add(7099, 7132), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12357PolyExtStep::Mul(7058, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12358PolyExtStep::Add(7099, 7134), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12359PolyExtStep::Mul(7060, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12360PolyExtStep::Add(7099, 7136), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12361PolyExtStep::Mul(7062, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12362PolyExtStep::Add(7099, 7138), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12363PolyExtStep::Mul(7064, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12364PolyExtStep::Add(7099, 7140), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12365PolyExtStep::Mul(7066, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12366PolyExtStep::Add(7099, 7142), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12367PolyExtStep::Mul(7068, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12368PolyExtStep::Add(7099, 7144), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12369PolyExtStep::Mul(7070, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12370PolyExtStep::Add(7099, 7146), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12371PolyExtStep::Add(7101, 285), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12372PolyExtStep::Mul(7148, 7148), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12373PolyExtStep::Mul(7149, 7148), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12374PolyExtStep::Sub(7150, 747), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12375PolyExtStep::AndEqz(5195, 7151), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12376PolyExtStep::Mul(5489, 7148), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12377PolyExtStep::Sub(7152, 746), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12378PolyExtStep::AndEqz(5196, 7153), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12379PolyExtStep::Add(746, 7103), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12380PolyExtStep::Add(7154, 7105), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12381PolyExtStep::Add(7155, 7107), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12382PolyExtStep::Add(7156, 7109), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12383PolyExtStep::Add(7157, 7111), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12384PolyExtStep::Add(7158, 7113), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12385PolyExtStep::Add(7159, 7115), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12386PolyExtStep::Add(7160, 7117), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12387PolyExtStep::Add(7161, 7119), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12388PolyExtStep::Add(7162, 7121), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12389PolyExtStep::Add(7163, 7123), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12390PolyExtStep::Add(7164, 7125), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12391PolyExtStep::Add(7165, 7127), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12392PolyExtStep::Add(7166, 7129), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12393PolyExtStep::Add(7167, 7131), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12394PolyExtStep::Add(7168, 7133), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12395PolyExtStep::Add(7169, 7135), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12396PolyExtStep::Add(7170, 7137), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12397PolyExtStep::Add(7171, 7139), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12398PolyExtStep::Add(7172, 7141), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12399PolyExtStep::Add(7173, 7143), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12400PolyExtStep::Add(7174, 7145), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12401PolyExtStep::Add(7175, 7147), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12402PolyExtStep::Mul(746, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12403PolyExtStep::Add(7176, 7177), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12404PolyExtStep::Mul(7103, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12405PolyExtStep::Add(7176, 7179), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12406PolyExtStep::Mul(7105, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12407PolyExtStep::Add(7176, 7181), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12408PolyExtStep::Mul(7107, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12409PolyExtStep::Add(7176, 7183), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12410PolyExtStep::Mul(7109, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12411PolyExtStep::Add(7176, 7185), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12412PolyExtStep::Mul(7111, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12413PolyExtStep::Add(7176, 7187), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12414PolyExtStep::Mul(7113, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12415PolyExtStep::Add(7176, 7189), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12416PolyExtStep::Mul(7115, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12417PolyExtStep::Add(7176, 7191), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12418PolyExtStep::Mul(7117, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12419PolyExtStep::Add(7176, 7193), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12420PolyExtStep::Mul(7119, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12421PolyExtStep::Add(7176, 7195), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12422PolyExtStep::Mul(7121, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12423PolyExtStep::Add(7176, 7197), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12424PolyExtStep::Mul(7123, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12425PolyExtStep::Add(7176, 7199), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12426PolyExtStep::Mul(7125, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12427PolyExtStep::Add(7176, 7201), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12428PolyExtStep::Mul(7127, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12429PolyExtStep::Add(7176, 7203), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12430PolyExtStep::Mul(7129, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12431PolyExtStep::Add(7176, 7205), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12432PolyExtStep::Mul(7131, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12433PolyExtStep::Add(7176, 7207), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12434PolyExtStep::Mul(7133, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12435PolyExtStep::Add(7176, 7209), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12436PolyExtStep::Mul(7135, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12437PolyExtStep::Add(7176, 7211), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12438PolyExtStep::Mul(7137, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12439PolyExtStep::Add(7176, 7213), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12440PolyExtStep::Mul(7139, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12441PolyExtStep::Add(7176, 7215), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12442PolyExtStep::Mul(7141, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12443PolyExtStep::Add(7176, 7217), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12444PolyExtStep::Mul(7143, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12445PolyExtStep::Add(7176, 7219), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12446PolyExtStep::Mul(7145, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12447PolyExtStep::Add(7176, 7221), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12448PolyExtStep::Mul(7147, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12449PolyExtStep::Add(7176, 7223), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12450PolyExtStep::Add(7178, 286), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12451PolyExtStep::Mul(7225, 7225), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12452PolyExtStep::Mul(7226, 7225), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12453PolyExtStep::Sub(7227, 766), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12454PolyExtStep::AndEqz(5197, 7228), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12455PolyExtStep::Mul(5496, 7225), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12456PolyExtStep::Sub(7229, 760), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12457PolyExtStep::AndEqz(5198, 7230), // loc(callsite( Reg ( <preamble> :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12458PolyExtStep::Add(760, 7180), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12459PolyExtStep::Add(7231, 7182), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12460PolyExtStep::Add(7232, 7184), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12461PolyExtStep::Add(7233, 7186), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12462PolyExtStep::Add(7234, 7188), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12463PolyExtStep::Add(7235, 7190), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12464PolyExtStep::Add(7236, 7192), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12465PolyExtStep::Add(7237, 7194), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12466PolyExtStep::Add(7238, 7196), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12467PolyExtStep::Add(7239, 7198), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12468PolyExtStep::Add(7240, 7200), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12469PolyExtStep::Add(7241, 7202), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12470PolyExtStep::Add(7242, 7204), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12471PolyExtStep::Add(7243, 7206), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12472PolyExtStep::Add(7244, 7208), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12473PolyExtStep::Add(7245, 7210), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12474PolyExtStep::Add(7246, 7212), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12475PolyExtStep::Add(7247, 7214), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12476PolyExtStep::Add(7248, 7216), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12477PolyExtStep::Add(7249, 7218), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12478PolyExtStep::Add(7250, 7220), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12479PolyExtStep::Add(7251, 7222), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12480PolyExtStep::Add(7252, 7224), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12481PolyExtStep::Mul(760, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12482PolyExtStep::Add(7253, 7254), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12483PolyExtStep::Mul(7180, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12484PolyExtStep::Add(7253, 7256), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12485PolyExtStep::Mul(7182, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12486PolyExtStep::Add(7253, 7258), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12487PolyExtStep::Mul(7184, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12488PolyExtStep::Add(7253, 7260), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12489PolyExtStep::Mul(7186, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12490PolyExtStep::Add(7253, 7262), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12491PolyExtStep::Mul(7188, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12492PolyExtStep::Add(7253, 7264), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12493PolyExtStep::Mul(7190, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12494PolyExtStep::Add(7253, 7266), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12495PolyExtStep::Mul(7192, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12496PolyExtStep::Add(7253, 7268), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12497PolyExtStep::Mul(7194, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12498PolyExtStep::Add(7253, 7270), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12499PolyExtStep::Mul(7196, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12500PolyExtStep::Add(7253, 7272), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12501PolyExtStep::Mul(7198, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12502PolyExtStep::Add(7253, 7274), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12503PolyExtStep::Mul(7200, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12504PolyExtStep::Add(7253, 7276), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12505PolyExtStep::Mul(7202, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12506PolyExtStep::Add(7253, 7278), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12507PolyExtStep::Mul(7204, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12508PolyExtStep::Add(7253, 7280), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12509PolyExtStep::Mul(7206, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12510PolyExtStep::Add(7253, 7282), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12511PolyExtStep::Mul(7208, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12512PolyExtStep::Add(7253, 7284), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12513PolyExtStep::Mul(7210, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12514PolyExtStep::Add(7253, 7286), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12515PolyExtStep::Mul(7212, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12516PolyExtStep::Add(7253, 7288), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12517PolyExtStep::Mul(7214, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12518PolyExtStep::Add(7253, 7290), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12519PolyExtStep::Mul(7216, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12520PolyExtStep::Add(7253, 7292), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12521PolyExtStep::Mul(7218, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12522PolyExtStep::Add(7253, 7294), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12523PolyExtStep::Mul(7220, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12524PolyExtStep::Add(7253, 7296), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12525PolyExtStep::Mul(7222, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12526PolyExtStep::Add(7253, 7298), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12527PolyExtStep::Mul(7224, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12528PolyExtStep::Add(7253, 7300), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12529PolyExtStep::AndEqz(5199, 4095), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12530PolyExtStep::AndEqz(5200, 4096), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12531PolyExtStep::AndEqz(5201, 4097), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12532PolyExtStep::AndEqz(5202, 4098), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12533PolyExtStep::AndEqz(5203, 4099), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12534PolyExtStep::AndEqz(5204, 4100), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12535PolyExtStep::AndEqz(5205, 4542), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12536PolyExtStep::Sub(5, 1154), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12537PolyExtStep::AndEqz(5206, 7302), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12538PolyExtStep::AndEqz(5207, 4102), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12539PolyExtStep::AndEqz(5208, 4103), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12540PolyExtStep::AndEqz(5209, 4104), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12541PolyExtStep::Sub(7255, 1373), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12542PolyExtStep::AndEqz(5210, 7303), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12543PolyExtStep::Sub(7257, 1375), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12544PolyExtStep::AndEqz(5211, 7304), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12545PolyExtStep::Sub(7259, 1382), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12546PolyExtStep::AndEqz(5212, 7305), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12547PolyExtStep::Sub(7261, 1383), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12548PolyExtStep::AndEqz(5213, 7306), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12549PolyExtStep::Sub(7263, 1385), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12550PolyExtStep::AndEqz(5214, 7307), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12551PolyExtStep::Sub(7265, 1391), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12552PolyExtStep::AndEqz(5215, 7308), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12553PolyExtStep::Sub(7267, 1392), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12554PolyExtStep::AndEqz(5216, 7309), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12555PolyExtStep::Sub(7269, 1394), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12556PolyExtStep::AndEqz(5217, 7310), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12557PolyExtStep::Sub(7271, 1401), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12558PolyExtStep::AndEqz(5218, 7311), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12559PolyExtStep::Sub(7273, 1402), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12560PolyExtStep::AndEqz(5219, 7312), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12561PolyExtStep::Sub(7275, 1404), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12562PolyExtStep::AndEqz(5220, 7313), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12563PolyExtStep::Sub(7277, 1410), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12564PolyExtStep::AndEqz(5221, 7314), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12565PolyExtStep::Sub(7279, 1411), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12566PolyExtStep::AndEqz(5222, 7315), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12567PolyExtStep::Sub(7281, 1424), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12568PolyExtStep::AndEqz(5223, 7316), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12569PolyExtStep::Sub(7283, 1427), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12570PolyExtStep::AndEqz(5224, 7317), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12571PolyExtStep::Sub(7285, 1426), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12572PolyExtStep::AndEqz(5225, 7318), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12573PolyExtStep::Sub(7287, 1428), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12574PolyExtStep::AndEqz(5226, 7319), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12575PolyExtStep::Sub(7289, 1829), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12576PolyExtStep::AndEqz(5227, 7320), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12577PolyExtStep::Sub(7291, 1830), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12578PolyExtStep::AndEqz(5228, 7321), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12579PolyExtStep::Sub(7293, 1429), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12580PolyExtStep::AndEqz(5229, 7322), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12581PolyExtStep::Sub(7295, 1430), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12582PolyExtStep::AndEqz(5230, 7323), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12583PolyExtStep::Sub(7297, 1431), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12584PolyExtStep::AndEqz(5231, 7324), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12585PolyExtStep::Sub(7299, 1432), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12586PolyExtStep::AndEqz(5232, 7325), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12587PolyExtStep::Sub(7301, 1439), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12588PolyExtStep::AndEqz(5233, 7326), // loc(callsite( Reg ( <preamble> :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12589PolyExtStep::AndEqz(5234, 5681), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12590PolyExtStep::AndCond(5157, 380, 5235), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12591PolyExtStep::AndCond(5236, 383, 4221), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12592PolyExtStep::AndCond(5237, 386, 4221), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12593PolyExtStep::AndCond(5238, 389, 4221), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12594PolyExtStep::AndCond(5239, 392, 4221), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12595PolyExtStep::AndCond(5240, 395, 4221), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12596PolyExtStep::AndCond(5241, 398, 4221), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12597PolyExtStep::AndCond(5047, 452, 5242), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
12598PolyExtStep::Add(376, 24), // loc(callsite( builtin Add at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :226:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12599PolyExtStep::Sub(371, 7327), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :226:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12600PolyExtStep::Sub(1075, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :225:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12601PolyExtStep::AndEqz(0, 7329), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :225:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12602PolyExtStep::Sub(1081, 542), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :225:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12603PolyExtStep::AndEqz(5244, 7330), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :225:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12604PolyExtStep::AndEqz(5245, 7328), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :226:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12605PolyExtStep::Sub(814, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12606PolyExtStep::AndEqz(0, 7331), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12607PolyExtStep::AndEqz(5247, 3893), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12608PolyExtStep::Sub(832, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12609PolyExtStep::AndEqz(5248, 7332), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12610PolyExtStep::AndEqz(5249, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12611PolyExtStep::Sub(817, 62), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12612PolyExtStep::AndEqz(5250, 7333), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12613PolyExtStep::AndEqz(5251, 4091), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12614PolyExtStep::Sub(826, 838), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12615PolyExtStep::AndEqz(5252, 7334), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12616PolyExtStep::Sub(3146, 820), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12617PolyExtStep::AndEqz(5253, 4828), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12618PolyExtStep::Sub(1014, 7335), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12619PolyExtStep::AndEqz(5254, 7336), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12620PolyExtStep::Mul(838, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12621PolyExtStep::Mul(835, 63), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12622PolyExtStep::Add(7337, 7338), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12623PolyExtStep::Sub(841, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12624PolyExtStep::AndEqz(5255, 7340), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12625PolyExtStep::AndEqz(5256, 3992), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12626PolyExtStep::Sub(859, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12627PolyExtStep::AndEqz(5257, 7341), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12628PolyExtStep::AndEqz(5258, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12629PolyExtStep::Sub(844, 64), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12630PolyExtStep::AndEqz(5259, 7342), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12631PolyExtStep::Sub(850, 893), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12632PolyExtStep::AndEqz(5260, 7343), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12633PolyExtStep::Sub(853, 896), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12634PolyExtStep::AndEqz(5261, 7344), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12635PolyExtStep::Sub(859, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12636PolyExtStep::Sub(7345, 847), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12637PolyExtStep::Sub(1017, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12638PolyExtStep::AndEqz(5262, 7347), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12639PolyExtStep::Sub(1051, 7346), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12640PolyExtStep::AndEqz(5263, 7348), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12641PolyExtStep::Mul(896, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12642PolyExtStep::Mul(893, 63), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12643PolyExtStep::Add(7349, 7350), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12644PolyExtStep::Sub(899, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12645PolyExtStep::AndEqz(5264, 7352), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12646PolyExtStep::Sub(914, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12647PolyExtStep::AndEqz(5265, 7353), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12648PolyExtStep::Sub(917, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12649PolyExtStep::AndEqz(5266, 7354), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12650PolyExtStep::AndEqz(5267, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12651PolyExtStep::Sub(902, 65), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12652PolyExtStep::AndEqz(5268, 7355), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12653PolyExtStep::Sub(908, 920), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12654PolyExtStep::AndEqz(5269, 7356), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12655PolyExtStep::Sub(911, 923), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12656PolyExtStep::AndEqz(5270, 7357), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12657PolyExtStep::Sub(4774, 905), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12658PolyExtStep::AndEqz(5271, 4839), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12659PolyExtStep::Sub(1057, 7358), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12660PolyExtStep::AndEqz(5272, 7359), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12661PolyExtStep::Mul(923, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12662PolyExtStep::Mul(920, 63), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12663PolyExtStep::Add(7360, 7361), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12664PolyExtStep::Sub(926, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12665PolyExtStep::AndEqz(5273, 7363), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12666PolyExtStep::AndEqz(5274, 4794), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12667PolyExtStep::Sub(975, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12668PolyExtStep::AndEqz(5275, 7364), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12669PolyExtStep::AndEqz(5276, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12670PolyExtStep::Sub(929, 66), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12671PolyExtStep::AndEqz(5277, 7365), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12672PolyExtStep::Sub(935, 978), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12673PolyExtStep::AndEqz(5278, 7366), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12674PolyExtStep::Sub(938, 981), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12675PolyExtStep::AndEqz(5279, 7367), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12676PolyExtStep::Sub(2052, 932), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12677PolyExtStep::Sub(1060, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12678PolyExtStep::AndEqz(5280, 7369), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12679PolyExtStep::Sub(1063, 7368), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12680PolyExtStep::AndEqz(5281, 7370), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12681PolyExtStep::Sub(984, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12682PolyExtStep::AndEqz(5282, 7371), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12683PolyExtStep::AndEqz(5283, 4817), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12684PolyExtStep::Sub(1002, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12685PolyExtStep::AndEqz(5284, 7372), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12686PolyExtStep::AndEqz(5285, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12687PolyExtStep::Sub(987, 311), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12688PolyExtStep::AndEqz(5286, 7373), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12689PolyExtStep::Sub(993, 1005), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12690PolyExtStep::AndEqz(5287, 7374), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12691PolyExtStep::Sub(996, 1008), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12692PolyExtStep::AndEqz(5288, 7375), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12693PolyExtStep::Sub(4820, 990), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12694PolyExtStep::AndEqz(5289, 4850), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12695PolyExtStep::Sub(1069, 7376), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12696PolyExtStep::AndEqz(5290, 7377), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
12697PolyExtStep::Mul(1008, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12698PolyExtStep::Mul(1005, 63), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12699PolyExtStep::Add(7378, 7379), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12700PolyExtStep::Sub(7339, 807), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :20:29) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12701PolyExtStep::AndEqz(5291, 7381), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :20:29) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12702PolyExtStep::Sub(7351, 1137), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :21:30) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12703PolyExtStep::AndEqz(5292, 7382), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :21:30) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12704PolyExtStep::Sub(7362, 808), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12705PolyExtStep::AndEqz(5293, 7383), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12706PolyExtStep::Sub(978, 1143), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12707PolyExtStep::AndEqz(5294, 7384), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12708PolyExtStep::Sub(7380, 809), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :24:23) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12709PolyExtStep::AndEqz(5295, 7385), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :24:23) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12710PolyExtStep::AndEqz(5296, 4027), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :25:23) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12711PolyExtStep::Sub(312, 810), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12712PolyExtStep::AndEqz(5297, 7386), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12713PolyExtStep::AndCond(5246, 377, 5298), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
12714PolyExtStep::Sub(6, 4036), // loc(callsite( builtin Sub at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12715PolyExtStep::AndEqz(0, 1086), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12716PolyExtStep::Mul(7387, 1087), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12717PolyExtStep::Sub(7388, 1085), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12718PolyExtStep::AndEqz(5300, 7389), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12719PolyExtStep::Mul(1084, 7387), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12720PolyExtStep::AndEqz(5301, 7390), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12721PolyExtStep::Mul(1084, 1087), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12722PolyExtStep::AndEqz(5302, 7391), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12723PolyExtStep::AndEqz(5303, 1092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12724PolyExtStep::Mul(4034, 1093), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12725PolyExtStep::Sub(7392, 1091), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12726PolyExtStep::AndEqz(5304, 7393), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12727PolyExtStep::Mul(1090, 4034), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12728PolyExtStep::AndEqz(5305, 7394), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12729PolyExtStep::Mul(1090, 1093), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12730PolyExtStep::AndEqz(5306, 7395), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12731PolyExtStep::Mul(1090, 13), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :102:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12732PolyExtStep::Mul(1091, 313), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :102:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12733PolyExtStep::Add(7396, 7397), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :102:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12734PolyExtStep::Mul(7398, 1084), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :101:17) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12735PolyExtStep::Mul(1085, 312), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :101:17) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12736PolyExtStep::Add(7399, 7400), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :101:17) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
12737PolyExtStep::Add(4031, 6), // loc(callsite( builtin Add at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:34) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12738PolyExtStep::Sub(7402, 4036), // loc(callsite( builtin Sub at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:48) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12739PolyExtStep::AndEqz(5307, 7331), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12740PolyExtStep::AndEqz(5308, 3893), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12741PolyExtStep::AndEqz(5309, 7332), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12742PolyExtStep::AndEqz(5310, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12743PolyExtStep::Sub(817, 7403), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12744PolyExtStep::AndEqz(5311, 7404), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12745PolyExtStep::AndEqz(5312, 4091), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12746PolyExtStep::AndEqz(5313, 7334), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12747PolyExtStep::AndEqz(5314, 4828), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12748PolyExtStep::AndEqz(5315, 7336), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12749PolyExtStep::Add(4031, 2), // loc(callsite( builtin Add at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:34) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12750PolyExtStep::Sub(7405, 4036), // loc(callsite( builtin Sub at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:48) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12751PolyExtStep::AndEqz(5316, 7340), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12752PolyExtStep::AndEqz(5317, 3992), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12753PolyExtStep::AndEqz(5318, 7341), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12754PolyExtStep::AndEqz(5319, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12755PolyExtStep::Sub(844, 7406), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12756PolyExtStep::AndEqz(5320, 7407), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12757PolyExtStep::AndEqz(5321, 7343), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12758PolyExtStep::AndEqz(5322, 7344), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12759PolyExtStep::AndEqz(5323, 7347), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12760PolyExtStep::AndEqz(5324, 7348), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12761PolyExtStep::Sub(4051, 4036), // loc(callsite( builtin Sub at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:43) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12762PolyExtStep::AndEqz(5325, 7352), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12763PolyExtStep::AndEqz(5326, 7353), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12764PolyExtStep::Sub(917, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12765PolyExtStep::AndEqz(5327, 7409), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12766PolyExtStep::AndEqz(5328, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12767PolyExtStep::Sub(902, 7408), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12768PolyExtStep::AndEqz(5329, 7410), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12769PolyExtStep::AndEqz(5330, 4839), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12770PolyExtStep::AndEqz(5331, 7359), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12771PolyExtStep::Sub(920, 835), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12772PolyExtStep::AndEqz(5332, 7411), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12773PolyExtStep::Sub(923, 838), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12774PolyExtStep::AndEqz(5333, 7412), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12775PolyExtStep::Sub(4085, 4036), // loc(callsite( builtin Sub at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:43) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12776PolyExtStep::AndEqz(5334, 7363), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12777PolyExtStep::AndEqz(5335, 4794), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12778PolyExtStep::Sub(975, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12779PolyExtStep::AndEqz(5336, 7414), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12780PolyExtStep::AndEqz(5337, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12781PolyExtStep::Sub(929, 7413), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12782PolyExtStep::AndEqz(5338, 7415), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12783PolyExtStep::AndEqz(5339, 7369), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12784PolyExtStep::AndEqz(5340, 7370), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12785PolyExtStep::Sub(978, 893), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12786PolyExtStep::AndEqz(5341, 7416), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12787PolyExtStep::Sub(981, 896), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12788PolyExtStep::AndEqz(5342, 7417), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12789PolyExtStep::Add(4036, 1), // loc(callsite( builtin Add at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :123:30) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12790PolyExtStep::Mul(1085, 7418), // loc(callsite( builtin Mul at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :123:20) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12791PolyExtStep::AndEqz(5343, 4095), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :20:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12792PolyExtStep::AndEqz(5344, 4096), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :21:30) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12793PolyExtStep::AndEqz(5345, 4097), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12794PolyExtStep::AndEqz(5346, 4098), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12795PolyExtStep::AndEqz(5347, 4099), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :24:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12796PolyExtStep::Sub(7419, 1148), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :25:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12797PolyExtStep::AndEqz(5348, 7420), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :25:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12798PolyExtStep::Sub(7401, 810), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12799PolyExtStep::AndEqz(5349, 7421), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12800PolyExtStep::Mul(811, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12801PolyExtStep::Mul(1160, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12802PolyExtStep::Mul(1372, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12803PolyExtStep::Mul(1373, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12804PolyExtStep::Mul(1375, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12805PolyExtStep::Mul(1382, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12806PolyExtStep::Mul(1383, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12807PolyExtStep::Add(1154, 7422), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12808PolyExtStep::Add(7429, 7423), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12809PolyExtStep::Add(7430, 7424), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12810PolyExtStep::Add(7431, 7425), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12811PolyExtStep::Add(7432, 7426), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12812PolyExtStep::Add(7433, 7427), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12813PolyExtStep::Add(7434, 7428), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12814PolyExtStep::Mul(1391, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12815PolyExtStep::Mul(1392, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12816PolyExtStep::Mul(1394, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12817PolyExtStep::Mul(1401, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12818PolyExtStep::Mul(1402, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12819PolyExtStep::Mul(1404, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12820PolyExtStep::Mul(1410, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12821PolyExtStep::Add(1385, 7436), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12822PolyExtStep::Add(7443, 7437), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12823PolyExtStep::Add(7444, 7438), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12824PolyExtStep::Add(7445, 7439), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12825PolyExtStep::Add(7446, 7440), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12826PolyExtStep::Add(7447, 7441), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12827PolyExtStep::Add(7448, 7442), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12828PolyExtStep::Mul(1424, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12829PolyExtStep::Mul(1427, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12830PolyExtStep::Mul(1426, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12831PolyExtStep::Mul(1428, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12832PolyExtStep::Mul(1829, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12833PolyExtStep::Mul(1830, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12834PolyExtStep::Mul(1429, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12835PolyExtStep::Add(1411, 7450), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12836PolyExtStep::Add(7457, 7451), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12837PolyExtStep::Add(7458, 7452), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12838PolyExtStep::Add(7459, 7453), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12839PolyExtStep::Add(7460, 7454), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12840PolyExtStep::Add(7461, 7455), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12841PolyExtStep::Add(7462, 7456), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12842PolyExtStep::Mul(1431, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12843PolyExtStep::Mul(1432, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12844PolyExtStep::Mul(1439, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12845PolyExtStep::Mul(1440, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12846PolyExtStep::Mul(1900, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12847PolyExtStep::Mul(538, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12848PolyExtStep::Mul(2278, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12849PolyExtStep::Add(1430, 7464), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12850PolyExtStep::Add(7471, 7465), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12851PolyExtStep::Add(7472, 7466), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12852PolyExtStep::Add(7473, 7467), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12853PolyExtStep::Add(7474, 7468), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12854PolyExtStep::Add(7475, 7469), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12855PolyExtStep::Add(7476, 7470), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12856PolyExtStep::Mul(1154, 4585), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12857PolyExtStep::AndEqz(5350, 7478), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12858PolyExtStep::Sub(1, 811), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12859PolyExtStep::Mul(811, 7479), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12860PolyExtStep::AndEqz(5351, 7480), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12861PolyExtStep::Mul(1160, 4915), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12862PolyExtStep::AndEqz(5352, 7481), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12863PolyExtStep::Mul(1372, 4920), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12864PolyExtStep::AndEqz(5353, 7482), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12865PolyExtStep::Sub(1, 1373), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12866PolyExtStep::Mul(1373, 7483), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12867PolyExtStep::AndEqz(5354, 7484), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12868PolyExtStep::AndEqz(5355, 1377), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12869PolyExtStep::AndEqz(5356, 2799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12870PolyExtStep::AndEqz(5357, 2805), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12871PolyExtStep::AndEqz(5358, 1387), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12872PolyExtStep::AndEqz(5359, 2815), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12873PolyExtStep::AndEqz(5360, 2821), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12874PolyExtStep::AndEqz(5361, 1396), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12875PolyExtStep::AndEqz(5362, 2827), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12876PolyExtStep::AndEqz(5363, 2833), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12877PolyExtStep::AndEqz(5364, 1406), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12878PolyExtStep::AndEqz(5365, 1413), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12879PolyExtStep::AndEqz(5366, 2839), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12880PolyExtStep::AndEqz(5367, 2845), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12881PolyExtStep::AndEqz(5368, 2851), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12882PolyExtStep::AndEqz(5369, 2857), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12883PolyExtStep::Sub(1, 1428), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12884PolyExtStep::Mul(1428, 7485), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12885PolyExtStep::AndEqz(5370, 7486), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12886PolyExtStep::AndEqz(5371, 2772), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12887PolyExtStep::Sub(1, 1830), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12888PolyExtStep::Mul(1830, 7487), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12889PolyExtStep::AndEqz(5372, 7488), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12890PolyExtStep::Sub(1, 1429), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12891PolyExtStep::Mul(1429, 7489), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12892PolyExtStep::AndEqz(5373, 7490), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12893PolyExtStep::AndEqz(5374, 2780), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12894PolyExtStep::Sub(1, 1431), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12895PolyExtStep::Mul(1431, 7491), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12896PolyExtStep::AndEqz(5375, 7492), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12897PolyExtStep::Sub(1, 1432), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12898PolyExtStep::Mul(1432, 7493), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12899PolyExtStep::AndEqz(5376, 7494), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12900PolyExtStep::Sub(1, 1439), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12901PolyExtStep::Mul(1439, 7495), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12902PolyExtStep::AndEqz(5377, 7496), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12903PolyExtStep::Sub(1, 1440), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12904PolyExtStep::Mul(1440, 7497), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12905PolyExtStep::AndEqz(5378, 7498), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12906PolyExtStep::Sub(1, 1900), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12907PolyExtStep::Mul(1900, 7499), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12908PolyExtStep::AndEqz(5379, 7500), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12909PolyExtStep::Sub(1, 538), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12910PolyExtStep::Mul(538, 7501), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12911PolyExtStep::AndEqz(5380, 7502), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12912PolyExtStep::Sub(1, 2278), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12913PolyExtStep::Mul(2278, 7503), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12914PolyExtStep::AndEqz(5381, 7504), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12915PolyExtStep::Mul(7463, 20), // loc(callsite( builtin Mul at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12916PolyExtStep::Add(7505, 7477), // loc(callsite( builtin Add at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:27) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12917PolyExtStep::Sub(835, 7506), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12918PolyExtStep::AndEqz(5382, 7507), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12919PolyExtStep::Mul(7435, 20), // loc(callsite( builtin Mul at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:24) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12920PolyExtStep::Add(7508, 7449), // loc(callsite( builtin Add at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:28) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12921PolyExtStep::Sub(838, 7509), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12922PolyExtStep::AndEqz(5383, 7510), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
12923PolyExtStep::Mul(591, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12924PolyExtStep::Mul(594, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12925PolyExtStep::Mul(601, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12926PolyExtStep::Mul(615, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12927PolyExtStep::Mul(622, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12928PolyExtStep::Add(539, 7511), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12929PolyExtStep::Add(7516, 7512), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12930PolyExtStep::Add(7517, 7513), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12931PolyExtStep::Add(7518, 1726), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12932PolyExtStep::Add(7519, 7514), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12933PolyExtStep::Add(7520, 7515), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12934PolyExtStep::Add(7521, 1691), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12935PolyExtStep::Mul(649, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12936PolyExtStep::Mul(652, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12937PolyExtStep::Mul(659, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12938PolyExtStep::Mul(666, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12939PolyExtStep::Add(632, 708), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12940PolyExtStep::Add(7527, 1697), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12941PolyExtStep::Add(7528, 7523), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12942PolyExtStep::Add(7529, 7524), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12943PolyExtStep::Add(7530, 7525), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12944PolyExtStep::Add(7531, 7526), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12945PolyExtStep::Add(7532, 703), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12946PolyExtStep::Mul(544, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12947PolyExtStep::Mul(551, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12948PolyExtStep::Mul(552, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12949PolyExtStep::Mul(555, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12950PolyExtStep::Mul(556, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12951PolyExtStep::Mul(563, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12952PolyExtStep::Mul(564, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12953PolyExtStep::Add(676, 7534), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12954PolyExtStep::Add(7541, 7535), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12955PolyExtStep::Add(7542, 7536), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12956PolyExtStep::Add(7543, 7537), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12957PolyExtStep::Add(7544, 7538), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12958PolyExtStep::Add(7545, 7539), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12959PolyExtStep::Add(7546, 7540), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12960PolyExtStep::Mul(570, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12961PolyExtStep::Mul(572, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12962PolyExtStep::Mul(574, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12963PolyExtStep::Mul(575, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12964PolyExtStep::Mul(576, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12965PolyExtStep::Mul(577, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12966PolyExtStep::Add(571, 7548), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12967PolyExtStep::Add(7554, 7549), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12968PolyExtStep::Add(7555, 2192), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12969PolyExtStep::Add(7556, 7550), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12970PolyExtStep::Add(7557, 7551), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12971PolyExtStep::Add(7558, 7552), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12972PolyExtStep::Add(7559, 7553), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12973PolyExtStep::Sub(1, 539), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12974PolyExtStep::Mul(539, 7561), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12975PolyExtStep::AndEqz(5384, 7562), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12976PolyExtStep::AndEqz(5385, 593), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12977PolyExtStep::AndEqz(5386, 596), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12978PolyExtStep::AndEqz(5387, 603), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12979PolyExtStep::AndEqz(5388, 610), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12980PolyExtStep::AndEqz(5389, 617), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12981PolyExtStep::AndEqz(5390, 624), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12982PolyExtStep::AndEqz(5391, 631), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12983PolyExtStep::AndEqz(5392, 634), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12984PolyExtStep::AndEqz(5393, 641), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12985PolyExtStep::AndEqz(5394, 648), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12986PolyExtStep::AndEqz(5395, 651), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12987PolyExtStep::AndEqz(5396, 654), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12988PolyExtStep::AndEqz(5397, 661), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12989PolyExtStep::AndEqz(5398, 668), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12990PolyExtStep::AndEqz(5399, 675), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12991PolyExtStep::AndEqz(5400, 1679), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12992PolyExtStep::AndEqz(5401, 546), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12993PolyExtStep::Sub(1, 551), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12994PolyExtStep::Mul(551, 7563), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
12995PolyExtStep::AndEqz(5402, 7564), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12996PolyExtStep::AndEqz(5403, 1634), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12997PolyExtStep::AndEqz(5404, 558), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12998PolyExtStep::AndEqz(5405, 2927), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
12999PolyExtStep::AndEqz(5406, 1642), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13000PolyExtStep::AndEqz(5407, 2089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13001PolyExtStep::AndEqz(5408, 2091), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13002PolyExtStep::AndEqz(5409, 2097), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13003PolyExtStep::AndEqz(5410, 2103), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13004PolyExtStep::AndEqz(5411, 2109), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13005PolyExtStep::AndEqz(5412, 2115), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13006PolyExtStep::AndEqz(5413, 2121), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13007PolyExtStep::AndEqz(5414, 2123), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13008PolyExtStep::AndEqz(5415, 2129), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13009PolyExtStep::Mul(7547, 20), // loc(callsite( builtin Mul at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13010PolyExtStep::Add(7565, 7560), // loc(callsite( builtin Add at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:27) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13011PolyExtStep::Sub(893, 7566), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13012PolyExtStep::AndEqz(5416, 7567), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13013PolyExtStep::Mul(7522, 20), // loc(callsite( builtin Mul at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:24) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13014PolyExtStep::Add(7568, 7533), // loc(callsite( builtin Add at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:28) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13015PolyExtStep::Sub(896, 7569), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13016PolyExtStep::AndEqz(5417, 7570), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13017PolyExtStep::AndEqz(5418, 578), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13018PolyExtStep::AndEqz(5419, 587), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13019PolyExtStep::AndEqz(5420, 588), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13020PolyExtStep::AndEqz(5421, 739), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13021PolyExtStep::AndEqz(5422, 740), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13022PolyExtStep::AndEqz(5423, 741), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13023PolyExtStep::AndEqz(5424, 742), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13024PolyExtStep::AndEqz(5425, 743), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13025PolyExtStep::AndEqz(5426, 744), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13026PolyExtStep::AndEqz(5427, 745), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13027PolyExtStep::AndEqz(5428, 746), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13028PolyExtStep::AndEqz(5429, 747), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13029PolyExtStep::AndEqz(5430, 760), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13030PolyExtStep::AndEqz(5431, 766), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13031PolyExtStep::AndEqz(5432, 767), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13032PolyExtStep::AndEqz(5433, 768), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13033PolyExtStep::AndEqz(5434, 769), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13034PolyExtStep::AndEqz(5435, 761), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13035PolyExtStep::AndEqz(5436, 770), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13036PolyExtStep::AndEqz(5437, 771), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13037PolyExtStep::AndEqz(5438, 772), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13038PolyExtStep::AndEqz(5439, 756), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13039PolyExtStep::AndEqz(5440, 757), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13040PolyExtStep::AndEqz(5441, 762), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13041PolyExtStep::AndEqz(5442, 781), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13042PolyExtStep::AndEqz(5443, 732), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13043PolyExtStep::AndEqz(5444, 737), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13044PolyExtStep::AndEqz(5445, 764), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13045PolyExtStep::AndEqz(5446, 798), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13046PolyExtStep::AndEqz(5447, 800), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13047PolyExtStep::AndEqz(5448, 802), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13048PolyExtStep::AndEqz(5449, 804), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
13049PolyExtStep::AndEqz(5450, 984), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
13050PolyExtStep::AndEqz(5451, 999), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
13051PolyExtStep::AndEqz(5452, 1066), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
13052PolyExtStep::AndCond(5299, 380, 5453), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
13053PolyExtStep::Get(360), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13054PolyExtStep::Get(366), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13055PolyExtStep::Get(372), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13056PolyExtStep::Get(378), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13057PolyExtStep::Get(384), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13058PolyExtStep::Get(390), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13059PolyExtStep::Get(396), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13060PolyExtStep::Get(402), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13061PolyExtStep::Get(408), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13062PolyExtStep::Get(414), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13063PolyExtStep::Get(420), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13064PolyExtStep::Get(426), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13065PolyExtStep::Get(432), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13066PolyExtStep::Get(438), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13067PolyExtStep::Get(444), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13068PolyExtStep::Get(450), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13069PolyExtStep::Get(456), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13070PolyExtStep::Get(462), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13071PolyExtStep::Get(468), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13072PolyExtStep::Get(474), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13073PolyExtStep::Get(480), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13074PolyExtStep::Get(504), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13075PolyExtStep::Get(510), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13076PolyExtStep::Get(516), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13077PolyExtStep::Get(522), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13078PolyExtStep::Get(528), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13079PolyExtStep::Get(534), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13080PolyExtStep::Get(540), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13081PolyExtStep::Get(546), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13082PolyExtStep::Get(169), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13083PolyExtStep::Get(175), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13084PolyExtStep::Get(181), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13085PolyExtStep::Get(187), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13086PolyExtStep::Get(193), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13087PolyExtStep::Get(199), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13088PolyExtStep::Get(205), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13089PolyExtStep::Get(211), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13090PolyExtStep::Get(217), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13091PolyExtStep::Get(223), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13092PolyExtStep::Get(229), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13093PolyExtStep::Get(235), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13094PolyExtStep::Get(241), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13095PolyExtStep::Get(247), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13096PolyExtStep::Get(253), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13097PolyExtStep::Get(259), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13098PolyExtStep::Get(265), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13099PolyExtStep::Get(271), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13100PolyExtStep::Get(277), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13101PolyExtStep::Get(283), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13102PolyExtStep::Get(289), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13103PolyExtStep::Get(295), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13104PolyExtStep::Get(301), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13105PolyExtStep::Get(307), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13106PolyExtStep::Get(313), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13107PolyExtStep::Get(319), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13108PolyExtStep::Get(325), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13109PolyExtStep::Get(331), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13110PolyExtStep::Get(337), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13111PolyExtStep::Get(343), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13112PolyExtStep::Get(349), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13113PolyExtStep::Get(355), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13114PolyExtStep::Get(361), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13115PolyExtStep::Get(367), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13116PolyExtStep::Get(373), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13117PolyExtStep::Get(379), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13118PolyExtStep::Get(385), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13119PolyExtStep::Get(391), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13120PolyExtStep::Get(397), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13121PolyExtStep::Get(403), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13122PolyExtStep::Get(409), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13123PolyExtStep::Get(415), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13124PolyExtStep::Get(421), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13125PolyExtStep::Get(427), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13126PolyExtStep::Get(433), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13127PolyExtStep::Get(439), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13128PolyExtStep::Get(445), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13129PolyExtStep::Get(451), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13130PolyExtStep::Get(457), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13131PolyExtStep::Get(463), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13132PolyExtStep::Get(469), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13133PolyExtStep::Get(475), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13134PolyExtStep::Get(481), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13135PolyExtStep::Get(487), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13136PolyExtStep::Get(493), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13137PolyExtStep::Get(499), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13138PolyExtStep::Get(505), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13139PolyExtStep::Get(511), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13140PolyExtStep::Get(517), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13141PolyExtStep::Get(523), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13142PolyExtStep::Get(529), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13143PolyExtStep::Get(535), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13144PolyExtStep::Get(541), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13145PolyExtStep::Get(547), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13146PolyExtStep::Get(170), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13147PolyExtStep::Get(176), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13148PolyExtStep::Get(182), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13149PolyExtStep::Get(188), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13150PolyExtStep::Get(194), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13151PolyExtStep::Get(200), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13152PolyExtStep::Get(206), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13153PolyExtStep::Get(212), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13154PolyExtStep::Get(218), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13155PolyExtStep::Get(224), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13156PolyExtStep::Get(230), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13157PolyExtStep::Get(236), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13158PolyExtStep::Get(242), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13159PolyExtStep::Get(248), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13160PolyExtStep::Get(254), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13161PolyExtStep::Get(260), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13162PolyExtStep::Get(266), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13163PolyExtStep::Get(272), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13164PolyExtStep::Get(278), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13165PolyExtStep::Get(284), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13166PolyExtStep::Get(290), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13167PolyExtStep::Get(296), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13168PolyExtStep::Get(302), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13169PolyExtStep::Get(308), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13170PolyExtStep::Get(314), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13171PolyExtStep::Get(320), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13172PolyExtStep::Get(326), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13173PolyExtStep::Get(332), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13174PolyExtStep::Get(338), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13175PolyExtStep::Get(344), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13176PolyExtStep::Get(350), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13177PolyExtStep::Get(356), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13178PolyExtStep::Get(362), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13179PolyExtStep::Get(368), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13180PolyExtStep::Get(374), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13181PolyExtStep::Get(380), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13182PolyExtStep::Get(386), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13183PolyExtStep::Get(392), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13184PolyExtStep::Get(398), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13185PolyExtStep::Get(404), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13186PolyExtStep::Get(410), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13187PolyExtStep::Get(416), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13188PolyExtStep::Get(422), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13189PolyExtStep::Get(428), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13190PolyExtStep::Get(434), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13191PolyExtStep::Get(440), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13192PolyExtStep::Get(446), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13193PolyExtStep::Get(452), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13194PolyExtStep::Get(458), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13195PolyExtStep::Get(464), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13196PolyExtStep::Get(470), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13197PolyExtStep::Get(476), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13198PolyExtStep::Get(482), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13199PolyExtStep::Get(488), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13200PolyExtStep::Get(494), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13201PolyExtStep::Get(500), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13202PolyExtStep::Get(506), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13203PolyExtStep::Get(512), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13204PolyExtStep::Get(518), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13205PolyExtStep::Get(524), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13206PolyExtStep::Get(530), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13207PolyExtStep::Get(536), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13208PolyExtStep::Get(542), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13209PolyExtStep::Get(548), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13210PolyExtStep::Get(171), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13211PolyExtStep::Get(177), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13212PolyExtStep::Get(183), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13213PolyExtStep::Get(189), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13214PolyExtStep::Get(195), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13215PolyExtStep::Get(201), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13216PolyExtStep::Get(207), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13217PolyExtStep::Get(213), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13218PolyExtStep::Get(219), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13219PolyExtStep::Get(225), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13220PolyExtStep::Get(231), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13221PolyExtStep::Get(237), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13222PolyExtStep::Get(243), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13223PolyExtStep::Get(249), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13224PolyExtStep::Get(255), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13225PolyExtStep::Get(261), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13226PolyExtStep::Get(267), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13227PolyExtStep::Get(273), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13228PolyExtStep::Get(279), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13229PolyExtStep::Get(285), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13230PolyExtStep::Get(291), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13231PolyExtStep::Get(297), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13232PolyExtStep::Get(303), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13233PolyExtStep::Get(309), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13234PolyExtStep::Get(315), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13235PolyExtStep::Get(321), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13236PolyExtStep::Get(327), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13237PolyExtStep::Get(333), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13238PolyExtStep::Get(339), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13239PolyExtStep::Get(345), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13240PolyExtStep::Get(351), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13241PolyExtStep::Get(357), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13242PolyExtStep::Get(363), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13243PolyExtStep::Get(369), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13244PolyExtStep::Get(375), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13245PolyExtStep::Get(381), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13246PolyExtStep::Get(387), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13247PolyExtStep::Get(393), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13248PolyExtStep::Get(399), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13249PolyExtStep::Get(405), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13250PolyExtStep::Get(411), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13251PolyExtStep::Get(417), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13252PolyExtStep::Get(423), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13253PolyExtStep::Get(429), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13254PolyExtStep::Get(435), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13255PolyExtStep::Get(441), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13256PolyExtStep::Get(447), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13257PolyExtStep::Get(453), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13258PolyExtStep::Get(459), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13259PolyExtStep::Get(465), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13260PolyExtStep::Get(471), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13261PolyExtStep::Get(477), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13262PolyExtStep::Get(483), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13263PolyExtStep::Get(489), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13264PolyExtStep::Get(495), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13265PolyExtStep::Get(501), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13266PolyExtStep::Get(507), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13267PolyExtStep::Get(513), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13268PolyExtStep::Get(519), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13269PolyExtStep::Get(525), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13270PolyExtStep::Get(531), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13271PolyExtStep::Get(537), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13272PolyExtStep::Get(543), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13273PolyExtStep::Get(549), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13274PolyExtStep::Sub(36, 4036), // loc(callsite( builtin Sub at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13275PolyExtStep::Mul(7792, 1087), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13276PolyExtStep::Sub(7793, 1085), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13277PolyExtStep::AndEqz(5300, 7794), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13278PolyExtStep::Mul(1084, 7792), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13279PolyExtStep::AndEqz(5455, 7795), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13280PolyExtStep::AndEqz(5456, 7391), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13281PolyExtStep::Add(4035, 4036), // loc(callsite( builtin Add at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:32) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13282PolyExtStep::AndEqz(5457, 7331), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13283PolyExtStep::AndEqz(5458, 3893), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13284PolyExtStep::AndEqz(5459, 7332), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13285PolyExtStep::AndEqz(5460, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13286PolyExtStep::Sub(817, 7796), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13287PolyExtStep::AndEqz(5461, 7797), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13288PolyExtStep::AndEqz(5462, 4091), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13289PolyExtStep::AndEqz(5463, 7334), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13290PolyExtStep::AndEqz(5464, 4828), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13291PolyExtStep::AndEqz(5465, 7336), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13292PolyExtStep::AndEqz(5466, 7340), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13293PolyExtStep::AndEqz(5467, 3992), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13294PolyExtStep::AndEqz(5468, 7341), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13295PolyExtStep::AndEqz(5469, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13296PolyExtStep::Sub(844, 4033), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13297PolyExtStep::AndEqz(5470, 7798), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13298PolyExtStep::AndEqz(5471, 7343), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13299PolyExtStep::AndEqz(5472, 7344), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13300PolyExtStep::AndEqz(5473, 7347), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13301PolyExtStep::AndEqz(5474, 7348), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13302PolyExtStep::Mul(587, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13303PolyExtStep::Mul(588, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13304PolyExtStep::Mul(740, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13305PolyExtStep::Mul(741, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13306PolyExtStep::Mul(742, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13307PolyExtStep::Mul(743, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13308PolyExtStep::Add(578, 7799), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13309PolyExtStep::Add(7805, 7800), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13310PolyExtStep::Add(7806, 2196), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13311PolyExtStep::Add(7807, 7801), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13312PolyExtStep::Add(7808, 7802), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13313PolyExtStep::Add(7809, 7803), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13314PolyExtStep::Add(7810, 7804), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13315PolyExtStep::Mul(745, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13316PolyExtStep::Mul(746, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13317PolyExtStep::Mul(747, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13318PolyExtStep::Mul(760, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13319PolyExtStep::Mul(766, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13320PolyExtStep::Mul(767, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13321PolyExtStep::Mul(768, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13322PolyExtStep::Add(744, 7812), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13323PolyExtStep::Add(7819, 7813), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13324PolyExtStep::Add(7820, 7814), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13325PolyExtStep::Add(7821, 7815), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13326PolyExtStep::Add(7822, 7816), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13327PolyExtStep::Add(7823, 7817), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13328PolyExtStep::Add(7824, 7818), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13329PolyExtStep::Mul(761, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13330PolyExtStep::Mul(770, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13331PolyExtStep::Mul(771, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13332PolyExtStep::Mul(772, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13333PolyExtStep::Mul(756, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13334PolyExtStep::Mul(757, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13335PolyExtStep::Mul(762, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13336PolyExtStep::Add(769, 7826), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13337PolyExtStep::Add(7833, 7827), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13338PolyExtStep::Add(7834, 7828), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13339PolyExtStep::Add(7835, 7829), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13340PolyExtStep::Add(7836, 7830), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13341PolyExtStep::Add(7837, 7831), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13342PolyExtStep::Add(7838, 7832), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13343PolyExtStep::Mul(732, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13344PolyExtStep::Mul(737, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13345PolyExtStep::Mul(764, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13346PolyExtStep::Mul(798, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13347PolyExtStep::Mul(800, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13348PolyExtStep::Mul(802, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13349PolyExtStep::Mul(804, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13350PolyExtStep::Add(781, 7840), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13351PolyExtStep::Add(7847, 7841), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13352PolyExtStep::Add(7848, 7842), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13353PolyExtStep::Add(7849, 7843), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13354PolyExtStep::Add(7850, 7844), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13355PolyExtStep::Add(7851, 7845), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13356PolyExtStep::Add(7852, 7846), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13357PolyExtStep::AndEqz(5475, 2135), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13358PolyExtStep::AndEqz(5476, 2137), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13359PolyExtStep::AndEqz(5477, 2139), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13360PolyExtStep::AndEqz(5478, 2145), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13361PolyExtStep::AndEqz(5479, 2151), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13362PolyExtStep::AndEqz(5480, 2157), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13363PolyExtStep::AndEqz(5481, 3068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13364PolyExtStep::AndEqz(5482, 2068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13365PolyExtStep::AndEqz(5483, 3574), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13366PolyExtStep::AndEqz(5484, 3074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13367PolyExtStep::AndEqz(5485, 2075), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13368PolyExtStep::AndEqz(5486, 3079), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13369PolyExtStep::AndEqz(5487, 2969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13370PolyExtStep::AndEqz(5488, 3001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13371PolyExtStep::AndEqz(5489, 3085), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13372PolyExtStep::AndEqz(5490, 3626), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13373PolyExtStep::AndEqz(5491, 3628), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13374PolyExtStep::AndEqz(5492, 3639), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13375PolyExtStep::AndEqz(5493, 3679), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13376PolyExtStep::AndEqz(5494, 3683), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13377PolyExtStep::Sub(1, 772), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13378PolyExtStep::Mul(772, 7854), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13379PolyExtStep::AndEqz(5495, 7855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13380PolyExtStep::Sub(1, 756), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13381PolyExtStep::Mul(756, 7856), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13382PolyExtStep::AndEqz(5496, 7857), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13383PolyExtStep::Sub(1, 757), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13384PolyExtStep::Mul(757, 7858), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13385PolyExtStep::AndEqz(5497, 7859), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13386PolyExtStep::Sub(1, 762), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13387PolyExtStep::Mul(762, 7860), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13388PolyExtStep::AndEqz(5498, 7861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13389PolyExtStep::AndEqz(5499, 3745), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13390PolyExtStep::AndEqz(5500, 734), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13391PolyExtStep::AndEqz(5501, 4987), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13392PolyExtStep::AndEqz(5502, 1735), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13393PolyExtStep::AndEqz(5503, 4989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13394PolyExtStep::AndEqz(5504, 3022), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13395PolyExtStep::AndEqz(5505, 4991), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13396PolyExtStep::AndEqz(5506, 3872), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13397PolyExtStep::Mul(7839, 20), // loc(callsite( builtin Mul at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13398PolyExtStep::Add(7862, 7853), // loc(callsite( builtin Add at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:27) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13399PolyExtStep::Sub(893, 7863), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:13) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13400PolyExtStep::AndEqz(5507, 7864), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:13) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13401PolyExtStep::Mul(7811, 20), // loc(callsite( builtin Mul at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:24) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13402PolyExtStep::Add(7865, 7825), // loc(callsite( builtin Add at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
13403PolyExtStep::Sub(896, 7866), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:14) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13404PolyExtStep::AndEqz(5508, 7867), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:14) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
13405PolyExtStep::Add(4123, 4132), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13406PolyExtStep::Mul(4123, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13407PolyExtStep::Mul(7869, 4132), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13408PolyExtStep::Sub(7868, 7870), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13409PolyExtStep::Add(4124, 4133), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13410PolyExtStep::Mul(4124, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13411PolyExtStep::Mul(7873, 4133), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13412PolyExtStep::Sub(7872, 7874), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13413PolyExtStep::Add(4125, 4134), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13414PolyExtStep::Mul(4125, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13415PolyExtStep::Mul(7877, 4134), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13416PolyExtStep::Sub(7876, 7878), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13417PolyExtStep::Add(4126, 4135), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13418PolyExtStep::Mul(4126, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13419PolyExtStep::Mul(7881, 4135), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13420PolyExtStep::Sub(7880, 7882), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13421PolyExtStep::Add(4127, 4136), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13422PolyExtStep::Mul(4127, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13423PolyExtStep::Mul(7885, 4136), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13424PolyExtStep::Sub(7884, 7886), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13425PolyExtStep::Add(4128, 4137), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13426PolyExtStep::Mul(4128, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13427PolyExtStep::Mul(7889, 4137), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13428PolyExtStep::Sub(7888, 7890), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13429PolyExtStep::Add(4129, 4145), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13430PolyExtStep::Mul(4129, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13431PolyExtStep::Mul(7893, 4145), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13432PolyExtStep::Sub(7892, 7894), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13433PolyExtStep::Add(4130, 4142), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13434PolyExtStep::Mul(4130, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13435PolyExtStep::Mul(7897, 4142), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13436PolyExtStep::Sub(7896, 7898), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13437PolyExtStep::Add(4131, 4139), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13438PolyExtStep::Mul(4167, 4139), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13439PolyExtStep::Sub(7900, 7901), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13440PolyExtStep::Add(4132, 4138), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13441PolyExtStep::Mul(4132, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13442PolyExtStep::Mul(7904, 4138), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13443PolyExtStep::Sub(7903, 7905), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13444PolyExtStep::Add(4133, 4113), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13445PolyExtStep::Mul(4169, 4113), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13446PolyExtStep::Sub(7907, 7908), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13447PolyExtStep::Add(4134, 4037), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13448PolyExtStep::Mul(4134, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13449PolyExtStep::Mul(7911, 4037), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13450PolyExtStep::Sub(7910, 7912), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13451PolyExtStep::Add(4135, 4038), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13452PolyExtStep::Mul(4179, 4038), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13453PolyExtStep::Sub(7914, 7915), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13454PolyExtStep::Add(4136, 4039), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13455PolyExtStep::Mul(4136, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13456PolyExtStep::Mul(7918, 4039), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13457PolyExtStep::Sub(7917, 7919), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13458PolyExtStep::Add(4137, 4114), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13459PolyExtStep::Mul(4181, 4114), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13460PolyExtStep::Sub(7921, 7922), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13461PolyExtStep::Add(4145, 4115), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13462PolyExtStep::Mul(4145, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13463PolyExtStep::Mul(7925, 4115), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13464PolyExtStep::Sub(7924, 7926), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13465PolyExtStep::Add(4142, 4116), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13466PolyExtStep::Mul(4142, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13467PolyExtStep::Mul(7929, 4116), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13468PolyExtStep::Sub(7928, 7930), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13469PolyExtStep::Add(4139, 4117), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13470PolyExtStep::Mul(4139, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13471PolyExtStep::Mul(7933, 4117), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13472PolyExtStep::Sub(7932, 7934), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13473PolyExtStep::Add(4138, 4118), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13474PolyExtStep::Mul(4138, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13475PolyExtStep::Mul(7937, 4118), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13476PolyExtStep::Sub(7936, 7938), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13477PolyExtStep::Add(4113, 4119), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13478PolyExtStep::Mul(4113, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13479PolyExtStep::Mul(7941, 4119), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13480PolyExtStep::Sub(7940, 7942), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13481PolyExtStep::Add(4037, 4120), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13482PolyExtStep::Mul(4037, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13483PolyExtStep::Mul(7945, 4120), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13484PolyExtStep::Sub(7944, 7946), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13485PolyExtStep::Add(4038, 4121), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13486PolyExtStep::Mul(4038, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13487PolyExtStep::Mul(7949, 4121), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13488PolyExtStep::Sub(7948, 7950), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13489PolyExtStep::Add(4039, 4122), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13490PolyExtStep::Mul(4039, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13491PolyExtStep::Mul(7953, 4122), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13492PolyExtStep::Sub(7952, 7954), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13493PolyExtStep::Add(4114, 4123), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13494PolyExtStep::Mul(4114, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13495PolyExtStep::Mul(7957, 4123), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13496PolyExtStep::Sub(7956, 7958), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13497PolyExtStep::Add(4115, 4124), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13498PolyExtStep::Mul(4612, 4124), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13499PolyExtStep::Sub(7960, 7961), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13500PolyExtStep::Add(4116, 4125), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13501PolyExtStep::Mul(4116, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13502PolyExtStep::Mul(7964, 4125), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13503PolyExtStep::Sub(7963, 7965), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13504PolyExtStep::Add(4117, 4126), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13505PolyExtStep::Mul(4614, 4126), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13506PolyExtStep::Sub(7967, 7968), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13507PolyExtStep::Add(4118, 4127), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13508PolyExtStep::Mul(4118, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13509PolyExtStep::Mul(7971, 4127), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13510PolyExtStep::Sub(7970, 7972), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13511PolyExtStep::Add(4119, 4128), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13512PolyExtStep::Mul(4624, 4128), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13513PolyExtStep::Sub(7974, 7975), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13514PolyExtStep::Add(4120, 4129), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13515PolyExtStep::Mul(4120, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13516PolyExtStep::Mul(7978, 4129), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13517PolyExtStep::Sub(7977, 7979), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13518PolyExtStep::Add(4121, 4130), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13519PolyExtStep::Mul(4626, 4130), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13520PolyExtStep::Sub(7981, 7982), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13521PolyExtStep::Add(4122, 4131), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13522PolyExtStep::Mul(4122, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13523PolyExtStep::Mul(7985, 4131), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13524PolyExtStep::Sub(7984, 7986), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13525PolyExtStep::Add(4038, 7871), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13526PolyExtStep::Mul(7949, 7871), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13527PolyExtStep::Sub(7988, 7989), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13528PolyExtStep::Add(4039, 7875), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13529PolyExtStep::Mul(7953, 7875), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13530PolyExtStep::Sub(7991, 7992), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13531PolyExtStep::Add(4114, 7879), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13532PolyExtStep::Mul(7957, 7879), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13533PolyExtStep::Sub(7994, 7995), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13534PolyExtStep::Add(4115, 7883), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13535PolyExtStep::Mul(4612, 7883), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13536PolyExtStep::Sub(7997, 7998), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13537PolyExtStep::Add(4116, 7887), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13538PolyExtStep::Mul(7964, 7887), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13539PolyExtStep::Sub(8000, 8001), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13540PolyExtStep::Add(4117, 7891), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13541PolyExtStep::Mul(4614, 7891), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13542PolyExtStep::Sub(8003, 8004), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13543PolyExtStep::Add(4118, 7895), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13544PolyExtStep::Mul(7971, 7895), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13545PolyExtStep::Sub(8006, 8007), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13546PolyExtStep::Add(4119, 7899), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13547PolyExtStep::Mul(4624, 7899), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13548PolyExtStep::Sub(8009, 8010), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13549PolyExtStep::Add(4120, 7902), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13550PolyExtStep::Mul(7978, 7902), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13551PolyExtStep::Sub(8012, 8013), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13552PolyExtStep::Add(4121, 7906), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13553PolyExtStep::Mul(4626, 7906), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13554PolyExtStep::Sub(8015, 8016), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13555PolyExtStep::Add(4122, 7909), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13556PolyExtStep::Mul(7985, 7909), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13557PolyExtStep::Sub(8018, 8019), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13558PolyExtStep::Add(4123, 7913), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13559PolyExtStep::Mul(7869, 7913), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13560PolyExtStep::Sub(8021, 8022), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13561PolyExtStep::Add(4124, 7916), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13562PolyExtStep::Mul(7873, 7916), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13563PolyExtStep::Sub(8024, 8025), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13564PolyExtStep::Add(4125, 7920), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13565PolyExtStep::Mul(7877, 7920), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13566PolyExtStep::Sub(8027, 8028), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13567PolyExtStep::Add(4126, 7923), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13568PolyExtStep::Mul(7881, 7923), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13569PolyExtStep::Sub(8030, 8031), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13570PolyExtStep::Add(4127, 7927), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13571PolyExtStep::Mul(7885, 7927), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13572PolyExtStep::Sub(8033, 8034), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13573PolyExtStep::Add(4128, 7931), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13574PolyExtStep::Mul(7889, 7931), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13575PolyExtStep::Sub(8036, 8037), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13576PolyExtStep::Add(4129, 7935), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13577PolyExtStep::Mul(7893, 7935), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13578PolyExtStep::Sub(8039, 8040), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13579PolyExtStep::Add(4130, 7939), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13580PolyExtStep::Mul(7897, 7939), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13581PolyExtStep::Sub(8042, 8043), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13582PolyExtStep::Add(4131, 7943), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13583PolyExtStep::Mul(4167, 7943), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13584PolyExtStep::Sub(8045, 8046), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13585PolyExtStep::Add(4132, 7947), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13586PolyExtStep::Mul(7904, 7947), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13587PolyExtStep::Sub(8048, 8049), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13588PolyExtStep::Add(4133, 7951), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13589PolyExtStep::Mul(4169, 7951), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13590PolyExtStep::Sub(8051, 8052), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13591PolyExtStep::Add(4134, 7955), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13592PolyExtStep::Mul(7911, 7955), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13593PolyExtStep::Sub(8054, 8055), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13594PolyExtStep::Add(4135, 7959), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13595PolyExtStep::Mul(4179, 7959), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13596PolyExtStep::Sub(8057, 8058), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13597PolyExtStep::Add(4136, 7962), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13598PolyExtStep::Mul(7918, 7962), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13599PolyExtStep::Sub(8060, 8061), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13600PolyExtStep::Add(4137, 7966), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13601PolyExtStep::Mul(4181, 7966), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13602PolyExtStep::Sub(8063, 8064), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13603PolyExtStep::Add(4145, 7969), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13604PolyExtStep::Mul(7925, 7969), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13605PolyExtStep::Sub(8066, 8067), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13606PolyExtStep::Add(4142, 7973), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13607PolyExtStep::Mul(7929, 7973), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13608PolyExtStep::Sub(8069, 8070), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13609PolyExtStep::Add(4139, 7976), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13610PolyExtStep::Mul(7933, 7976), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13611PolyExtStep::Sub(8072, 8073), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13612PolyExtStep::Add(4138, 7980), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13613PolyExtStep::Mul(7937, 7980), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13614PolyExtStep::Sub(8075, 8076), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13615PolyExtStep::Add(4113, 7983), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13616PolyExtStep::Mul(7941, 7983), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13617PolyExtStep::Sub(8078, 8079), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13618PolyExtStep::Add(4037, 7987), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13619PolyExtStep::Mul(7945, 7987), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13620PolyExtStep::Sub(8081, 8082), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13621PolyExtStep::Add(7582, 7593), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13622PolyExtStep::Mul(7582, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13623PolyExtStep::Mul(8085, 7593), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13624PolyExtStep::Sub(8084, 8086), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13625PolyExtStep::Add(7583, 7594), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13626PolyExtStep::Mul(7583, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13627PolyExtStep::Mul(8089, 7594), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13628PolyExtStep::Sub(8088, 8090), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13629PolyExtStep::Add(7584, 7595), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13630PolyExtStep::Mul(7584, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13631PolyExtStep::Mul(8093, 7595), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13632PolyExtStep::Sub(8092, 8094), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13633PolyExtStep::Add(7585, 7596), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13634PolyExtStep::Mul(7585, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13635PolyExtStep::Mul(8097, 7596), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13636PolyExtStep::Sub(8096, 8098), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13637PolyExtStep::Add(7586, 7597), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13638PolyExtStep::Mul(7586, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13639PolyExtStep::Mul(8101, 7597), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13640PolyExtStep::Sub(8100, 8102), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13641PolyExtStep::Add(7587, 7598), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13642PolyExtStep::Mul(7587, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13643PolyExtStep::Mul(8105, 7598), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13644PolyExtStep::Sub(8104, 8106), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13645PolyExtStep::Add(7588, 7599), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13646PolyExtStep::Mul(7588, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13647PolyExtStep::Mul(8109, 7599), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13648PolyExtStep::Sub(8108, 8110), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13649PolyExtStep::Add(7589, 7571), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13650PolyExtStep::Mul(7589, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13651PolyExtStep::Mul(8113, 7571), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13652PolyExtStep::Sub(8112, 8114), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13653PolyExtStep::Add(7590, 7572), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13654PolyExtStep::Mul(7590, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13655PolyExtStep::Mul(8117, 7572), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13656PolyExtStep::Sub(8116, 8118), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13657PolyExtStep::Add(7591, 7573), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13658PolyExtStep::Mul(7591, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13659PolyExtStep::Mul(8121, 7573), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13660PolyExtStep::Sub(8120, 8122), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13661PolyExtStep::Add(3654, 7574), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13662PolyExtStep::Mul(3654, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13663PolyExtStep::Mul(8125, 7574), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13664PolyExtStep::Sub(8124, 8126), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13665PolyExtStep::Add(3655, 7575), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13666PolyExtStep::Mul(3655, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13667PolyExtStep::Mul(8129, 7575), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13668PolyExtStep::Sub(8128, 8130), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13669PolyExtStep::Add(3656, 7576), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13670PolyExtStep::Mul(3656, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13671PolyExtStep::Mul(8133, 7576), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13672PolyExtStep::Sub(8132, 8134), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13673PolyExtStep::Add(7592, 7577), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13674PolyExtStep::Mul(7592, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13675PolyExtStep::Mul(8137, 7577), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13676PolyExtStep::Sub(8136, 8138), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13677PolyExtStep::Add(7593, 7578), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13678PolyExtStep::Mul(7593, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13679PolyExtStep::Mul(8141, 7578), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13680PolyExtStep::Sub(8140, 8142), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13681PolyExtStep::Add(7594, 7579), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13682PolyExtStep::Mul(7594, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13683PolyExtStep::Mul(8145, 7579), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13684PolyExtStep::Sub(8144, 8146), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13685PolyExtStep::Add(7595, 7580), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13686PolyExtStep::Mul(7595, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13687PolyExtStep::Mul(8149, 7580), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13688PolyExtStep::Sub(8148, 8150), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13689PolyExtStep::Add(7596, 7581), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13690PolyExtStep::Mul(7596, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13691PolyExtStep::Mul(8153, 7581), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13692PolyExtStep::Sub(8152, 8154), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13693PolyExtStep::Add(7597, 7582), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13694PolyExtStep::Mul(7597, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13695PolyExtStep::Mul(8157, 7582), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13696PolyExtStep::Sub(8156, 8158), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13697PolyExtStep::Add(7598, 7583), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13698PolyExtStep::Mul(7598, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13699PolyExtStep::Mul(8161, 7583), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13700PolyExtStep::Sub(8160, 8162), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13701PolyExtStep::Add(7599, 7584), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13702PolyExtStep::Mul(7599, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13703PolyExtStep::Mul(8165, 7584), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13704PolyExtStep::Sub(8164, 8166), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13705PolyExtStep::Add(7571, 7585), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13706PolyExtStep::Mul(7571, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13707PolyExtStep::Mul(8169, 7585), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13708PolyExtStep::Sub(8168, 8170), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13709PolyExtStep::Add(7572, 7586), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13710PolyExtStep::Mul(7572, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13711PolyExtStep::Mul(8173, 7586), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13712PolyExtStep::Sub(8172, 8174), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13713PolyExtStep::Add(7573, 7587), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13714PolyExtStep::Mul(7573, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13715PolyExtStep::Mul(8177, 7587), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13716PolyExtStep::Sub(8176, 8178), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13717PolyExtStep::Add(7574, 7588), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13718PolyExtStep::Mul(7574, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13719PolyExtStep::Mul(8181, 7588), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13720PolyExtStep::Sub(8180, 8182), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13721PolyExtStep::Add(7575, 7589), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13722PolyExtStep::Mul(7575, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13723PolyExtStep::Mul(8185, 7589), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13724PolyExtStep::Sub(8184, 8186), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13725PolyExtStep::Add(7576, 7590), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13726PolyExtStep::Mul(7576, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13727PolyExtStep::Mul(8189, 7590), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13728PolyExtStep::Sub(8188, 8190), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13729PolyExtStep::Add(7577, 7591), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13730PolyExtStep::Mul(7577, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13731PolyExtStep::Mul(8193, 7591), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13732PolyExtStep::Sub(8192, 8194), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13733PolyExtStep::Add(7578, 3654), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13734PolyExtStep::Mul(7578, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13735PolyExtStep::Mul(8197, 3654), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13736PolyExtStep::Sub(8196, 8198), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13737PolyExtStep::Add(7579, 3655), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13738PolyExtStep::Mul(7579, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13739PolyExtStep::Mul(8201, 3655), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13740PolyExtStep::Sub(8200, 8202), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13741PolyExtStep::Add(7580, 3656), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13742PolyExtStep::Mul(7580, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13743PolyExtStep::Mul(8205, 3656), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13744PolyExtStep::Sub(8204, 8206), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13745PolyExtStep::Add(7581, 7592), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13746PolyExtStep::Mul(7581, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13747PolyExtStep::Mul(8209, 7592), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13748PolyExtStep::Sub(8208, 8210), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13749PolyExtStep::Add(7577, 8087), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13750PolyExtStep::Mul(8193, 8087), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13751PolyExtStep::Sub(8212, 8213), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13752PolyExtStep::Add(7578, 8091), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13753PolyExtStep::Mul(8197, 8091), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13754PolyExtStep::Sub(8215, 8216), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13755PolyExtStep::Add(7579, 8095), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13756PolyExtStep::Mul(8201, 8095), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13757PolyExtStep::Sub(8218, 8219), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13758PolyExtStep::Add(7580, 8099), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13759PolyExtStep::Mul(8205, 8099), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13760PolyExtStep::Sub(8221, 8222), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13761PolyExtStep::Add(7581, 8103), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13762PolyExtStep::Mul(8209, 8103), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13763PolyExtStep::Sub(8224, 8225), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13764PolyExtStep::Add(7582, 8107), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13765PolyExtStep::Mul(8085, 8107), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13766PolyExtStep::Sub(8227, 8228), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13767PolyExtStep::Add(7583, 8111), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13768PolyExtStep::Mul(8089, 8111), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13769PolyExtStep::Sub(8230, 8231), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13770PolyExtStep::Add(7584, 8115), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13771PolyExtStep::Mul(8093, 8115), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13772PolyExtStep::Sub(8233, 8234), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13773PolyExtStep::Add(7585, 8119), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13774PolyExtStep::Mul(8097, 8119), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13775PolyExtStep::Sub(8236, 8237), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13776PolyExtStep::Add(7586, 8123), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13777PolyExtStep::Mul(8101, 8123), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13778PolyExtStep::Sub(8239, 8240), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13779PolyExtStep::Add(7587, 8127), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13780PolyExtStep::Mul(8105, 8127), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13781PolyExtStep::Sub(8242, 8243), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13782PolyExtStep::Add(7588, 8131), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13783PolyExtStep::Mul(8109, 8131), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13784PolyExtStep::Sub(8245, 8246), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13785PolyExtStep::Add(7589, 8135), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13786PolyExtStep::Mul(8113, 8135), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13787PolyExtStep::Sub(8248, 8249), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13788PolyExtStep::Add(7590, 8139), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13789PolyExtStep::Mul(8117, 8139), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13790PolyExtStep::Sub(8251, 8252), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13791PolyExtStep::Add(7591, 8143), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13792PolyExtStep::Mul(8121, 8143), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13793PolyExtStep::Sub(8254, 8255), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13794PolyExtStep::Add(3654, 8147), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13795PolyExtStep::Mul(8125, 8147), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13796PolyExtStep::Sub(8257, 8258), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13797PolyExtStep::Add(3655, 8151), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13798PolyExtStep::Mul(8129, 8151), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13799PolyExtStep::Sub(8260, 8261), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13800PolyExtStep::Add(3656, 8155), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13801PolyExtStep::Mul(8133, 8155), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13802PolyExtStep::Sub(8263, 8264), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13803PolyExtStep::Add(7592, 8159), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13804PolyExtStep::Mul(8137, 8159), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13805PolyExtStep::Sub(8266, 8267), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13806PolyExtStep::Add(7593, 8163), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13807PolyExtStep::Mul(8141, 8163), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13808PolyExtStep::Sub(8269, 8270), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13809PolyExtStep::Add(7594, 8167), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13810PolyExtStep::Mul(8145, 8167), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13811PolyExtStep::Sub(8272, 8273), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13812PolyExtStep::Add(7595, 8171), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13813PolyExtStep::Mul(8149, 8171), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13814PolyExtStep::Sub(8275, 8276), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13815PolyExtStep::Add(7596, 8175), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13816PolyExtStep::Mul(8153, 8175), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13817PolyExtStep::Sub(8278, 8279), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13818PolyExtStep::Add(7597, 8179), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13819PolyExtStep::Mul(8157, 8179), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13820PolyExtStep::Sub(8281, 8282), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13821PolyExtStep::Add(7598, 8183), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13822PolyExtStep::Mul(8161, 8183), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13823PolyExtStep::Sub(8284, 8285), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13824PolyExtStep::Add(7599, 8187), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13825PolyExtStep::Mul(8165, 8187), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13826PolyExtStep::Sub(8287, 8288), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13827PolyExtStep::Add(7571, 8191), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13828PolyExtStep::Mul(8169, 8191), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13829PolyExtStep::Sub(8290, 8291), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13830PolyExtStep::Add(7572, 8195), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13831PolyExtStep::Mul(8173, 8195), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13832PolyExtStep::Sub(8293, 8294), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13833PolyExtStep::Add(7573, 8199), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13834PolyExtStep::Mul(8177, 8199), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13835PolyExtStep::Sub(8296, 8297), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13836PolyExtStep::Add(7574, 8203), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13837PolyExtStep::Mul(8181, 8203), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13838PolyExtStep::Sub(8299, 8300), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13839PolyExtStep::Add(7575, 8207), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13840PolyExtStep::Mul(8185, 8207), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13841PolyExtStep::Sub(8302, 8303), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13842PolyExtStep::Add(7576, 8211), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13843PolyExtStep::Mul(8189, 8211), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13844PolyExtStep::Sub(8305, 8306), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13845PolyExtStep::Mul(744, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13846PolyExtStep::Mul(745, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13847PolyExtStep::Mul(746, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13848PolyExtStep::Mul(747, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13849PolyExtStep::Mul(760, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13850PolyExtStep::Mul(766, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13851PolyExtStep::Mul(767, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13852PolyExtStep::Mul(768, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13853PolyExtStep::Add(7811, 8308), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13854PolyExtStep::Add(8316, 8309), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13855PolyExtStep::Add(8317, 8310), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13856PolyExtStep::Add(8318, 8311), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13857PolyExtStep::Add(8319, 8312), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13858PolyExtStep::Add(8320, 8313), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13859PolyExtStep::Add(8321, 8314), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13860PolyExtStep::Add(8322, 8315), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13861PolyExtStep::Mul(781, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13862PolyExtStep::Mul(732, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13863PolyExtStep::Mul(737, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13864PolyExtStep::Mul(764, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13865PolyExtStep::Mul(798, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13866PolyExtStep::Mul(800, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13867PolyExtStep::Mul(802, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13868PolyExtStep::Mul(804, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13869PolyExtStep::Add(7839, 8324), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13870PolyExtStep::Add(8332, 8325), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13871PolyExtStep::Add(8333, 8326), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13872PolyExtStep::Add(8334, 8327), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13873PolyExtStep::Add(8335, 8328), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13874PolyExtStep::Add(8336, 8329), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13875PolyExtStep::Add(8337, 8330), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13876PolyExtStep::Add(8338, 8331), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13877PolyExtStep::Mul(7761, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13878PolyExtStep::Mul(7762, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13879PolyExtStep::Mul(7763, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13880PolyExtStep::Mul(7764, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13881PolyExtStep::Mul(7765, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13882PolyExtStep::Mul(7766, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13883PolyExtStep::Mul(7767, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13884PolyExtStep::Mul(7768, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13885PolyExtStep::Mul(7769, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13886PolyExtStep::Mul(7770, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13887PolyExtStep::Mul(7771, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13888PolyExtStep::Mul(7772, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13889PolyExtStep::Mul(7773, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13890PolyExtStep::Mul(7774, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13891PolyExtStep::Mul(7775, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13892PolyExtStep::Add(7760, 8340), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13893PolyExtStep::Add(8355, 8341), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13894PolyExtStep::Add(8356, 8342), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13895PolyExtStep::Add(8357, 8343), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13896PolyExtStep::Add(8358, 8344), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13897PolyExtStep::Add(8359, 8345), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13898PolyExtStep::Add(8360, 8346), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13899PolyExtStep::Add(8361, 8347), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13900PolyExtStep::Add(8362, 8348), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13901PolyExtStep::Add(8363, 8349), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13902PolyExtStep::Add(8364, 8350), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13903PolyExtStep::Add(8365, 8351), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13904PolyExtStep::Add(8366, 8352), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13905PolyExtStep::Add(8367, 8353), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13906PolyExtStep::Add(8368, 8354), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13907PolyExtStep::Mul(7777, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13908PolyExtStep::Mul(7778, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13909PolyExtStep::Mul(7779, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13910PolyExtStep::Mul(7780, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13911PolyExtStep::Mul(7781, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13912PolyExtStep::Mul(7782, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13913PolyExtStep::Mul(7783, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13914PolyExtStep::Mul(7784, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13915PolyExtStep::Mul(7785, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13916PolyExtStep::Mul(7786, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13917PolyExtStep::Mul(7787, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13918PolyExtStep::Mul(7788, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13919PolyExtStep::Mul(7789, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13920PolyExtStep::Mul(7790, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13921PolyExtStep::Mul(7791, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13922PolyExtStep::Add(7776, 8370), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13923PolyExtStep::Add(8385, 8371), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13924PolyExtStep::Add(8386, 8372), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13925PolyExtStep::Add(8387, 8373), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13926PolyExtStep::Add(8388, 8374), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13927PolyExtStep::Add(8389, 8375), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13928PolyExtStep::Add(8390, 8376), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13929PolyExtStep::Add(8391, 8377), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13930PolyExtStep::Add(8392, 8378), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13931PolyExtStep::Add(8393, 8379), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13932PolyExtStep::Add(8394, 8380), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13933PolyExtStep::Add(8395, 8381), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13934PolyExtStep::Add(8396, 8382), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13935PolyExtStep::Add(8397, 8383), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13936PolyExtStep::Add(8398, 8384), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
13937PolyExtStep::Mul(7571, 7632), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13938PolyExtStep::Sub(1, 7571), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13939PolyExtStep::Mul(8401, 7696), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13940PolyExtStep::Add(8400, 8402), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13941PolyExtStep::Mul(7572, 7633), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13942PolyExtStep::Sub(1, 7572), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13943PolyExtStep::Mul(8405, 7697), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13944PolyExtStep::Add(8404, 8406), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13945PolyExtStep::Mul(7573, 7634), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13946PolyExtStep::Sub(1, 7573), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13947PolyExtStep::Mul(8409, 7698), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13948PolyExtStep::Add(8408, 8410), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13949PolyExtStep::Mul(7574, 7635), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13950PolyExtStep::Sub(1, 7574), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13951PolyExtStep::Mul(8413, 7699), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13952PolyExtStep::Add(8412, 8414), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13953PolyExtStep::Mul(7575, 7636), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13954PolyExtStep::Sub(1, 7575), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13955PolyExtStep::Mul(8417, 7700), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13956PolyExtStep::Add(8416, 8418), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13957PolyExtStep::Mul(7576, 7637), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13958PolyExtStep::Sub(1, 7576), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13959PolyExtStep::Mul(8421, 7701), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13960PolyExtStep::Add(8420, 8422), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13961PolyExtStep::Mul(7577, 7638), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13962PolyExtStep::Sub(1, 7577), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13963PolyExtStep::Mul(8425, 7702), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13964PolyExtStep::Add(8424, 8426), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13965PolyExtStep::Mul(7578, 7639), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13966PolyExtStep::Sub(1, 7578), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13967PolyExtStep::Mul(8429, 7703), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13968PolyExtStep::Add(8428, 8430), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13969PolyExtStep::Mul(7579, 7640), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13970PolyExtStep::Sub(1, 7579), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13971PolyExtStep::Mul(8433, 7704), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13972PolyExtStep::Add(8432, 8434), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13973PolyExtStep::Mul(7580, 7641), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13974PolyExtStep::Sub(1, 7580), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13975PolyExtStep::Mul(8437, 7705), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13976PolyExtStep::Add(8436, 8438), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13977PolyExtStep::Mul(7581, 7642), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13978PolyExtStep::Sub(1, 7581), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13979PolyExtStep::Mul(8441, 7706), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13980PolyExtStep::Add(8440, 8442), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13981PolyExtStep::Mul(7582, 7643), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13982PolyExtStep::Sub(1, 7582), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13983PolyExtStep::Mul(8445, 7707), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13984PolyExtStep::Add(8444, 8446), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13985PolyExtStep::Mul(7583, 7644), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13986PolyExtStep::Sub(1, 7583), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13987PolyExtStep::Mul(8449, 7708), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13988PolyExtStep::Add(8448, 8450), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13989PolyExtStep::Mul(7584, 7645), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13990PolyExtStep::Sub(1, 7584), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13991PolyExtStep::Mul(8453, 7709), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13992PolyExtStep::Add(8452, 8454), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13993PolyExtStep::Mul(7585, 7646), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13994PolyExtStep::Sub(1, 7585), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13995PolyExtStep::Mul(8457, 7710), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13996PolyExtStep::Add(8456, 8458), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13997PolyExtStep::Mul(7586, 7647), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13998PolyExtStep::Sub(1, 7586), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
13999PolyExtStep::Mul(8461, 7711), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14000PolyExtStep::Add(8460, 8462), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14001PolyExtStep::Mul(7587, 7648), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14002PolyExtStep::Sub(1, 7587), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14003PolyExtStep::Mul(8465, 7712), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14004PolyExtStep::Add(8464, 8466), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14005PolyExtStep::Mul(7588, 7649), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14006PolyExtStep::Sub(1, 7588), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14007PolyExtStep::Mul(8469, 7713), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14008PolyExtStep::Add(8468, 8470), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14009PolyExtStep::Mul(7589, 7650), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14010PolyExtStep::Sub(1, 7589), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14011PolyExtStep::Mul(8473, 7714), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14012PolyExtStep::Add(8472, 8474), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14013PolyExtStep::Mul(7590, 7651), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14014PolyExtStep::Sub(1, 7590), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14015PolyExtStep::Mul(8477, 7715), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14016PolyExtStep::Add(8476, 8478), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14017PolyExtStep::Mul(7591, 7652), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14018PolyExtStep::Sub(1, 7591), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14019PolyExtStep::Mul(8481, 7716), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14020PolyExtStep::Add(8480, 8482), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14021PolyExtStep::Mul(3654, 7653), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14022PolyExtStep::Sub(1, 3654), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14023PolyExtStep::Mul(8485, 7717), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14024PolyExtStep::Add(8484, 8486), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14025PolyExtStep::Mul(3655, 7654), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14026PolyExtStep::Sub(1, 3655), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14027PolyExtStep::Mul(8489, 7718), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14028PolyExtStep::Add(8488, 8490), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14029PolyExtStep::Mul(3656, 7655), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14030PolyExtStep::Sub(1, 3656), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14031PolyExtStep::Mul(8493, 7719), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14032PolyExtStep::Add(8492, 8494), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14033PolyExtStep::Mul(7592, 7656), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14034PolyExtStep::Sub(1, 7592), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14035PolyExtStep::Mul(8497, 7720), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14036PolyExtStep::Add(8496, 8498), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14037PolyExtStep::Mul(7593, 7657), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14038PolyExtStep::Sub(1, 7593), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14039PolyExtStep::Mul(8501, 7721), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14040PolyExtStep::Add(8500, 8502), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14041PolyExtStep::Mul(7594, 7658), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14042PolyExtStep::Sub(1, 7594), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14043PolyExtStep::Mul(8505, 7722), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14044PolyExtStep::Add(8504, 8506), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14045PolyExtStep::Mul(7595, 7659), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14046PolyExtStep::Sub(1, 7595), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14047PolyExtStep::Mul(8509, 7723), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14048PolyExtStep::Add(8508, 8510), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14049PolyExtStep::Mul(7596, 7660), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14050PolyExtStep::Sub(1, 7596), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14051PolyExtStep::Mul(8513, 7724), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14052PolyExtStep::Add(8512, 8514), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14053PolyExtStep::Mul(7597, 7661), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14054PolyExtStep::Sub(1, 7597), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14055PolyExtStep::Mul(8517, 7725), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14056PolyExtStep::Add(8516, 8518), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14057PolyExtStep::Mul(7598, 7662), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14058PolyExtStep::Sub(1, 7598), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14059PolyExtStep::Mul(8521, 7726), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14060PolyExtStep::Add(8520, 8522), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14061PolyExtStep::Mul(7599, 7663), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14062PolyExtStep::Sub(1, 7599), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14063PolyExtStep::Mul(8525, 7727), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14064PolyExtStep::Add(8524, 8526), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14065PolyExtStep::Mul(8407, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14066PolyExtStep::Mul(8411, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14067PolyExtStep::Mul(8415, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14068PolyExtStep::Mul(8419, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14069PolyExtStep::Mul(8423, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14070PolyExtStep::Mul(8427, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14071PolyExtStep::Mul(8431, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14072PolyExtStep::Mul(8435, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14073PolyExtStep::Mul(8439, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14074PolyExtStep::Mul(8443, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14075PolyExtStep::Mul(8447, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14076PolyExtStep::Mul(8451, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14077PolyExtStep::Mul(8455, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14078PolyExtStep::Mul(8459, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14079PolyExtStep::Mul(8463, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14080PolyExtStep::Add(8403, 8528), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14081PolyExtStep::Add(8543, 8529), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14082PolyExtStep::Add(8544, 8530), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14083PolyExtStep::Add(8545, 8531), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14084PolyExtStep::Add(8546, 8532), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14085PolyExtStep::Add(8547, 8533), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14086PolyExtStep::Add(8548, 8534), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14087PolyExtStep::Add(8549, 8535), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14088PolyExtStep::Add(8550, 8536), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14089PolyExtStep::Add(8551, 8537), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14090PolyExtStep::Add(8552, 8538), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14091PolyExtStep::Add(8553, 8539), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14092PolyExtStep::Add(8554, 8540), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14093PolyExtStep::Add(8555, 8541), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14094PolyExtStep::Add(8556, 8542), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14095PolyExtStep::Mul(8471, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14096PolyExtStep::Mul(8475, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14097PolyExtStep::Mul(8479, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14098PolyExtStep::Mul(8483, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14099PolyExtStep::Mul(8487, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14100PolyExtStep::Mul(8491, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14101PolyExtStep::Mul(8495, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14102PolyExtStep::Mul(8499, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14103PolyExtStep::Mul(8503, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14104PolyExtStep::Mul(8507, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14105PolyExtStep::Mul(8511, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14106PolyExtStep::Mul(8515, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14107PolyExtStep::Mul(8519, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14108PolyExtStep::Mul(8523, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14109PolyExtStep::Mul(8527, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14110PolyExtStep::Add(8467, 8558), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14111PolyExtStep::Add(8573, 8559), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14112PolyExtStep::Add(8574, 8560), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14113PolyExtStep::Add(8575, 8561), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14114PolyExtStep::Add(8576, 8562), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14115PolyExtStep::Add(8577, 8563), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14116PolyExtStep::Add(8578, 8564), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14117PolyExtStep::Add(8579, 8565), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14118PolyExtStep::Add(8580, 8566), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14119PolyExtStep::Add(8581, 8567), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14120PolyExtStep::Add(8582, 8568), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14121PolyExtStep::Add(8583, 8569), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14122PolyExtStep::Add(8584, 8570), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14123PolyExtStep::Add(8585, 8571), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14124PolyExtStep::Add(8586, 8572), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14125PolyExtStep::Mul(8217, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14126PolyExtStep::Mul(8220, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14127PolyExtStep::Mul(8223, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14128PolyExtStep::Mul(8226, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14129PolyExtStep::Mul(8229, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14130PolyExtStep::Mul(8232, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14131PolyExtStep::Mul(8235, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14132PolyExtStep::Mul(8238, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14133PolyExtStep::Mul(8241, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14134PolyExtStep::Mul(8244, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14135PolyExtStep::Mul(8247, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14136PolyExtStep::Mul(8250, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14137PolyExtStep::Mul(8253, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14138PolyExtStep::Mul(8256, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14139PolyExtStep::Mul(8259, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14140PolyExtStep::Add(8214, 8588), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14141PolyExtStep::Add(8603, 8589), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14142PolyExtStep::Add(8604, 8590), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14143PolyExtStep::Add(8605, 8591), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14144PolyExtStep::Add(8606, 8592), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14145PolyExtStep::Add(8607, 8593), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14146PolyExtStep::Add(8608, 8594), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14147PolyExtStep::Add(8609, 8595), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14148PolyExtStep::Add(8610, 8596), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14149PolyExtStep::Add(8611, 8597), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14150PolyExtStep::Add(8612, 8598), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14151PolyExtStep::Add(8613, 8599), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14152PolyExtStep::Add(8614, 8600), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14153PolyExtStep::Add(8615, 8601), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14154PolyExtStep::Add(8616, 8602), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14155PolyExtStep::Mul(8265, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14156PolyExtStep::Mul(8268, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14157PolyExtStep::Mul(8271, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14158PolyExtStep::Mul(8274, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14159PolyExtStep::Mul(8277, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14160PolyExtStep::Mul(8280, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14161PolyExtStep::Mul(8283, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14162PolyExtStep::Mul(8286, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14163PolyExtStep::Mul(8289, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14164PolyExtStep::Mul(8292, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14165PolyExtStep::Mul(8295, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14166PolyExtStep::Mul(8298, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14167PolyExtStep::Mul(8301, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14168PolyExtStep::Mul(8304, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14169PolyExtStep::Mul(8307, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14170PolyExtStep::Add(8262, 8618), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14171PolyExtStep::Add(8633, 8619), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14172PolyExtStep::Add(8634, 8620), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14173PolyExtStep::Add(8635, 8621), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14174PolyExtStep::Add(8636, 8622), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14175PolyExtStep::Add(8637, 8623), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14176PolyExtStep::Add(8638, 8624), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14177PolyExtStep::Add(8639, 8625), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14178PolyExtStep::Add(8640, 8626), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14179PolyExtStep::Add(8641, 8627), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14180PolyExtStep::Add(8642, 8628), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14181PolyExtStep::Add(8643, 8629), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14182PolyExtStep::Add(8644, 8630), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14183PolyExtStep::Add(8645, 8631), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14184PolyExtStep::Add(8646, 8632), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14185PolyExtStep::Add(8557, 8617), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:58) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14186PolyExtStep::Add(8587, 8647), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:58) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14187PolyExtStep::Add(8369, 8648), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:42) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14188PolyExtStep::Add(8399, 8649), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:42) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14189PolyExtStep::Add(835, 8650), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:34) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14190PolyExtStep::Add(838, 8651), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:34) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14191PolyExtStep::Add(8323, 8652), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14192PolyExtStep::Add(8339, 8653), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14193PolyExtStep::Mul(4113, 7600), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14194PolyExtStep::Sub(1, 7664), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14195PolyExtStep::Mul(8656, 8657), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14196PolyExtStep::Sub(1, 7600), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14197PolyExtStep::Mul(4113, 8659), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14198PolyExtStep::Mul(8660, 7664), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14199PolyExtStep::Add(8658, 8661), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14200PolyExtStep::Sub(1, 4113), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14201PolyExtStep::Mul(8663, 7600), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14202PolyExtStep::Mul(8664, 7664), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14203PolyExtStep::Add(8662, 8665), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14204PolyExtStep::Mul(8656, 7664), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14205PolyExtStep::Add(8666, 8667), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14206PolyExtStep::Mul(4037, 7601), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14207PolyExtStep::Sub(1, 7665), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14208PolyExtStep::Mul(8669, 8670), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14209PolyExtStep::Sub(1, 7601), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14210PolyExtStep::Mul(4037, 8672), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14211PolyExtStep::Mul(8673, 7665), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14212PolyExtStep::Add(8671, 8674), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14213PolyExtStep::Sub(1, 4037), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14214PolyExtStep::Mul(8676, 7601), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14215PolyExtStep::Mul(8677, 7665), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14216PolyExtStep::Add(8675, 8678), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14217PolyExtStep::Mul(8669, 7665), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14218PolyExtStep::Add(8679, 8680), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14219PolyExtStep::Mul(4038, 7602), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14220PolyExtStep::Sub(1, 7666), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14221PolyExtStep::Mul(8682, 8683), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14222PolyExtStep::Sub(1, 7602), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14223PolyExtStep::Mul(4038, 8685), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14224PolyExtStep::Mul(8686, 7666), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14225PolyExtStep::Add(8684, 8687), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14226PolyExtStep::Sub(1, 4038), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14227PolyExtStep::Mul(8689, 7602), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14228PolyExtStep::Mul(8690, 7666), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14229PolyExtStep::Add(8688, 8691), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14230PolyExtStep::Mul(8682, 7666), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14231PolyExtStep::Add(8692, 8693), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14232PolyExtStep::Mul(4039, 7603), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14233PolyExtStep::Sub(1, 7667), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14234PolyExtStep::Mul(8695, 8696), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14235PolyExtStep::Sub(1, 7603), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14236PolyExtStep::Mul(4039, 8698), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14237PolyExtStep::Mul(8699, 7667), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14238PolyExtStep::Add(8697, 8700), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14239PolyExtStep::Sub(1, 4039), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14240PolyExtStep::Mul(8702, 7603), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14241PolyExtStep::Mul(8703, 7667), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14242PolyExtStep::Add(8701, 8704), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14243PolyExtStep::Mul(8695, 7667), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14244PolyExtStep::Add(8705, 8706), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14245PolyExtStep::Mul(4114, 7604), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14246PolyExtStep::Sub(1, 7668), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14247PolyExtStep::Mul(8708, 8709), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14248PolyExtStep::Sub(1, 7604), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14249PolyExtStep::Mul(4114, 8711), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14250PolyExtStep::Mul(8712, 7668), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14251PolyExtStep::Add(8710, 8713), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14252PolyExtStep::Sub(1, 4114), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14253PolyExtStep::Mul(8715, 7604), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14254PolyExtStep::Mul(8716, 7668), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14255PolyExtStep::Add(8714, 8717), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14256PolyExtStep::Mul(8708, 7668), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14257PolyExtStep::Add(8718, 8719), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14258PolyExtStep::Mul(4115, 7605), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14259PolyExtStep::Sub(1, 7669), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14260PolyExtStep::Mul(8721, 8722), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14261PolyExtStep::Sub(1, 7605), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14262PolyExtStep::Mul(4115, 8724), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14263PolyExtStep::Mul(8725, 7669), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14264PolyExtStep::Add(8723, 8726), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14265PolyExtStep::Sub(1, 4115), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14266PolyExtStep::Mul(8728, 7605), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14267PolyExtStep::Mul(8729, 7669), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14268PolyExtStep::Add(8727, 8730), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14269PolyExtStep::Mul(8721, 7669), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14270PolyExtStep::Add(8731, 8732), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14271PolyExtStep::Mul(4116, 7606), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14272PolyExtStep::Sub(1, 7670), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14273PolyExtStep::Mul(8734, 8735), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14274PolyExtStep::Sub(1, 7606), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14275PolyExtStep::Mul(4116, 8737), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14276PolyExtStep::Mul(8738, 7670), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14277PolyExtStep::Add(8736, 8739), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14278PolyExtStep::Sub(1, 4116), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14279PolyExtStep::Mul(8741, 7606), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14280PolyExtStep::Mul(8742, 7670), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14281PolyExtStep::Add(8740, 8743), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14282PolyExtStep::Mul(8734, 7670), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14283PolyExtStep::Add(8744, 8745), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14284PolyExtStep::Mul(4117, 7607), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14285PolyExtStep::Sub(1, 7671), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14286PolyExtStep::Mul(8747, 8748), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14287PolyExtStep::Sub(1, 7607), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14288PolyExtStep::Mul(4117, 8750), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14289PolyExtStep::Mul(8751, 7671), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14290PolyExtStep::Add(8749, 8752), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14291PolyExtStep::Sub(1, 4117), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14292PolyExtStep::Mul(8754, 7607), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14293PolyExtStep::Mul(8755, 7671), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14294PolyExtStep::Add(8753, 8756), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14295PolyExtStep::Mul(8747, 7671), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14296PolyExtStep::Add(8757, 8758), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14297PolyExtStep::Mul(4118, 7608), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14298PolyExtStep::Sub(1, 7672), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14299PolyExtStep::Mul(8760, 8761), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14300PolyExtStep::Sub(1, 7608), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14301PolyExtStep::Mul(4118, 8763), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14302PolyExtStep::Mul(8764, 7672), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14303PolyExtStep::Add(8762, 8765), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14304PolyExtStep::Sub(1, 4118), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14305PolyExtStep::Mul(8767, 7608), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14306PolyExtStep::Mul(8768, 7672), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14307PolyExtStep::Add(8766, 8769), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14308PolyExtStep::Mul(8760, 7672), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14309PolyExtStep::Add(8770, 8771), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14310PolyExtStep::Mul(4119, 7609), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14311PolyExtStep::Sub(1, 7673), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14312PolyExtStep::Mul(8773, 8774), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14313PolyExtStep::Sub(1, 7609), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14314PolyExtStep::Mul(4119, 8776), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14315PolyExtStep::Mul(8777, 7673), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14316PolyExtStep::Add(8775, 8778), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14317PolyExtStep::Sub(1, 4119), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14318PolyExtStep::Mul(8780, 7609), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14319PolyExtStep::Mul(8781, 7673), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14320PolyExtStep::Add(8779, 8782), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14321PolyExtStep::Mul(8773, 7673), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14322PolyExtStep::Add(8783, 8784), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14323PolyExtStep::Mul(4120, 7610), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14324PolyExtStep::Sub(1, 7674), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14325PolyExtStep::Mul(8786, 8787), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14326PolyExtStep::Sub(1, 7610), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14327PolyExtStep::Mul(4120, 8789), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14328PolyExtStep::Mul(8790, 7674), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14329PolyExtStep::Add(8788, 8791), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14330PolyExtStep::Sub(1, 4120), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14331PolyExtStep::Mul(8793, 7610), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14332PolyExtStep::Mul(8794, 7674), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14333PolyExtStep::Add(8792, 8795), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14334PolyExtStep::Mul(8786, 7674), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14335PolyExtStep::Add(8796, 8797), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14336PolyExtStep::Mul(4121, 7611), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14337PolyExtStep::Sub(1, 7675), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14338PolyExtStep::Mul(8799, 8800), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14339PolyExtStep::Sub(1, 7611), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14340PolyExtStep::Mul(4121, 8802), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14341PolyExtStep::Mul(8803, 7675), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14342PolyExtStep::Add(8801, 8804), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14343PolyExtStep::Sub(1, 4121), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14344PolyExtStep::Mul(8806, 7611), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14345PolyExtStep::Mul(8807, 7675), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14346PolyExtStep::Add(8805, 8808), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14347PolyExtStep::Mul(8799, 7675), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14348PolyExtStep::Add(8809, 8810), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14349PolyExtStep::Mul(4122, 7612), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14350PolyExtStep::Sub(1, 7676), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14351PolyExtStep::Mul(8812, 8813), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14352PolyExtStep::Sub(1, 7612), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14353PolyExtStep::Mul(4122, 8815), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14354PolyExtStep::Mul(8816, 7676), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14355PolyExtStep::Add(8814, 8817), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14356PolyExtStep::Sub(1, 4122), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14357PolyExtStep::Mul(8819, 7612), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14358PolyExtStep::Mul(8820, 7676), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14359PolyExtStep::Add(8818, 8821), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14360PolyExtStep::Mul(8812, 7676), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14361PolyExtStep::Add(8822, 8823), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14362PolyExtStep::Mul(4123, 7613), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14363PolyExtStep::Sub(1, 7677), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14364PolyExtStep::Mul(8825, 8826), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14365PolyExtStep::Sub(1, 7613), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14366PolyExtStep::Mul(4123, 8828), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14367PolyExtStep::Mul(8829, 7677), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14368PolyExtStep::Add(8827, 8830), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14369PolyExtStep::Sub(1, 4123), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14370PolyExtStep::Mul(8832, 7613), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14371PolyExtStep::Mul(8833, 7677), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14372PolyExtStep::Add(8831, 8834), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14373PolyExtStep::Mul(8825, 7677), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14374PolyExtStep::Add(8835, 8836), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14375PolyExtStep::Mul(4124, 7614), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14376PolyExtStep::Sub(1, 7678), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14377PolyExtStep::Mul(8838, 8839), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14378PolyExtStep::Sub(1, 7614), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14379PolyExtStep::Mul(4124, 8841), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14380PolyExtStep::Mul(8842, 7678), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14381PolyExtStep::Add(8840, 8843), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14382PolyExtStep::Sub(1, 4124), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14383PolyExtStep::Mul(8845, 7614), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14384PolyExtStep::Mul(8846, 7678), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14385PolyExtStep::Add(8844, 8847), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14386PolyExtStep::Mul(8838, 7678), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14387PolyExtStep::Add(8848, 8849), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14388PolyExtStep::Mul(4125, 7615), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14389PolyExtStep::Sub(1, 7679), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14390PolyExtStep::Mul(8851, 8852), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14391PolyExtStep::Sub(1, 7615), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14392PolyExtStep::Mul(4125, 8854), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14393PolyExtStep::Mul(8855, 7679), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14394PolyExtStep::Add(8853, 8856), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14395PolyExtStep::Sub(1, 4125), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14396PolyExtStep::Mul(8858, 7615), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14397PolyExtStep::Mul(8859, 7679), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14398PolyExtStep::Add(8857, 8860), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14399PolyExtStep::Mul(8851, 7679), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14400PolyExtStep::Add(8861, 8862), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14401PolyExtStep::Mul(4126, 7616), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14402PolyExtStep::Sub(1, 7680), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14403PolyExtStep::Mul(8864, 8865), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14404PolyExtStep::Sub(1, 7616), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14405PolyExtStep::Mul(4126, 8867), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14406PolyExtStep::Mul(8868, 7680), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14407PolyExtStep::Add(8866, 8869), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14408PolyExtStep::Sub(1, 4126), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14409PolyExtStep::Mul(8871, 7616), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14410PolyExtStep::Mul(8872, 7680), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14411PolyExtStep::Add(8870, 8873), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14412PolyExtStep::Mul(8864, 7680), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14413PolyExtStep::Add(8874, 8875), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14414PolyExtStep::Mul(4127, 7617), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14415PolyExtStep::Sub(1, 7681), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14416PolyExtStep::Mul(8877, 8878), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14417PolyExtStep::Sub(1, 7617), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14418PolyExtStep::Mul(4127, 8880), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14419PolyExtStep::Mul(8881, 7681), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14420PolyExtStep::Add(8879, 8882), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14421PolyExtStep::Sub(1, 4127), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14422PolyExtStep::Mul(8884, 7617), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14423PolyExtStep::Mul(8885, 7681), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14424PolyExtStep::Add(8883, 8886), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14425PolyExtStep::Mul(8877, 7681), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14426PolyExtStep::Add(8887, 8888), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14427PolyExtStep::Mul(4128, 7618), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14428PolyExtStep::Sub(1, 7682), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14429PolyExtStep::Mul(8890, 8891), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14430PolyExtStep::Sub(1, 7618), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14431PolyExtStep::Mul(4128, 8893), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14432PolyExtStep::Mul(8894, 7682), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14433PolyExtStep::Add(8892, 8895), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14434PolyExtStep::Sub(1, 4128), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14435PolyExtStep::Mul(8897, 7618), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14436PolyExtStep::Mul(8898, 7682), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14437PolyExtStep::Add(8896, 8899), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14438PolyExtStep::Mul(8890, 7682), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14439PolyExtStep::Add(8900, 8901), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14440PolyExtStep::Mul(4129, 7619), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14441PolyExtStep::Sub(1, 7683), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14442PolyExtStep::Mul(8903, 8904), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14443PolyExtStep::Sub(1, 7619), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14444PolyExtStep::Mul(4129, 8906), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14445PolyExtStep::Mul(8907, 7683), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14446PolyExtStep::Add(8905, 8908), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14447PolyExtStep::Sub(1, 4129), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14448PolyExtStep::Mul(8910, 7619), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14449PolyExtStep::Mul(8911, 7683), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14450PolyExtStep::Add(8909, 8912), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14451PolyExtStep::Mul(8903, 7683), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14452PolyExtStep::Add(8913, 8914), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14453PolyExtStep::Mul(4130, 7620), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14454PolyExtStep::Sub(1, 7684), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14455PolyExtStep::Mul(8916, 8917), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14456PolyExtStep::Sub(1, 7620), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14457PolyExtStep::Mul(4130, 8919), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14458PolyExtStep::Mul(8920, 7684), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14459PolyExtStep::Add(8918, 8921), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14460PolyExtStep::Sub(1, 4130), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14461PolyExtStep::Mul(8923, 7620), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14462PolyExtStep::Mul(8924, 7684), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14463PolyExtStep::Add(8922, 8925), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14464PolyExtStep::Mul(8916, 7684), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14465PolyExtStep::Add(8926, 8927), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14466PolyExtStep::Mul(4131, 7621), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14467PolyExtStep::Sub(1, 7685), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14468PolyExtStep::Mul(8929, 8930), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14469PolyExtStep::Sub(1, 7621), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14470PolyExtStep::Mul(4131, 8932), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14471PolyExtStep::Mul(8933, 7685), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14472PolyExtStep::Add(8931, 8934), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14473PolyExtStep::Sub(1, 4131), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14474PolyExtStep::Mul(8936, 7621), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14475PolyExtStep::Mul(8937, 7685), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14476PolyExtStep::Add(8935, 8938), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14477PolyExtStep::Mul(8929, 7685), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14478PolyExtStep::Add(8939, 8940), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14479PolyExtStep::Mul(4132, 7622), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14480PolyExtStep::Sub(1, 7686), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14481PolyExtStep::Mul(8942, 8943), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14482PolyExtStep::Sub(1, 7622), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14483PolyExtStep::Mul(4132, 8945), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14484PolyExtStep::Mul(8946, 7686), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14485PolyExtStep::Add(8944, 8947), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14486PolyExtStep::Sub(1, 4132), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14487PolyExtStep::Mul(8949, 7622), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14488PolyExtStep::Mul(8950, 7686), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14489PolyExtStep::Add(8948, 8951), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14490PolyExtStep::Mul(8942, 7686), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14491PolyExtStep::Add(8952, 8953), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14492PolyExtStep::Mul(4133, 7623), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14493PolyExtStep::Sub(1, 7687), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14494PolyExtStep::Mul(8955, 8956), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14495PolyExtStep::Sub(1, 7623), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14496PolyExtStep::Mul(4133, 8958), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14497PolyExtStep::Mul(8959, 7687), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14498PolyExtStep::Add(8957, 8960), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14499PolyExtStep::Sub(1, 4133), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14500PolyExtStep::Mul(8962, 7623), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14501PolyExtStep::Mul(8963, 7687), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14502PolyExtStep::Add(8961, 8964), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14503PolyExtStep::Mul(8955, 7687), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14504PolyExtStep::Add(8965, 8966), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14505PolyExtStep::Mul(4134, 7624), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14506PolyExtStep::Sub(1, 7688), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14507PolyExtStep::Mul(8968, 8969), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14508PolyExtStep::Sub(1, 7624), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14509PolyExtStep::Mul(4134, 8971), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14510PolyExtStep::Mul(8972, 7688), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14511PolyExtStep::Add(8970, 8973), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14512PolyExtStep::Sub(1, 4134), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14513PolyExtStep::Mul(8975, 7624), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14514PolyExtStep::Mul(8976, 7688), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14515PolyExtStep::Add(8974, 8977), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14516PolyExtStep::Mul(8968, 7688), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14517PolyExtStep::Add(8978, 8979), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14518PolyExtStep::Mul(4135, 7625), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14519PolyExtStep::Sub(1, 7689), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14520PolyExtStep::Mul(8981, 8982), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14521PolyExtStep::Sub(1, 7625), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14522PolyExtStep::Mul(4135, 8984), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14523PolyExtStep::Mul(8985, 7689), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14524PolyExtStep::Add(8983, 8986), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14525PolyExtStep::Sub(1, 4135), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14526PolyExtStep::Mul(8988, 7625), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14527PolyExtStep::Mul(8989, 7689), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14528PolyExtStep::Add(8987, 8990), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14529PolyExtStep::Mul(8981, 7689), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14530PolyExtStep::Add(8991, 8992), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14531PolyExtStep::Mul(4136, 7626), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14532PolyExtStep::Sub(1, 7690), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14533PolyExtStep::Mul(8994, 8995), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14534PolyExtStep::Sub(1, 7626), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14535PolyExtStep::Mul(4136, 8997), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14536PolyExtStep::Mul(8998, 7690), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14537PolyExtStep::Add(8996, 8999), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14538PolyExtStep::Sub(1, 4136), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14539PolyExtStep::Mul(9001, 7626), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14540PolyExtStep::Mul(9002, 7690), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14541PolyExtStep::Add(9000, 9003), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14542PolyExtStep::Mul(8994, 7690), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14543PolyExtStep::Add(9004, 9005), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14544PolyExtStep::Mul(4137, 7627), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14545PolyExtStep::Sub(1, 7691), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14546PolyExtStep::Mul(9007, 9008), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14547PolyExtStep::Sub(1, 7627), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14548PolyExtStep::Mul(4137, 9010), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14549PolyExtStep::Mul(9011, 7691), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14550PolyExtStep::Add(9009, 9012), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14551PolyExtStep::Sub(1, 4137), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14552PolyExtStep::Mul(9014, 7627), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14553PolyExtStep::Mul(9015, 7691), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14554PolyExtStep::Add(9013, 9016), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14555PolyExtStep::Mul(9007, 7691), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14556PolyExtStep::Add(9017, 9018), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14557PolyExtStep::Mul(4145, 7628), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14558PolyExtStep::Sub(1, 7692), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14559PolyExtStep::Mul(9020, 9021), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14560PolyExtStep::Sub(1, 7628), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14561PolyExtStep::Mul(4145, 9023), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14562PolyExtStep::Mul(9024, 7692), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14563PolyExtStep::Add(9022, 9025), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14564PolyExtStep::Sub(1, 4145), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14565PolyExtStep::Mul(9027, 7628), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14566PolyExtStep::Mul(9028, 7692), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14567PolyExtStep::Add(9026, 9029), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14568PolyExtStep::Mul(9020, 7692), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14569PolyExtStep::Add(9030, 9031), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14570PolyExtStep::Mul(4142, 7629), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14571PolyExtStep::Sub(1, 7693), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14572PolyExtStep::Mul(9033, 9034), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14573PolyExtStep::Sub(1, 7629), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14574PolyExtStep::Mul(4142, 9036), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14575PolyExtStep::Mul(9037, 7693), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14576PolyExtStep::Add(9035, 9038), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14577PolyExtStep::Sub(1, 4142), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14578PolyExtStep::Mul(9040, 7629), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14579PolyExtStep::Mul(9041, 7693), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14580PolyExtStep::Add(9039, 9042), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14581PolyExtStep::Mul(9033, 7693), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14582PolyExtStep::Add(9043, 9044), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14583PolyExtStep::Mul(4139, 7630), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14584PolyExtStep::Sub(1, 7694), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14585PolyExtStep::Mul(9046, 9047), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14586PolyExtStep::Sub(1, 7630), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14587PolyExtStep::Mul(4139, 9049), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14588PolyExtStep::Mul(9050, 7694), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14589PolyExtStep::Add(9048, 9051), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14590PolyExtStep::Sub(1, 4139), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14591PolyExtStep::Mul(9053, 7630), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14592PolyExtStep::Mul(9054, 7694), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14593PolyExtStep::Add(9052, 9055), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14594PolyExtStep::Mul(9046, 7694), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14595PolyExtStep::Add(9056, 9057), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14596PolyExtStep::Mul(4138, 7631), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14597PolyExtStep::Sub(1, 7695), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14598PolyExtStep::Mul(9059, 9060), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14599PolyExtStep::Sub(1, 7631), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14600PolyExtStep::Mul(4138, 9062), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14601PolyExtStep::Mul(9063, 7695), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14602PolyExtStep::Add(9061, 9064), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14603PolyExtStep::Sub(1, 4138), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14604PolyExtStep::Mul(9066, 7631), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14605PolyExtStep::Mul(9067, 7695), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14606PolyExtStep::Add(9065, 9068), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14607PolyExtStep::Mul(9059, 7695), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14608PolyExtStep::Add(9069, 9070), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14609PolyExtStep::Mul(8681, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14610PolyExtStep::Mul(8694, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14611PolyExtStep::Mul(8707, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14612PolyExtStep::Mul(8720, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14613PolyExtStep::Mul(8733, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14614PolyExtStep::Mul(8746, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14615PolyExtStep::Mul(8759, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14616PolyExtStep::Mul(8772, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14617PolyExtStep::Mul(8785, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14618PolyExtStep::Mul(8798, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14619PolyExtStep::Mul(8811, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14620PolyExtStep::Mul(8824, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14621PolyExtStep::Mul(8837, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14622PolyExtStep::Mul(8850, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14623PolyExtStep::Mul(8863, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14624PolyExtStep::Add(8668, 9072), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14625PolyExtStep::Add(9087, 9073), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14626PolyExtStep::Add(9088, 9074), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14627PolyExtStep::Add(9089, 9075), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14628PolyExtStep::Add(9090, 9076), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14629PolyExtStep::Add(9091, 9077), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14630PolyExtStep::Add(9092, 9078), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14631PolyExtStep::Add(9093, 9079), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14632PolyExtStep::Add(9094, 9080), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14633PolyExtStep::Add(9095, 9081), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14634PolyExtStep::Add(9096, 9082), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14635PolyExtStep::Add(9097, 9083), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14636PolyExtStep::Add(9098, 9084), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14637PolyExtStep::Add(9099, 9085), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14638PolyExtStep::Add(9100, 9086), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14639PolyExtStep::Mul(8889, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14640PolyExtStep::Mul(8902, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14641PolyExtStep::Mul(8915, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14642PolyExtStep::Mul(8928, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14643PolyExtStep::Mul(8941, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14644PolyExtStep::Mul(8954, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14645PolyExtStep::Mul(8967, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14646PolyExtStep::Mul(8980, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14647PolyExtStep::Mul(8993, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14648PolyExtStep::Mul(9006, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14649PolyExtStep::Mul(9019, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14650PolyExtStep::Mul(9032, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14651PolyExtStep::Mul(9045, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14652PolyExtStep::Mul(9058, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14653PolyExtStep::Mul(9071, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14654PolyExtStep::Add(8876, 9102), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14655PolyExtStep::Add(9117, 9103), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14656PolyExtStep::Add(9118, 9104), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14657PolyExtStep::Add(9119, 9105), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14658PolyExtStep::Add(9120, 9106), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14659PolyExtStep::Add(9121, 9107), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14660PolyExtStep::Add(9122, 9108), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14661PolyExtStep::Add(9123, 9109), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14662PolyExtStep::Add(9124, 9110), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14663PolyExtStep::Add(9125, 9111), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14664PolyExtStep::Add(9126, 9112), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14665PolyExtStep::Add(9127, 9113), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14666PolyExtStep::Add(9128, 9114), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14667PolyExtStep::Add(9129, 9115), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14668PolyExtStep::Add(9130, 9116), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14669PolyExtStep::Mul(7993, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14670PolyExtStep::Mul(7996, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14671PolyExtStep::Mul(7999, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14672PolyExtStep::Mul(8002, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14673PolyExtStep::Mul(8005, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14674PolyExtStep::Mul(8008, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14675PolyExtStep::Mul(8011, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14676PolyExtStep::Mul(8014, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14677PolyExtStep::Mul(8017, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14678PolyExtStep::Mul(8020, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14679PolyExtStep::Mul(8023, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14680PolyExtStep::Mul(8026, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14681PolyExtStep::Mul(8029, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14682PolyExtStep::Mul(8032, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14683PolyExtStep::Mul(8035, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14684PolyExtStep::Add(7990, 9132), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14685PolyExtStep::Add(9147, 9133), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14686PolyExtStep::Add(9148, 9134), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14687PolyExtStep::Add(9149, 9135), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14688PolyExtStep::Add(9150, 9136), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14689PolyExtStep::Add(9151, 9137), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14690PolyExtStep::Add(9152, 9138), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14691PolyExtStep::Add(9153, 9139), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14692PolyExtStep::Add(9154, 9140), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14693PolyExtStep::Add(9155, 9141), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14694PolyExtStep::Add(9156, 9142), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14695PolyExtStep::Add(9157, 9143), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14696PolyExtStep::Add(9158, 9144), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14697PolyExtStep::Add(9159, 9145), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14698PolyExtStep::Add(9160, 9146), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14699PolyExtStep::Mul(8041, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14700PolyExtStep::Mul(8044, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14701PolyExtStep::Mul(8047, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14702PolyExtStep::Mul(8050, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14703PolyExtStep::Mul(8053, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14704PolyExtStep::Mul(8056, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14705PolyExtStep::Mul(8059, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14706PolyExtStep::Mul(8062, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14707PolyExtStep::Mul(8065, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14708PolyExtStep::Mul(8068, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14709PolyExtStep::Mul(8071, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14710PolyExtStep::Mul(8074, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14711PolyExtStep::Mul(8077, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14712PolyExtStep::Mul(8080, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14713PolyExtStep::Mul(8083, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14714PolyExtStep::Add(8038, 9162), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14715PolyExtStep::Add(9177, 9163), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14716PolyExtStep::Add(9178, 9164), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14717PolyExtStep::Add(9179, 9165), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14718PolyExtStep::Add(9180, 9166), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14719PolyExtStep::Add(9181, 9167), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14720PolyExtStep::Add(9182, 9168), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14721PolyExtStep::Add(9183, 9169), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14722PolyExtStep::Add(9184, 9170), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14723PolyExtStep::Add(9185, 9171), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14724PolyExtStep::Add(9186, 9172), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14725PolyExtStep::Add(9187, 9173), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14726PolyExtStep::Add(9188, 9174), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14727PolyExtStep::Add(9189, 9175), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14728PolyExtStep::Add(9190, 9176), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14729PolyExtStep::Add(9101, 9161), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:36) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14730PolyExtStep::Add(9131, 9191), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:36) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14731PolyExtStep::Add(8654, 9192), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14732PolyExtStep::Add(8655, 9193), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14733PolyExtStep::Mul(7729, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14734PolyExtStep::Mul(7730, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14735PolyExtStep::Mul(7731, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14736PolyExtStep::Mul(7732, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14737PolyExtStep::Mul(7733, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14738PolyExtStep::Mul(7734, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14739PolyExtStep::Mul(7735, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14740PolyExtStep::Mul(7736, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14741PolyExtStep::Mul(7737, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14742PolyExtStep::Mul(7738, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14743PolyExtStep::Mul(7739, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14744PolyExtStep::Mul(7740, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14745PolyExtStep::Mul(7741, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14746PolyExtStep::Mul(7742, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14747PolyExtStep::Mul(7743, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14748PolyExtStep::Add(7728, 9196), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14749PolyExtStep::Add(9211, 9197), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14750PolyExtStep::Add(9212, 9198), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14751PolyExtStep::Add(9213, 9199), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14752PolyExtStep::Add(9214, 9200), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14753PolyExtStep::Add(9215, 9201), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14754PolyExtStep::Add(9216, 9202), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14755PolyExtStep::Add(9217, 9203), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14756PolyExtStep::Add(9218, 9204), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14757PolyExtStep::Add(9219, 9205), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14758PolyExtStep::Add(9220, 9206), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14759PolyExtStep::Add(9221, 9207), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14760PolyExtStep::Add(9222, 9208), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14761PolyExtStep::Add(9223, 9209), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14762PolyExtStep::Add(9224, 9210), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14763PolyExtStep::Mul(7745, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14764PolyExtStep::Mul(7746, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14765PolyExtStep::Mul(7747, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14766PolyExtStep::Mul(7748, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14767PolyExtStep::Mul(7749, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14768PolyExtStep::Mul(7750, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14769PolyExtStep::Mul(7751, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14770PolyExtStep::Mul(7752, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14771PolyExtStep::Mul(7753, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14772PolyExtStep::Mul(7754, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14773PolyExtStep::Mul(7755, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14774PolyExtStep::Mul(7756, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14775PolyExtStep::Mul(7757, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14776PolyExtStep::Mul(7758, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14777PolyExtStep::Mul(7759, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14778PolyExtStep::Add(7744, 9226), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14779PolyExtStep::Add(9241, 9227), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14780PolyExtStep::Add(9242, 9228), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14781PolyExtStep::Add(9243, 9229), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14782PolyExtStep::Add(9244, 9230), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14783PolyExtStep::Add(9245, 9231), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14784PolyExtStep::Add(9246, 9232), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14785PolyExtStep::Add(9247, 9233), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14786PolyExtStep::Add(9248, 9234), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14787PolyExtStep::Add(9249, 9235), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14788PolyExtStep::Add(9250, 9236), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14789PolyExtStep::Add(9251, 9237), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14790PolyExtStep::Add(9252, 9238), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14791PolyExtStep::Add(9253, 9239), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14792PolyExtStep::Add(9254, 9240), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14793PolyExtStep::Add(8654, 9225), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14794PolyExtStep::Add(8655, 9255), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14795PolyExtStep::AndEqz(5509, 1092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14796PolyExtStep::AndEqz(5510, 1095), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14797PolyExtStep::AndEqz(5511, 1098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14798PolyExtStep::Mul(1096, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14799PolyExtStep::Mul(1093, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14800PolyExtStep::Add(9258, 9259), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14801PolyExtStep::Add(9260, 1090), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14802PolyExtStep::Mul(9261, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14803PolyExtStep::Sub(9194, 9262), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14804PolyExtStep::Add(9195, 9261), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14805PolyExtStep::AndEqz(5512, 3995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14806PolyExtStep::AndEqz(5513, 4190), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14807PolyExtStep::AndEqz(5514, 4001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14808PolyExtStep::Mul(2744, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14809PolyExtStep::Mul(2737, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14810PolyExtStep::Add(9265, 9266), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14811PolyExtStep::Add(9267, 2736), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14812PolyExtStep::Mul(9268, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14813PolyExtStep::Sub(9264, 9269), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14814PolyExtStep::AndEqz(5515, 7478), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14815PolyExtStep::AndEqz(5516, 7480), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14816PolyExtStep::AndEqz(5517, 7481), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14817PolyExtStep::AndEqz(5518, 7482), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14818PolyExtStep::AndEqz(5519, 7484), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14819PolyExtStep::AndEqz(5520, 1377), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14820PolyExtStep::AndEqz(5521, 2799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14821PolyExtStep::AndEqz(5522, 2805), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14822PolyExtStep::AndEqz(5523, 1387), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14823PolyExtStep::AndEqz(5524, 2815), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14824PolyExtStep::AndEqz(5525, 2821), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14825PolyExtStep::AndEqz(5526, 1396), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14826PolyExtStep::AndEqz(5527, 2827), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14827PolyExtStep::AndEqz(5528, 2833), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14828PolyExtStep::AndEqz(5529, 1406), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14829PolyExtStep::AndEqz(5530, 1413), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14830PolyExtStep::AndEqz(5531, 2839), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14831PolyExtStep::AndEqz(5532, 2845), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14832PolyExtStep::AndEqz(5533, 2851), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14833PolyExtStep::AndEqz(5534, 2857), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14834PolyExtStep::AndEqz(5535, 7486), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14835PolyExtStep::AndEqz(5536, 2772), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14836PolyExtStep::AndEqz(5537, 7488), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14837PolyExtStep::AndEqz(5538, 7490), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14838PolyExtStep::AndEqz(5539, 2780), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14839PolyExtStep::AndEqz(5540, 7492), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14840PolyExtStep::AndEqz(5541, 7494), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14841PolyExtStep::AndEqz(5542, 7496), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14842PolyExtStep::AndEqz(5543, 7498), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14843PolyExtStep::AndEqz(5544, 7500), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14844PolyExtStep::AndEqz(5545, 7502), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14845PolyExtStep::AndEqz(5546, 7504), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14846PolyExtStep::Mul(1391, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14847PolyExtStep::Mul(1392, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14848PolyExtStep::Mul(1394, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14849PolyExtStep::Mul(1401, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14850PolyExtStep::Mul(1402, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14851PolyExtStep::Mul(1404, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14852PolyExtStep::Mul(1410, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14853PolyExtStep::Add(7435, 1814), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14854PolyExtStep::Add(9278, 9271), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14855PolyExtStep::Add(9279, 9272), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14856PolyExtStep::Add(9280, 9273), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14857PolyExtStep::Add(9281, 9274), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14858PolyExtStep::Add(9282, 9275), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14859PolyExtStep::Add(9283, 9276), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14860PolyExtStep::Add(9284, 9277), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14861PolyExtStep::Mul(1430, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14862PolyExtStep::Mul(1431, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14863PolyExtStep::Mul(1432, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14864PolyExtStep::Mul(1439, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14865PolyExtStep::Mul(1440, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14866PolyExtStep::Mul(1900, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14867PolyExtStep::Mul(538, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14868PolyExtStep::Mul(2278, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14869PolyExtStep::Add(7463, 9286), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14870PolyExtStep::Add(9294, 9287), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14871PolyExtStep::Add(9295, 9288), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14872PolyExtStep::Add(9296, 9289), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14873PolyExtStep::Add(9297, 9290), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14874PolyExtStep::Add(9298, 9291), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14875PolyExtStep::Add(9299, 9292), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14876PolyExtStep::Add(9300, 9293), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14877PolyExtStep::Sub(9285, 9263), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14878PolyExtStep::AndEqz(5547, 9302), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14879PolyExtStep::Sub(9301, 9270), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14880PolyExtStep::AndEqz(5548, 9303), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14881PolyExtStep::AndEqz(5549, 4003), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14882PolyExtStep::AndEqz(5550, 4009), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14883PolyExtStep::AndEqz(5551, 4150), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14884PolyExtStep::Mul(2751, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14885PolyExtStep::Add(9304, 4880), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14886PolyExtStep::Add(9305, 2745), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14887PolyExtStep::Mul(9306, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14888PolyExtStep::Sub(9256, 9307), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14889PolyExtStep::Add(9257, 9306), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14890PolyExtStep::AndEqz(5552, 2755), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14891PolyExtStep::AndEqz(5553, 4853), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14892PolyExtStep::AndEqz(5554, 4861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14893PolyExtStep::Mul(2761, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14894PolyExtStep::Mul(2760, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14895PolyExtStep::Add(9310, 9311), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14896PolyExtStep::Add(9312, 2753), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14897PolyExtStep::Mul(9313, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14898PolyExtStep::Sub(9309, 9314), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14899PolyExtStep::AndEqz(5555, 7562), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14900PolyExtStep::AndEqz(5556, 593), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14901PolyExtStep::AndEqz(5557, 596), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14902PolyExtStep::AndEqz(5558, 603), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14903PolyExtStep::AndEqz(5559, 610), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14904PolyExtStep::AndEqz(5560, 617), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14905PolyExtStep::AndEqz(5561, 624), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14906PolyExtStep::AndEqz(5562, 631), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14907PolyExtStep::AndEqz(5563, 634), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14908PolyExtStep::AndEqz(5564, 641), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14909PolyExtStep::AndEqz(5565, 648), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14910PolyExtStep::AndEqz(5566, 651), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14911PolyExtStep::AndEqz(5567, 654), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14912PolyExtStep::AndEqz(5568, 661), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14913PolyExtStep::AndEqz(5569, 668), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14914PolyExtStep::AndEqz(5570, 675), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14915PolyExtStep::AndEqz(5571, 1679), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14916PolyExtStep::AndEqz(5572, 546), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14917PolyExtStep::AndEqz(5573, 7564), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14918PolyExtStep::AndEqz(5574, 1634), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14919PolyExtStep::AndEqz(5575, 558), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14920PolyExtStep::AndEqz(5576, 2927), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14921PolyExtStep::AndEqz(5577, 1642), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14922PolyExtStep::AndEqz(5578, 2089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14923PolyExtStep::AndEqz(5579, 2091), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14924PolyExtStep::AndEqz(5580, 2097), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14925PolyExtStep::AndEqz(5581, 2103), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14926PolyExtStep::AndEqz(5582, 2109), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14927PolyExtStep::AndEqz(5583, 2115), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14928PolyExtStep::AndEqz(5584, 2121), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14929PolyExtStep::AndEqz(5585, 2123), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14930PolyExtStep::AndEqz(5586, 2129), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14931PolyExtStep::Mul(632, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14932PolyExtStep::Mul(639, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14933PolyExtStep::Mul(646, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14934PolyExtStep::Mul(649, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14935PolyExtStep::Mul(659, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14936PolyExtStep::Mul(666, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14937PolyExtStep::Mul(673, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14938PolyExtStep::Add(7522, 9316), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14939PolyExtStep::Add(9323, 9317), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14940PolyExtStep::Add(9324, 9318), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14941PolyExtStep::Add(9325, 9319), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14942PolyExtStep::Add(9326, 697), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14943PolyExtStep::Add(9327, 9320), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14944PolyExtStep::Add(9328, 9321), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14945PolyExtStep::Add(9329, 9322), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14946PolyExtStep::Mul(571, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14947PolyExtStep::Mul(570, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14948PolyExtStep::Mul(572, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14949PolyExtStep::Mul(573, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14950PolyExtStep::Mul(574, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14951PolyExtStep::Mul(575, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14952PolyExtStep::Mul(576, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14953PolyExtStep::Mul(577, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14954PolyExtStep::Add(7547, 9331), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14955PolyExtStep::Add(9339, 9332), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14956PolyExtStep::Add(9340, 9333), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14957PolyExtStep::Add(9341, 9334), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14958PolyExtStep::Add(9342, 9335), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14959PolyExtStep::Add(9343, 9336), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14960PolyExtStep::Add(9344, 9337), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14961PolyExtStep::Add(9345, 9338), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
14962PolyExtStep::Sub(9330, 9308), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14963PolyExtStep::AndEqz(5587, 9347), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14964PolyExtStep::Sub(9346, 9315), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14965PolyExtStep::AndEqz(5588, 9348), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
14966PolyExtStep::Mul(1084, 51), // loc(callsite( builtin Mul at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :154:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14967PolyExtStep::Mul(1085, 313), // loc(callsite( builtin Mul at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :154:48) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14968PolyExtStep::Add(9349, 9350), // loc(callsite( builtin Add at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :154:30) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14969PolyExtStep::AndEqz(5589, 4095), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :20:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14970PolyExtStep::AndEqz(5590, 4096), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :21:30) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14971PolyExtStep::Sub(4732, 808), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14972PolyExtStep::AndEqz(5591, 9352), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14973PolyExtStep::AndEqz(5592, 4098), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14974PolyExtStep::AndEqz(5593, 4099), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :24:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14975PolyExtStep::AndEqz(5594, 7420), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :25:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14976PolyExtStep::Sub(9351, 810), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14977PolyExtStep::AndEqz(5595, 9353), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
14978PolyExtStep::AndEqz(5596, 899), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14979PolyExtStep::AndEqz(5597, 914), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14980PolyExtStep::AndEqz(5598, 926), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14981PolyExtStep::AndEqz(5599, 972), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14982PolyExtStep::AndEqz(5600, 984), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14983PolyExtStep::AndEqz(5601, 999), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14984PolyExtStep::AndEqz(5602, 1054), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14985PolyExtStep::AndEqz(5603, 1060), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14986PolyExtStep::AndEqz(5604, 1066), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14987PolyExtStep::AndCond(5454, 383, 5605), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
14988PolyExtStep::Get(552), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14989PolyExtStep::Get(557), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14990PolyExtStep::Get(562), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14991PolyExtStep::Get(567), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14992PolyExtStep::Get(572), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14993PolyExtStep::Get(577), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14994PolyExtStep::Get(582), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14995PolyExtStep::Get(587), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14996PolyExtStep::Get(592), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14997PolyExtStep::Get(597), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14998PolyExtStep::Get(602), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
14999PolyExtStep::Get(607), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15000PolyExtStep::Get(612), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15001PolyExtStep::Get(617), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15002PolyExtStep::Get(622), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15003PolyExtStep::Get(627), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15004PolyExtStep::Get(632), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15005PolyExtStep::Get(637), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15006PolyExtStep::Get(642), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15007PolyExtStep::Get(647), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15008PolyExtStep::Get(652), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15009PolyExtStep::Get(657), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15010PolyExtStep::Get(662), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15011PolyExtStep::Get(667), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15012PolyExtStep::Get(672), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15013PolyExtStep::Get(677), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15014PolyExtStep::Get(682), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15015PolyExtStep::Get(687), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15016PolyExtStep::Get(692), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15017PolyExtStep::Get(697), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15018PolyExtStep::Get(702), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15019PolyExtStep::Get(707), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15020PolyExtStep::Get(553), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15021PolyExtStep::Get(558), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15022PolyExtStep::Get(563), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15023PolyExtStep::Get(568), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15024PolyExtStep::Get(573), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15025PolyExtStep::Get(578), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15026PolyExtStep::Get(583), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15027PolyExtStep::Get(588), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15028PolyExtStep::Get(593), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15029PolyExtStep::Get(598), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15030PolyExtStep::Get(603), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15031PolyExtStep::Get(608), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15032PolyExtStep::Get(613), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15033PolyExtStep::Get(618), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15034PolyExtStep::Get(623), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15035PolyExtStep::Get(628), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15036PolyExtStep::Get(633), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15037PolyExtStep::Get(638), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15038PolyExtStep::Get(643), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15039PolyExtStep::Get(648), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15040PolyExtStep::Get(653), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15041PolyExtStep::Get(658), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15042PolyExtStep::Get(663), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15043PolyExtStep::Get(668), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15044PolyExtStep::Get(673), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15045PolyExtStep::Get(678), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15046PolyExtStep::Get(683), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15047PolyExtStep::Get(688), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15048PolyExtStep::Get(693), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15049PolyExtStep::Get(698), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15050PolyExtStep::Get(703), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15051PolyExtStep::Get(708), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15052PolyExtStep::Get(554), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15053PolyExtStep::Get(559), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15054PolyExtStep::Get(564), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15055PolyExtStep::Get(569), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15056PolyExtStep::Get(574), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15057PolyExtStep::Get(579), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15058PolyExtStep::Get(584), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15059PolyExtStep::Get(589), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15060PolyExtStep::Get(594), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15061PolyExtStep::Get(599), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15062PolyExtStep::Get(604), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15063PolyExtStep::Get(609), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15064PolyExtStep::Get(614), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15065PolyExtStep::Get(619), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15066PolyExtStep::Get(624), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15067PolyExtStep::Get(629), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15068PolyExtStep::Get(634), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15069PolyExtStep::Get(639), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15070PolyExtStep::Get(644), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15071PolyExtStep::Get(649), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15072PolyExtStep::Get(654), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15073PolyExtStep::Get(659), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15074PolyExtStep::Get(664), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15075PolyExtStep::Get(669), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15076PolyExtStep::Get(674), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15077PolyExtStep::Get(679), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15078PolyExtStep::Get(684), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15079PolyExtStep::Get(689), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15080PolyExtStep::Get(694), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15081PolyExtStep::Get(699), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15082PolyExtStep::Get(704), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15083PolyExtStep::Get(709), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15084PolyExtStep::Get(555), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15085PolyExtStep::Get(560), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15086PolyExtStep::Get(565), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15087PolyExtStep::Get(570), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15088PolyExtStep::Get(575), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15089PolyExtStep::Get(580), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15090PolyExtStep::Get(585), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15091PolyExtStep::Get(590), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15092PolyExtStep::Get(595), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15093PolyExtStep::Get(600), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15094PolyExtStep::Get(605), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15095PolyExtStep::Get(610), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15096PolyExtStep::Get(615), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15097PolyExtStep::Get(620), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15098PolyExtStep::Get(625), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15099PolyExtStep::Get(630), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15100PolyExtStep::Get(635), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15101PolyExtStep::Get(640), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15102PolyExtStep::Get(645), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15103PolyExtStep::Get(650), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15104PolyExtStep::Get(655), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15105PolyExtStep::Get(660), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15106PolyExtStep::Get(665), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15107PolyExtStep::Get(670), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15108PolyExtStep::Get(675), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15109PolyExtStep::Get(680), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15110PolyExtStep::Get(685), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15111PolyExtStep::Get(690), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15112PolyExtStep::Get(695), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15113PolyExtStep::Get(700), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15114PolyExtStep::Get(705), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15115PolyExtStep::Get(710), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15116PolyExtStep::Sub(314, 4036), // loc(callsite( builtin Sub at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15117PolyExtStep::Mul(9482, 1087), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15118PolyExtStep::Sub(9483, 1085), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15119PolyExtStep::AndEqz(5300, 9484), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15120PolyExtStep::Mul(1084, 9482), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15121PolyExtStep::AndEqz(5607, 9485), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15122PolyExtStep::AndEqz(5608, 7391), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15123PolyExtStep::Add(4035, 23), // loc(callsite( builtin Add at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:32) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15124PolyExtStep::Add(9486, 4036), // loc(callsite( builtin Add at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:40) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15125PolyExtStep::AndEqz(5609, 7331), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15126PolyExtStep::AndEqz(5610, 3893), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15127PolyExtStep::AndEqz(5611, 7332), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15128PolyExtStep::AndEqz(5612, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15129PolyExtStep::Sub(817, 9487), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15130PolyExtStep::AndEqz(5613, 9488), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15131PolyExtStep::AndEqz(5614, 4091), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15132PolyExtStep::AndEqz(5615, 7334), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15133PolyExtStep::AndEqz(5616, 4828), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15134PolyExtStep::AndEqz(5617, 7336), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15135PolyExtStep::Add(9436, 9421), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15136PolyExtStep::Mul(9436, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15137PolyExtStep::Mul(9490, 9421), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15138PolyExtStep::Sub(9489, 9491), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15139PolyExtStep::Add(9437, 9422), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15140PolyExtStep::Mul(9437, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15141PolyExtStep::Mul(9494, 9422), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15142PolyExtStep::Sub(9493, 9495), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15143PolyExtStep::Add(9438, 9423), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15144PolyExtStep::Mul(9438, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15145PolyExtStep::Mul(9498, 9423), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15146PolyExtStep::Sub(9497, 9499), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15147PolyExtStep::Add(9439, 9424), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15148PolyExtStep::Mul(9439, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15149PolyExtStep::Mul(9502, 9424), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15150PolyExtStep::Sub(9501, 9503), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15151PolyExtStep::Add(9440, 9425), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15152PolyExtStep::Mul(9440, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15153PolyExtStep::Mul(9506, 9425), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15154PolyExtStep::Sub(9505, 9507), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15155PolyExtStep::Add(9441, 9426), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15156PolyExtStep::Mul(9441, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15157PolyExtStep::Mul(9510, 9426), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15158PolyExtStep::Sub(9509, 9511), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15159PolyExtStep::Add(9442, 9427), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15160PolyExtStep::Mul(9442, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15161PolyExtStep::Mul(9514, 9427), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15162PolyExtStep::Sub(9513, 9515), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15163PolyExtStep::Add(9443, 9428), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15164PolyExtStep::Mul(9443, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15165PolyExtStep::Mul(9518, 9428), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15166PolyExtStep::Sub(9517, 9519), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15167PolyExtStep::Add(9444, 9429), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15168PolyExtStep::Mul(9444, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15169PolyExtStep::Mul(9522, 9429), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15170PolyExtStep::Sub(9521, 9523), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15171PolyExtStep::Add(9445, 9430), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15172PolyExtStep::Mul(9445, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15173PolyExtStep::Mul(9526, 9430), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15174PolyExtStep::Sub(9525, 9527), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15175PolyExtStep::Add(9446, 9431), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15176PolyExtStep::Mul(9446, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15177PolyExtStep::Mul(9530, 9431), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15178PolyExtStep::Sub(9529, 9531), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15179PolyExtStep::Add(9447, 9432), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15180PolyExtStep::Mul(9447, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15181PolyExtStep::Mul(9534, 9432), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15182PolyExtStep::Sub(9533, 9535), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15183PolyExtStep::Add(9448, 9433), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15184PolyExtStep::Mul(9448, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15185PolyExtStep::Mul(9538, 9433), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15186PolyExtStep::Sub(9537, 9539), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15187PolyExtStep::Add(9449, 9434), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15188PolyExtStep::Mul(9449, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15189PolyExtStep::Mul(9542, 9434), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15190PolyExtStep::Sub(9541, 9543), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15191PolyExtStep::Add(9418, 9435), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15192PolyExtStep::Mul(9418, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15193PolyExtStep::Mul(9546, 9435), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15194PolyExtStep::Sub(9545, 9547), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15195PolyExtStep::Add(9419, 9436), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15196PolyExtStep::Mul(9419, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15197PolyExtStep::Mul(9550, 9436), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15198PolyExtStep::Sub(9549, 9551), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15199PolyExtStep::Add(9420, 9437), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15200PolyExtStep::Mul(9420, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15201PolyExtStep::Mul(9554, 9437), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15202PolyExtStep::Sub(9553, 9555), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15203PolyExtStep::Add(9421, 9438), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15204PolyExtStep::Mul(9421, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15205PolyExtStep::Mul(9558, 9438), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15206PolyExtStep::Sub(9557, 9559), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15207PolyExtStep::Add(9422, 9439), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15208PolyExtStep::Mul(9422, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15209PolyExtStep::Mul(9562, 9439), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15210PolyExtStep::Sub(9561, 9563), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15211PolyExtStep::Add(9423, 9440), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15212PolyExtStep::Mul(9423, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15213PolyExtStep::Mul(9566, 9440), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15214PolyExtStep::Sub(9565, 9567), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15215PolyExtStep::Add(9424, 9441), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15216PolyExtStep::Mul(9424, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15217PolyExtStep::Mul(9570, 9441), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15218PolyExtStep::Sub(9569, 9571), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15219PolyExtStep::Add(9425, 9442), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15220PolyExtStep::Mul(9425, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15221PolyExtStep::Mul(9574, 9442), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15222PolyExtStep::Sub(9573, 9575), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15223PolyExtStep::Add(9426, 9443), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15224PolyExtStep::Mul(9426, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15225PolyExtStep::Mul(9578, 9443), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15226PolyExtStep::Sub(9577, 9579), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15227PolyExtStep::Add(9427, 9444), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15228PolyExtStep::Mul(9427, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15229PolyExtStep::Mul(9582, 9444), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15230PolyExtStep::Sub(9581, 9583), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15231PolyExtStep::Add(9428, 9445), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15232PolyExtStep::Mul(9428, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15233PolyExtStep::Mul(9586, 9445), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15234PolyExtStep::Sub(9585, 9587), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15235PolyExtStep::Add(9429, 9446), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15236PolyExtStep::Mul(9429, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15237PolyExtStep::Mul(9590, 9446), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15238PolyExtStep::Sub(9589, 9591), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15239PolyExtStep::Add(9430, 9447), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15240PolyExtStep::Mul(9430, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15241PolyExtStep::Mul(9594, 9447), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15242PolyExtStep::Sub(9593, 9595), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15243PolyExtStep::Add(9431, 9448), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15244PolyExtStep::Mul(9431, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15245PolyExtStep::Mul(9598, 9448), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15246PolyExtStep::Sub(9597, 9599), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15247PolyExtStep::Add(9432, 9449), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15248PolyExtStep::Mul(9432, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15249PolyExtStep::Mul(9602, 9449), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15250PolyExtStep::Sub(9601, 9603), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15251PolyExtStep::Add(9425, 9492), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15252PolyExtStep::Mul(9574, 9492), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15253PolyExtStep::Sub(9605, 9606), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15254PolyExtStep::Add(9426, 9496), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15255PolyExtStep::Mul(9578, 9496), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15256PolyExtStep::Sub(9608, 9609), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15257PolyExtStep::Add(9427, 9500), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15258PolyExtStep::Mul(9582, 9500), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15259PolyExtStep::Sub(9611, 9612), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15260PolyExtStep::Add(9428, 9504), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15261PolyExtStep::Mul(9586, 9504), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15262PolyExtStep::Sub(9614, 9615), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15263PolyExtStep::Add(9429, 9508), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15264PolyExtStep::Mul(9590, 9508), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15265PolyExtStep::Sub(9617, 9618), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15266PolyExtStep::Add(9430, 9512), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15267PolyExtStep::Mul(9594, 9512), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15268PolyExtStep::Sub(9620, 9621), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15269PolyExtStep::Add(9431, 9516), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15270PolyExtStep::Mul(9598, 9516), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15271PolyExtStep::Sub(9623, 9624), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15272PolyExtStep::Add(9432, 9520), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15273PolyExtStep::Mul(9602, 9520), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15274PolyExtStep::Sub(9626, 9627), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15275PolyExtStep::Add(9433, 9524), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15276PolyExtStep::Mul(9433, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15277PolyExtStep::Mul(9630, 9524), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15278PolyExtStep::Sub(9629, 9631), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15279PolyExtStep::Add(9434, 9528), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15280PolyExtStep::Mul(9434, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15281PolyExtStep::Mul(9634, 9528), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15282PolyExtStep::Sub(9633, 9635), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15283PolyExtStep::Add(9435, 9532), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15284PolyExtStep::Mul(9435, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15285PolyExtStep::Mul(9638, 9532), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15286PolyExtStep::Sub(9637, 9639), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15287PolyExtStep::Add(9436, 9536), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15288PolyExtStep::Mul(9490, 9536), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15289PolyExtStep::Sub(9641, 9642), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15290PolyExtStep::Add(9437, 9540), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15291PolyExtStep::Mul(9494, 9540), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15292PolyExtStep::Sub(9644, 9645), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15293PolyExtStep::Add(9438, 9544), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15294PolyExtStep::Mul(9498, 9544), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15295PolyExtStep::Sub(9647, 9648), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15296PolyExtStep::Add(9439, 9548), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15297PolyExtStep::Mul(9502, 9548), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15298PolyExtStep::Sub(9650, 9651), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15299PolyExtStep::Add(9440, 9552), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15300PolyExtStep::Mul(9506, 9552), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15301PolyExtStep::Sub(9653, 9654), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15302PolyExtStep::Add(9441, 9556), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15303PolyExtStep::Mul(9510, 9556), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15304PolyExtStep::Sub(9656, 9657), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15305PolyExtStep::Add(9442, 9560), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15306PolyExtStep::Mul(9514, 9560), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15307PolyExtStep::Sub(9659, 9660), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15308PolyExtStep::Add(9443, 9564), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15309PolyExtStep::Mul(9518, 9564), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15310PolyExtStep::Sub(9662, 9663), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15311PolyExtStep::Add(9444, 9568), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15312PolyExtStep::Mul(9522, 9568), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15313PolyExtStep::Sub(9665, 9666), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15314PolyExtStep::Add(9445, 9572), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15315PolyExtStep::Mul(9526, 9572), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15316PolyExtStep::Sub(9668, 9669), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15317PolyExtStep::Add(9446, 9576), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15318PolyExtStep::Mul(9530, 9576), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15319PolyExtStep::Sub(9671, 9672), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15320PolyExtStep::Add(9447, 9580), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15321PolyExtStep::Mul(9534, 9580), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15322PolyExtStep::Sub(9674, 9675), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15323PolyExtStep::Add(9448, 9584), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15324PolyExtStep::Mul(9538, 9584), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15325PolyExtStep::Sub(9677, 9678), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15326PolyExtStep::Add(9449, 9588), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15327PolyExtStep::Mul(9542, 9588), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15328PolyExtStep::Sub(9680, 9681), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15329PolyExtStep::Add(9418, 9592), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15330PolyExtStep::Mul(9546, 9592), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15331PolyExtStep::Sub(9683, 9684), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15332PolyExtStep::Add(9419, 9596), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15333PolyExtStep::Mul(9550, 9596), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15334PolyExtStep::Sub(9686, 9687), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15335PolyExtStep::Add(9420, 9600), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15336PolyExtStep::Mul(9554, 9600), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15337PolyExtStep::Sub(9689, 9690), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15338PolyExtStep::Add(9421, 9604), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15339PolyExtStep::Mul(9558, 9604), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15340PolyExtStep::Sub(9692, 9693), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15341PolyExtStep::Add(9422, 9433), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15342PolyExtStep::Mul(9562, 9433), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15343PolyExtStep::Sub(9695, 9696), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15344PolyExtStep::Add(9423, 9434), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15345PolyExtStep::Mul(9566, 9434), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15346PolyExtStep::Sub(9698, 9699), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15347PolyExtStep::Add(9424, 9435), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15348PolyExtStep::Mul(9570, 9435), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15349PolyExtStep::Sub(9701, 9702), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15350PolyExtStep::Add(9373, 9364), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15351PolyExtStep::Mul(9373, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15352PolyExtStep::Mul(9705, 9364), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15353PolyExtStep::Sub(9704, 9706), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15354PolyExtStep::Add(9374, 9365), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15355PolyExtStep::Mul(9374, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15356PolyExtStep::Mul(9709, 9365), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15357PolyExtStep::Sub(9708, 9710), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15358PolyExtStep::Add(9375, 9366), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15359PolyExtStep::Mul(9375, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15360PolyExtStep::Mul(9713, 9366), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15361PolyExtStep::Sub(9712, 9714), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15362PolyExtStep::Add(9376, 9367), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15363PolyExtStep::Mul(9376, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15364PolyExtStep::Mul(9717, 9367), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15365PolyExtStep::Sub(9716, 9718), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15366PolyExtStep::Add(9377, 9368), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15367PolyExtStep::Mul(9377, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15368PolyExtStep::Mul(9721, 9368), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15369PolyExtStep::Sub(9720, 9722), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15370PolyExtStep::Add(9378, 9369), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15371PolyExtStep::Mul(9378, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15372PolyExtStep::Mul(9725, 9369), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15373PolyExtStep::Sub(9724, 9726), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15374PolyExtStep::Add(9379, 9370), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15375PolyExtStep::Mul(9379, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15376PolyExtStep::Mul(9729, 9370), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15377PolyExtStep::Sub(9728, 9730), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15378PolyExtStep::Add(9380, 9371), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15379PolyExtStep::Mul(9380, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15380PolyExtStep::Mul(9733, 9371), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15381PolyExtStep::Sub(9732, 9734), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15382PolyExtStep::Add(9381, 9372), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15383PolyExtStep::Mul(9381, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15384PolyExtStep::Mul(9737, 9372), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15385PolyExtStep::Sub(9736, 9738), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15386PolyExtStep::Add(9382, 9373), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15387PolyExtStep::Mul(9382, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15388PolyExtStep::Mul(9741, 9373), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15389PolyExtStep::Sub(9740, 9742), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15390PolyExtStep::Add(9383, 9374), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15391PolyExtStep::Mul(9383, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15392PolyExtStep::Mul(9745, 9374), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15393PolyExtStep::Sub(9744, 9746), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15394PolyExtStep::Add(9384, 9375), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15395PolyExtStep::Mul(9384, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15396PolyExtStep::Mul(9749, 9375), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15397PolyExtStep::Sub(9748, 9750), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15398PolyExtStep::Add(9385, 9376), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15399PolyExtStep::Mul(9385, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15400PolyExtStep::Mul(9753, 9376), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15401PolyExtStep::Sub(9752, 9754), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15402PolyExtStep::Add(9354, 9377), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15403PolyExtStep::Mul(9354, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15404PolyExtStep::Mul(9757, 9377), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15405PolyExtStep::Sub(9756, 9758), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15406PolyExtStep::Add(9355, 9378), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15407PolyExtStep::Mul(9355, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15408PolyExtStep::Mul(9761, 9378), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15409PolyExtStep::Sub(9760, 9762), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15410PolyExtStep::Add(9356, 9379), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15411PolyExtStep::Mul(9356, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15412PolyExtStep::Mul(9765, 9379), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15413PolyExtStep::Sub(9764, 9766), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15414PolyExtStep::Add(9357, 9380), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15415PolyExtStep::Mul(9357, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15416PolyExtStep::Mul(9769, 9380), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15417PolyExtStep::Sub(9768, 9770), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15418PolyExtStep::Add(9358, 9381), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15419PolyExtStep::Mul(9358, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15420PolyExtStep::Mul(9773, 9381), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15421PolyExtStep::Sub(9772, 9774), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15422PolyExtStep::Add(9359, 9382), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15423PolyExtStep::Mul(9359, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15424PolyExtStep::Mul(9777, 9382), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15425PolyExtStep::Sub(9776, 9778), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15426PolyExtStep::Add(9360, 9383), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15427PolyExtStep::Mul(9360, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15428PolyExtStep::Mul(9781, 9383), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15429PolyExtStep::Sub(9780, 9782), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15430PolyExtStep::Add(9361, 9384), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15431PolyExtStep::Mul(9361, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15432PolyExtStep::Mul(9785, 9384), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15433PolyExtStep::Sub(9784, 9786), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15434PolyExtStep::Add(9362, 9385), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15435PolyExtStep::Mul(9362, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15436PolyExtStep::Mul(9789, 9385), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15437PolyExtStep::Sub(9788, 9790), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15438PolyExtStep::Add(9371, 9707), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15439PolyExtStep::Mul(9371, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15440PolyExtStep::Mul(9793, 9707), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15441PolyExtStep::Sub(9792, 9794), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15442PolyExtStep::Add(9372, 9711), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15443PolyExtStep::Mul(9372, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15444PolyExtStep::Mul(9797, 9711), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15445PolyExtStep::Sub(9796, 9798), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15446PolyExtStep::Add(9373, 9715), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15447PolyExtStep::Mul(9705, 9715), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15448PolyExtStep::Sub(9800, 9801), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15449PolyExtStep::Add(9374, 9719), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15450PolyExtStep::Mul(9709, 9719), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15451PolyExtStep::Sub(9803, 9804), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15452PolyExtStep::Add(9375, 9723), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15453PolyExtStep::Mul(9713, 9723), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15454PolyExtStep::Sub(9806, 9807), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15455PolyExtStep::Add(9376, 9727), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15456PolyExtStep::Mul(9717, 9727), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15457PolyExtStep::Sub(9809, 9810), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15458PolyExtStep::Add(9377, 9731), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15459PolyExtStep::Mul(9721, 9731), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15460PolyExtStep::Sub(9812, 9813), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15461PolyExtStep::Add(9378, 9735), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15462PolyExtStep::Mul(9725, 9735), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15463PolyExtStep::Sub(9815, 9816), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15464PolyExtStep::Add(9379, 9739), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15465PolyExtStep::Mul(9729, 9739), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15466PolyExtStep::Sub(9818, 9819), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15467PolyExtStep::Add(9380, 9743), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15468PolyExtStep::Mul(9733, 9743), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15469PolyExtStep::Sub(9821, 9822), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15470PolyExtStep::Add(9381, 9747), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15471PolyExtStep::Mul(9737, 9747), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15472PolyExtStep::Sub(9824, 9825), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15473PolyExtStep::Add(9382, 9751), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15474PolyExtStep::Mul(9741, 9751), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15475PolyExtStep::Sub(9827, 9828), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15476PolyExtStep::Add(9383, 9755), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15477PolyExtStep::Mul(9745, 9755), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15478PolyExtStep::Sub(9830, 9831), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15479PolyExtStep::Add(9384, 9759), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15480PolyExtStep::Mul(9749, 9759), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15481PolyExtStep::Sub(9833, 9834), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15482PolyExtStep::Add(9385, 9763), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15483PolyExtStep::Mul(9753, 9763), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15484PolyExtStep::Sub(9836, 9837), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15485PolyExtStep::Add(9354, 9767), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15486PolyExtStep::Mul(9757, 9767), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15487PolyExtStep::Sub(9839, 9840), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15488PolyExtStep::Add(9355, 9771), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15489PolyExtStep::Mul(9761, 9771), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15490PolyExtStep::Sub(9842, 9843), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15491PolyExtStep::Add(9356, 9775), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15492PolyExtStep::Mul(9765, 9775), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15493PolyExtStep::Sub(9845, 9846), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15494PolyExtStep::Add(9357, 9779), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15495PolyExtStep::Mul(9769, 9779), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15496PolyExtStep::Sub(9848, 9849), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15497PolyExtStep::Add(9358, 9783), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15498PolyExtStep::Mul(9773, 9783), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15499PolyExtStep::Sub(9851, 9852), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15500PolyExtStep::Add(9359, 9787), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15501PolyExtStep::Mul(9777, 9787), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15502PolyExtStep::Sub(9854, 9855), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15503PolyExtStep::Add(9360, 9791), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15504PolyExtStep::Mul(9781, 9791), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15505PolyExtStep::Sub(9857, 9858), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15506PolyExtStep::Add(9361, 9363), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15507PolyExtStep::Mul(9785, 9363), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15508PolyExtStep::Sub(9860, 9861), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15509PolyExtStep::Add(9362, 9364), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15510PolyExtStep::Mul(9789, 9364), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15511PolyExtStep::Sub(9863, 9864), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15512PolyExtStep::Add(9363, 9365), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15513PolyExtStep::Mul(9363, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15514PolyExtStep::Mul(9867, 9365), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15515PolyExtStep::Sub(9866, 9868), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15516PolyExtStep::Add(9364, 9366), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15517PolyExtStep::Mul(9364, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15518PolyExtStep::Mul(9871, 9366), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15519PolyExtStep::Sub(9870, 9872), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15520PolyExtStep::Add(9365, 9367), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15521PolyExtStep::Mul(9365, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15522PolyExtStep::Mul(9875, 9367), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15523PolyExtStep::Sub(9874, 9876), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15524PolyExtStep::Add(9366, 9368), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15525PolyExtStep::Mul(9366, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15526PolyExtStep::Mul(9879, 9368), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15527PolyExtStep::Sub(9878, 9880), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15528PolyExtStep::Add(9367, 9369), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15529PolyExtStep::Mul(9367, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15530PolyExtStep::Mul(9883, 9369), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15531PolyExtStep::Sub(9882, 9884), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15532PolyExtStep::Add(9368, 9370), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15533PolyExtStep::Mul(9368, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15534PolyExtStep::Mul(9887, 9370), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15535PolyExtStep::Sub(9886, 9888), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15536PolyExtStep::Add(9369, 9371), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15537PolyExtStep::Mul(9369, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15538PolyExtStep::Mul(9891, 9371), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15539PolyExtStep::Sub(9890, 9892), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15540PolyExtStep::Add(9370, 9372), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15541PolyExtStep::Mul(9370, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15542PolyExtStep::Mul(9895, 9372), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15543PolyExtStep::Sub(9894, 9896), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15544PolyExtStep::Mul(9610, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15545PolyExtStep::Mul(9613, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15546PolyExtStep::Mul(9616, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15547PolyExtStep::Mul(9619, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15548PolyExtStep::Mul(9622, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15549PolyExtStep::Mul(9625, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15550PolyExtStep::Mul(9628, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15551PolyExtStep::Mul(9632, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15552PolyExtStep::Mul(9636, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15553PolyExtStep::Mul(9640, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15554PolyExtStep::Mul(9643, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15555PolyExtStep::Mul(9646, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15556PolyExtStep::Mul(9649, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15557PolyExtStep::Mul(9652, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15558PolyExtStep::Mul(9655, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15559PolyExtStep::Add(9607, 9898), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15560PolyExtStep::Add(9913, 9899), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15561PolyExtStep::Add(9914, 9900), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15562PolyExtStep::Add(9915, 9901), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15563PolyExtStep::Add(9916, 9902), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15564PolyExtStep::Add(9917, 9903), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15565PolyExtStep::Add(9918, 9904), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15566PolyExtStep::Add(9919, 9905), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15567PolyExtStep::Add(9920, 9906), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15568PolyExtStep::Add(9921, 9907), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15569PolyExtStep::Add(9922, 9908), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15570PolyExtStep::Add(9923, 9909), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15571PolyExtStep::Add(9924, 9910), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15572PolyExtStep::Add(9925, 9911), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15573PolyExtStep::Add(9926, 9912), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15574PolyExtStep::Mul(9661, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15575PolyExtStep::Mul(9664, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15576PolyExtStep::Mul(9667, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15577PolyExtStep::Mul(9670, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15578PolyExtStep::Mul(9673, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15579PolyExtStep::Mul(9676, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15580PolyExtStep::Mul(9679, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15581PolyExtStep::Mul(9682, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15582PolyExtStep::Mul(9685, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15583PolyExtStep::Mul(9688, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15584PolyExtStep::Mul(9691, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15585PolyExtStep::Mul(9694, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15586PolyExtStep::Mul(9697, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15587PolyExtStep::Mul(9700, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15588PolyExtStep::Mul(9703, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15589PolyExtStep::Add(9658, 9928), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15590PolyExtStep::Add(9943, 9929), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15591PolyExtStep::Add(9944, 9930), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15592PolyExtStep::Add(9945, 9931), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15593PolyExtStep::Add(9946, 9932), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15594PolyExtStep::Add(9947, 9933), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15595PolyExtStep::Add(9948, 9934), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15596PolyExtStep::Add(9949, 9935), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15597PolyExtStep::Add(9950, 9936), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15598PolyExtStep::Add(9951, 9937), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15599PolyExtStep::Add(9952, 9938), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15600PolyExtStep::Add(9953, 9939), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15601PolyExtStep::Add(9954, 9940), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15602PolyExtStep::Add(9955, 9941), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15603PolyExtStep::Add(9956, 9942), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15604PolyExtStep::Mul(9799, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15605PolyExtStep::Mul(9802, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15606PolyExtStep::Mul(9805, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15607PolyExtStep::Mul(9808, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15608PolyExtStep::Mul(9811, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15609PolyExtStep::Mul(9814, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15610PolyExtStep::Mul(9817, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15611PolyExtStep::Mul(9820, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15612PolyExtStep::Mul(9823, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15613PolyExtStep::Mul(9826, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15614PolyExtStep::Mul(9829, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15615PolyExtStep::Mul(9832, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15616PolyExtStep::Mul(9835, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15617PolyExtStep::Mul(9838, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15618PolyExtStep::Mul(9841, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15619PolyExtStep::Add(9795, 9958), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15620PolyExtStep::Add(9973, 9959), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15621PolyExtStep::Add(9974, 9960), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15622PolyExtStep::Add(9975, 9961), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15623PolyExtStep::Add(9976, 9962), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15624PolyExtStep::Add(9977, 9963), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15625PolyExtStep::Add(9978, 9964), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15626PolyExtStep::Add(9979, 9965), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15627PolyExtStep::Add(9980, 9966), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15628PolyExtStep::Add(9981, 9967), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15629PolyExtStep::Add(9982, 9968), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15630PolyExtStep::Add(9983, 9969), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15631PolyExtStep::Add(9984, 9970), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15632PolyExtStep::Add(9985, 9971), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15633PolyExtStep::Add(9986, 9972), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15634PolyExtStep::Mul(9847, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15635PolyExtStep::Mul(9850, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15636PolyExtStep::Mul(9853, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15637PolyExtStep::Mul(9856, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15638PolyExtStep::Mul(9859, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15639PolyExtStep::Mul(9862, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15640PolyExtStep::Mul(9865, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15641PolyExtStep::Mul(9869, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15642PolyExtStep::Mul(9873, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15643PolyExtStep::Mul(9877, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15644PolyExtStep::Mul(9881, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15645PolyExtStep::Mul(9885, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15646PolyExtStep::Mul(9889, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15647PolyExtStep::Mul(9893, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15648PolyExtStep::Mul(9897, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15649PolyExtStep::Add(9844, 9988), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15650PolyExtStep::Add(10003, 9989), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15651PolyExtStep::Add(10004, 9990), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15652PolyExtStep::Add(10005, 9991), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15653PolyExtStep::Add(10006, 9992), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15654PolyExtStep::Add(10007, 9993), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15655PolyExtStep::Add(10008, 9994), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15656PolyExtStep::Add(10009, 9995), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15657PolyExtStep::Add(10010, 9996), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15658PolyExtStep::Add(10011, 9997), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15659PolyExtStep::Add(10012, 9998), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15660PolyExtStep::Add(10013, 9999), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15661PolyExtStep::Add(10014, 10000), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15662PolyExtStep::Add(10015, 10001), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15663PolyExtStep::Add(10016, 10002), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15664PolyExtStep::Mul(9451, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15665PolyExtStep::Mul(9452, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15666PolyExtStep::Mul(9453, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15667PolyExtStep::Mul(9454, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15668PolyExtStep::Mul(9455, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15669PolyExtStep::Mul(9456, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15670PolyExtStep::Mul(9457, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15671PolyExtStep::Mul(9458, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15672PolyExtStep::Mul(9459, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15673PolyExtStep::Mul(9460, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15674PolyExtStep::Mul(9461, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15675PolyExtStep::Mul(9462, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15676PolyExtStep::Mul(9463, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15677PolyExtStep::Mul(9464, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15678PolyExtStep::Mul(9465, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15679PolyExtStep::Add(9450, 10018), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15680PolyExtStep::Add(10033, 10019), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15681PolyExtStep::Add(10034, 10020), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15682PolyExtStep::Add(10035, 10021), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15683PolyExtStep::Add(10036, 10022), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15684PolyExtStep::Add(10037, 10023), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15685PolyExtStep::Add(10038, 10024), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15686PolyExtStep::Add(10039, 10025), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15687PolyExtStep::Add(10040, 10026), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15688PolyExtStep::Add(10041, 10027), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15689PolyExtStep::Add(10042, 10028), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15690PolyExtStep::Add(10043, 10029), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15691PolyExtStep::Add(10044, 10030), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15692PolyExtStep::Add(10045, 10031), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15693PolyExtStep::Add(10046, 10032), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15694PolyExtStep::Mul(9467, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15695PolyExtStep::Mul(9468, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15696PolyExtStep::Mul(9469, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15697PolyExtStep::Mul(9470, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15698PolyExtStep::Mul(9471, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15699PolyExtStep::Mul(9472, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15700PolyExtStep::Mul(9473, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15701PolyExtStep::Mul(9474, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15702PolyExtStep::Mul(9475, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15703PolyExtStep::Mul(9476, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15704PolyExtStep::Mul(9477, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15705PolyExtStep::Mul(9478, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15706PolyExtStep::Mul(9479, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15707PolyExtStep::Mul(9480, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15708PolyExtStep::Mul(9481, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15709PolyExtStep::Add(9466, 10048), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15710PolyExtStep::Add(10063, 10049), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15711PolyExtStep::Add(10064, 10050), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15712PolyExtStep::Add(10065, 10051), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15713PolyExtStep::Add(10066, 10052), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15714PolyExtStep::Add(10067, 10053), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15715PolyExtStep::Add(10068, 10054), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15716PolyExtStep::Add(10069, 10055), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15717PolyExtStep::Add(10070, 10056), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15718PolyExtStep::Add(10071, 10057), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15719PolyExtStep::Add(10072, 10058), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15720PolyExtStep::Add(10073, 10059), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15721PolyExtStep::Add(10074, 10060), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15722PolyExtStep::Add(10075, 10061), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15723PolyExtStep::Add(10076, 10062), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15724PolyExtStep::Mul(9387, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15725PolyExtStep::Mul(9388, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15726PolyExtStep::Mul(9389, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15727PolyExtStep::Mul(9390, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15728PolyExtStep::Mul(9391, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15729PolyExtStep::Mul(9392, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15730PolyExtStep::Mul(9393, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15731PolyExtStep::Mul(9394, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15732PolyExtStep::Mul(9395, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15733PolyExtStep::Mul(9396, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15734PolyExtStep::Mul(9397, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15735PolyExtStep::Mul(9398, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15736PolyExtStep::Mul(9399, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15737PolyExtStep::Mul(9400, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15738PolyExtStep::Mul(9401, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15739PolyExtStep::Add(9386, 10078), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15740PolyExtStep::Add(10093, 10079), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15741PolyExtStep::Add(10094, 10080), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15742PolyExtStep::Add(10095, 10081), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15743PolyExtStep::Add(10096, 10082), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15744PolyExtStep::Add(10097, 10083), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15745PolyExtStep::Add(10098, 10084), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15746PolyExtStep::Add(10099, 10085), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15747PolyExtStep::Add(10100, 10086), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15748PolyExtStep::Add(10101, 10087), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15749PolyExtStep::Add(10102, 10088), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15750PolyExtStep::Add(10103, 10089), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15751PolyExtStep::Add(10104, 10090), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15752PolyExtStep::Add(10105, 10091), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15753PolyExtStep::Add(10106, 10092), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15754PolyExtStep::Mul(9403, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15755PolyExtStep::Mul(9404, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15756PolyExtStep::Mul(9405, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15757PolyExtStep::Mul(9406, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15758PolyExtStep::Mul(9407, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15759PolyExtStep::Mul(9408, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15760PolyExtStep::Mul(9409, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15761PolyExtStep::Mul(9410, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15762PolyExtStep::Mul(9411, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15763PolyExtStep::Mul(9412, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15764PolyExtStep::Mul(9413, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15765PolyExtStep::Mul(9414, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15766PolyExtStep::Mul(9415, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15767PolyExtStep::Mul(9416, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15768PolyExtStep::Mul(9417, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15769PolyExtStep::Add(9402, 10108), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15770PolyExtStep::Add(10123, 10109), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15771PolyExtStep::Add(10124, 10110), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15772PolyExtStep::Add(10125, 10111), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15773PolyExtStep::Add(10126, 10112), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15774PolyExtStep::Add(10127, 10113), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15775PolyExtStep::Add(10128, 10114), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15776PolyExtStep::Add(10129, 10115), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15777PolyExtStep::Add(10130, 10116), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15778PolyExtStep::Add(10131, 10117), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15779PolyExtStep::Add(10132, 10118), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15780PolyExtStep::Add(10133, 10119), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15781PolyExtStep::Add(10134, 10120), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15782PolyExtStep::Add(10135, 10121), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15783PolyExtStep::Add(10136, 10122), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15784PolyExtStep::Add(10047, 10107), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:50) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15785PolyExtStep::Add(10077, 10137), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:50) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15786PolyExtStep::Add(9987, 10138), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:33) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15787PolyExtStep::Add(10017, 10139), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:33) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15788PolyExtStep::Add(9927, 10140), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15789PolyExtStep::Add(9957, 10141), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15790PolyExtStep::AndEqz(5618, 1092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15791PolyExtStep::AndEqz(5619, 1095), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15792PolyExtStep::AndEqz(5620, 1098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15793PolyExtStep::Sub(10142, 9262), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15794PolyExtStep::Add(10143, 9261), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15795PolyExtStep::AndEqz(5621, 3995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15796PolyExtStep::AndEqz(5622, 4190), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15797PolyExtStep::AndEqz(5623, 4001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15798PolyExtStep::Sub(10145, 9269), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15799PolyExtStep::AndEqz(5624, 2135), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15800PolyExtStep::AndEqz(5625, 2137), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15801PolyExtStep::AndEqz(5626, 2139), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15802PolyExtStep::AndEqz(5627, 2145), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15803PolyExtStep::AndEqz(5628, 2151), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15804PolyExtStep::AndEqz(5629, 2157), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15805PolyExtStep::AndEqz(5630, 3068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15806PolyExtStep::AndEqz(5631, 2068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15807PolyExtStep::AndEqz(5632, 3574), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15808PolyExtStep::AndEqz(5633, 3074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15809PolyExtStep::AndEqz(5634, 2075), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15810PolyExtStep::AndEqz(5635, 3079), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15811PolyExtStep::AndEqz(5636, 2969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15812PolyExtStep::AndEqz(5637, 3001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15813PolyExtStep::AndEqz(5638, 3085), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15814PolyExtStep::AndEqz(5639, 3626), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15815PolyExtStep::AndEqz(5640, 3628), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15816PolyExtStep::AndEqz(5641, 3639), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15817PolyExtStep::AndEqz(5642, 3679), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15818PolyExtStep::AndEqz(5643, 3683), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15819PolyExtStep::AndEqz(5644, 7855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15820PolyExtStep::AndEqz(5645, 7857), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15821PolyExtStep::AndEqz(5646, 7859), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15822PolyExtStep::AndEqz(5647, 7861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15823PolyExtStep::AndEqz(5648, 3745), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15824PolyExtStep::AndEqz(5649, 734), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15825PolyExtStep::AndEqz(5650, 4987), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15826PolyExtStep::AndEqz(5651, 1735), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15827PolyExtStep::AndEqz(5652, 4989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15828PolyExtStep::AndEqz(5653, 3022), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15829PolyExtStep::AndEqz(5654, 4991), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15830PolyExtStep::AndEqz(5655, 3872), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15831PolyExtStep::Sub(8323, 10144), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15832PolyExtStep::AndEqz(5656, 10147), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15833PolyExtStep::Sub(8339, 10146), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15834PolyExtStep::AndEqz(5657, 10148), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15835PolyExtStep::AndEqz(5658, 4003), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15836PolyExtStep::AndEqz(5659, 4009), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15837PolyExtStep::AndEqz(5660, 4150), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15838PolyExtStep::Sub(9194, 9307), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15839PolyExtStep::Add(9195, 9306), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15840PolyExtStep::AndEqz(5661, 2755), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15841PolyExtStep::AndEqz(5662, 4853), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15842PolyExtStep::AndEqz(5663, 4861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15843PolyExtStep::Sub(10150, 9314), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15844PolyExtStep::AndEqz(5664, 7478), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15845PolyExtStep::AndEqz(5665, 7480), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15846PolyExtStep::AndEqz(5666, 7481), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15847PolyExtStep::AndEqz(5667, 7482), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15848PolyExtStep::AndEqz(5668, 7484), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15849PolyExtStep::AndEqz(5669, 1377), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15850PolyExtStep::AndEqz(5670, 2799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15851PolyExtStep::AndEqz(5671, 2805), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15852PolyExtStep::AndEqz(5672, 1387), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15853PolyExtStep::AndEqz(5673, 2815), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15854PolyExtStep::AndEqz(5674, 2821), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15855PolyExtStep::AndEqz(5675, 1396), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15856PolyExtStep::AndEqz(5676, 2827), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15857PolyExtStep::AndEqz(5677, 2833), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15858PolyExtStep::AndEqz(5678, 1406), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15859PolyExtStep::AndEqz(5679, 1413), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15860PolyExtStep::AndEqz(5680, 2839), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15861PolyExtStep::AndEqz(5681, 2845), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15862PolyExtStep::AndEqz(5682, 2851), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15863PolyExtStep::AndEqz(5683, 2857), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15864PolyExtStep::AndEqz(5684, 7486), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15865PolyExtStep::AndEqz(5685, 2772), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15866PolyExtStep::AndEqz(5686, 7488), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15867PolyExtStep::AndEqz(5687, 7490), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15868PolyExtStep::AndEqz(5688, 2780), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15869PolyExtStep::AndEqz(5689, 7492), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15870PolyExtStep::AndEqz(5690, 7494), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15871PolyExtStep::AndEqz(5691, 7496), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15872PolyExtStep::AndEqz(5692, 7498), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15873PolyExtStep::AndEqz(5693, 7500), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15874PolyExtStep::AndEqz(5694, 7502), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15875PolyExtStep::AndEqz(5695, 7504), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15876PolyExtStep::Sub(9285, 10149), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15877PolyExtStep::AndEqz(5696, 10152), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15878PolyExtStep::Sub(9301, 10151), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15879PolyExtStep::AndEqz(5697, 10153), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15880PolyExtStep::AndEqz(5698, 2765), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15881PolyExtStep::Get(785), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15882PolyExtStep::Sub(1, 10154), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15883PolyExtStep::Mul(10154, 10155), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15884PolyExtStep::AndEqz(5699, 10156), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15885PolyExtStep::Get(786), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15886PolyExtStep::Sub(1, 10157), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15887PolyExtStep::Mul(10157, 10158), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15888PolyExtStep::AndEqz(5700, 10159), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15889PolyExtStep::Mul(10157, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15890PolyExtStep::Mul(10154, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15891PolyExtStep::Add(10160, 10161), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15892PolyExtStep::Add(10162, 2763), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15893PolyExtStep::Mul(10163, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15894PolyExtStep::Sub(9256, 10164), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15895PolyExtStep::Add(9257, 10163), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15896PolyExtStep::Get(787), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15897PolyExtStep::Sub(1, 10167), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15898PolyExtStep::Mul(10167, 10168), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15899PolyExtStep::AndEqz(5701, 10169), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15900PolyExtStep::Get(788), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15901PolyExtStep::Sub(1, 10170), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15902PolyExtStep::Mul(10170, 10171), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15903PolyExtStep::AndEqz(5702, 10172), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15904PolyExtStep::Get(789), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15905PolyExtStep::Sub(1, 10173), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15906PolyExtStep::Mul(10173, 10174), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
15907PolyExtStep::AndEqz(5703, 10175), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15908PolyExtStep::Mul(10173, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15909PolyExtStep::Mul(10170, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15910PolyExtStep::Add(10176, 10177), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15911PolyExtStep::Add(10178, 10167), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15912PolyExtStep::Mul(10179, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15913PolyExtStep::Sub(10166, 10180), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15914PolyExtStep::AndEqz(5704, 7562), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15915PolyExtStep::AndEqz(5705, 593), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15916PolyExtStep::AndEqz(5706, 596), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15917PolyExtStep::AndEqz(5707, 603), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15918PolyExtStep::AndEqz(5708, 610), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15919PolyExtStep::AndEqz(5709, 617), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15920PolyExtStep::AndEqz(5710, 624), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15921PolyExtStep::AndEqz(5711, 631), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15922PolyExtStep::AndEqz(5712, 634), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15923PolyExtStep::AndEqz(5713, 641), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15924PolyExtStep::AndEqz(5714, 648), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15925PolyExtStep::AndEqz(5715, 651), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15926PolyExtStep::AndEqz(5716, 654), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15927PolyExtStep::AndEqz(5717, 661), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15928PolyExtStep::AndEqz(5718, 668), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15929PolyExtStep::AndEqz(5719, 675), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15930PolyExtStep::AndEqz(5720, 1679), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15931PolyExtStep::AndEqz(5721, 546), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15932PolyExtStep::AndEqz(5722, 7564), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15933PolyExtStep::AndEqz(5723, 1634), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15934PolyExtStep::AndEqz(5724, 558), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15935PolyExtStep::AndEqz(5725, 2927), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15936PolyExtStep::AndEqz(5726, 1642), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15937PolyExtStep::AndEqz(5727, 2089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15938PolyExtStep::AndEqz(5728, 2091), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15939PolyExtStep::AndEqz(5729, 2097), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15940PolyExtStep::AndEqz(5730, 2103), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15941PolyExtStep::AndEqz(5731, 2109), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15942PolyExtStep::AndEqz(5732, 2115), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15943PolyExtStep::AndEqz(5733, 2121), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15944PolyExtStep::AndEqz(5734, 2123), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15945PolyExtStep::AndEqz(5735, 2129), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
15946PolyExtStep::Sub(9330, 10165), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15947PolyExtStep::AndEqz(5736, 10182), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15948PolyExtStep::Sub(9346, 10181), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15949PolyExtStep::AndEqz(5737, 10183), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
15950PolyExtStep::Mul(1084, 315), // loc(callsite( builtin Mul at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :182:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15951PolyExtStep::Mul(1085, 51), // loc(callsite( builtin Mul at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :182:55) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15952PolyExtStep::Add(10184, 10185), // loc(callsite( builtin Add at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :182:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15953PolyExtStep::AndEqz(5738, 4095), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :20:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15954PolyExtStep::AndEqz(5739, 4096), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :21:30) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15955PolyExtStep::AndEqz(5740, 4097), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15956PolyExtStep::AndEqz(5741, 4098), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15957PolyExtStep::AndEqz(5742, 4099), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :24:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15958PolyExtStep::AndEqz(5743, 7420), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :25:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15959PolyExtStep::Sub(10186, 810), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15960PolyExtStep::AndEqz(5744, 10187), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
15961PolyExtStep::AndEqz(5745, 841), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15962PolyExtStep::AndEqz(5746, 856), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15963PolyExtStep::AndEqz(5747, 899), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15964PolyExtStep::AndEqz(5748, 914), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15965PolyExtStep::AndEqz(5749, 926), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15966PolyExtStep::AndEqz(5750, 972), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15967PolyExtStep::AndEqz(5751, 984), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15968PolyExtStep::AndEqz(5752, 999), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15969PolyExtStep::AndEqz(5753, 1017), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15970PolyExtStep::AndEqz(5754, 1054), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15971PolyExtStep::AndEqz(5755, 1060), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15972PolyExtStep::AndEqz(5756, 1066), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15973PolyExtStep::AndCond(5606, 386, 5757), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
15974PolyExtStep::Get(172), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15975PolyExtStep::Get(178), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15976PolyExtStep::Get(184), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15977PolyExtStep::Get(190), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15978PolyExtStep::Get(196), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15979PolyExtStep::Get(202), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15980PolyExtStep::Get(208), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15981PolyExtStep::Get(214), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15982PolyExtStep::Get(220), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15983PolyExtStep::Get(226), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15984PolyExtStep::Get(232), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15985PolyExtStep::Get(238), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15986PolyExtStep::Get(244), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15987PolyExtStep::Get(250), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15988PolyExtStep::Get(256), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15989PolyExtStep::Get(262), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15990PolyExtStep::Get(268), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15991PolyExtStep::Get(274), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15992PolyExtStep::Get(280), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15993PolyExtStep::Get(286), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15994PolyExtStep::Get(292), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15995PolyExtStep::Get(298), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15996PolyExtStep::Get(304), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15997PolyExtStep::Get(310), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15998PolyExtStep::Get(316), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
15999PolyExtStep::Get(322), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16000PolyExtStep::Get(328), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16001PolyExtStep::Get(334), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16002PolyExtStep::Get(340), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16003PolyExtStep::Get(346), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16004PolyExtStep::Get(352), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16005PolyExtStep::Get(358), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16006PolyExtStep::Get(364), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16007PolyExtStep::Get(370), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16008PolyExtStep::Get(376), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16009PolyExtStep::Get(382), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16010PolyExtStep::Get(388), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16011PolyExtStep::Get(394), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16012PolyExtStep::Get(400), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16013PolyExtStep::Get(406), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16014PolyExtStep::Get(412), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16015PolyExtStep::Get(418), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16016PolyExtStep::Get(424), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16017PolyExtStep::Get(430), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16018PolyExtStep::Get(436), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16019PolyExtStep::Get(442), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16020PolyExtStep::Get(448), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16021PolyExtStep::Get(454), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16022PolyExtStep::Get(460), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16023PolyExtStep::Get(466), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16024PolyExtStep::Get(472), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16025PolyExtStep::Get(478), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16026PolyExtStep::Get(484), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16027PolyExtStep::Get(490), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16028PolyExtStep::Get(496), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16029PolyExtStep::Get(502), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16030PolyExtStep::Get(508), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16031PolyExtStep::Get(514), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16032PolyExtStep::Get(520), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16033PolyExtStep::Get(526), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16034PolyExtStep::Get(532), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16035PolyExtStep::Get(538), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16036PolyExtStep::Get(544), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16037PolyExtStep::Get(550), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16038PolyExtStep::Sub(4034, 1084), // loc(callsite( builtin Sub at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :192:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16039PolyExtStep::Mul(10252, 1093), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :193:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16040PolyExtStep::Sub(10253, 1091), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :193:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16041PolyExtStep::AndEqz(5304, 10254), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :193:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16042PolyExtStep::Mul(1090, 10252), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :193:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16043PolyExtStep::AndEqz(5759, 10255), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :193:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16044PolyExtStep::AndEqz(5760, 7395), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :193:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16045PolyExtStep::Mul(1084, 313), // loc(callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :197:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16046PolyExtStep::Mul(1085, 315), // loc(callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :197:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16047PolyExtStep::Add(10256, 10257), // loc(callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :197:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16048PolyExtStep::Mul(10258, 1091), // loc(callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :194:17) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16049PolyExtStep::Add(7396, 10259), // loc(callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :194:17) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16050PolyExtStep::Mul(10189, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16051PolyExtStep::Mul(10190, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16052PolyExtStep::Mul(10191, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16053PolyExtStep::Mul(10192, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16054PolyExtStep::Mul(10193, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16055PolyExtStep::Mul(10194, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16056PolyExtStep::Mul(10195, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16057PolyExtStep::Mul(10196, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16058PolyExtStep::Mul(10197, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16059PolyExtStep::Mul(10198, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16060PolyExtStep::Mul(10199, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16061PolyExtStep::Mul(10200, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16062PolyExtStep::Mul(10201, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16063PolyExtStep::Mul(10202, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16064PolyExtStep::Mul(10203, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16065PolyExtStep::Add(10188, 10261), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16066PolyExtStep::Add(10276, 10262), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16067PolyExtStep::Add(10277, 10263), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16068PolyExtStep::Add(10278, 10264), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16069PolyExtStep::Add(10279, 10265), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16070PolyExtStep::Add(10280, 10266), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16071PolyExtStep::Add(10281, 10267), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16072PolyExtStep::Add(10282, 10268), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16073PolyExtStep::Add(10283, 10269), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16074PolyExtStep::Add(10284, 10270), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16075PolyExtStep::Add(10285, 10271), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16076PolyExtStep::Add(10286, 10272), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16077PolyExtStep::Add(10287, 10273), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16078PolyExtStep::Add(10288, 10274), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16079PolyExtStep::Add(10289, 10275), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16080PolyExtStep::Mul(10205, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16081PolyExtStep::Mul(10206, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16082PolyExtStep::Mul(10207, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16083PolyExtStep::Mul(10208, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16084PolyExtStep::Mul(10209, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16085PolyExtStep::Mul(10210, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16086PolyExtStep::Mul(10211, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16087PolyExtStep::Mul(10212, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16088PolyExtStep::Mul(10213, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16089PolyExtStep::Mul(10214, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16090PolyExtStep::Mul(10215, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16091PolyExtStep::Mul(10216, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16092PolyExtStep::Mul(10217, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16093PolyExtStep::Mul(10218, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16094PolyExtStep::Mul(10219, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16095PolyExtStep::Add(10204, 10291), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16096PolyExtStep::Add(10306, 10292), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16097PolyExtStep::Add(10307, 10293), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16098PolyExtStep::Add(10308, 10294), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16099PolyExtStep::Add(10309, 10295), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16100PolyExtStep::Add(10310, 10296), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16101PolyExtStep::Add(10311, 10297), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16102PolyExtStep::Add(10312, 10298), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16103PolyExtStep::Add(10313, 10299), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16104PolyExtStep::Add(10314, 10300), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16105PolyExtStep::Add(10315, 10301), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16106PolyExtStep::Add(10316, 10302), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16107PolyExtStep::Add(10317, 10303), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16108PolyExtStep::Add(10318, 10304), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16109PolyExtStep::Add(10319, 10305), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16110PolyExtStep::Add(9225, 10290), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16111PolyExtStep::Add(9255, 10320), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16112PolyExtStep::AndEqz(5761, 1098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16113PolyExtStep::AndEqz(5762, 3995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16114PolyExtStep::AndEqz(5763, 4190), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16115PolyExtStep::Mul(2737, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16116PolyExtStep::Add(10323, 4909), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16117PolyExtStep::Add(10324, 1096), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16118PolyExtStep::Mul(10325, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16119PolyExtStep::Sub(10321, 10326), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16120PolyExtStep::Add(10322, 10325), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16121PolyExtStep::AndEqz(5764, 4001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16122PolyExtStep::AndEqz(5765, 4003), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16123PolyExtStep::AndEqz(5766, 4009), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16124PolyExtStep::Mul(2750, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16125PolyExtStep::Mul(2745, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16126PolyExtStep::Add(10329, 10330), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16127PolyExtStep::Add(10331, 2744), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16128PolyExtStep::Mul(10332, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16129PolyExtStep::Sub(10328, 10333), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16130PolyExtStep::AndEqz(5767, 7478), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16131PolyExtStep::AndEqz(5768, 7480), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16132PolyExtStep::AndEqz(5769, 7481), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16133PolyExtStep::AndEqz(5770, 7482), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16134PolyExtStep::AndEqz(5771, 7484), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16135PolyExtStep::AndEqz(5772, 1377), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16136PolyExtStep::AndEqz(5773, 2799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16137PolyExtStep::AndEqz(5774, 2805), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16138PolyExtStep::AndEqz(5775, 1387), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16139PolyExtStep::AndEqz(5776, 2815), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16140PolyExtStep::AndEqz(5777, 2821), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16141PolyExtStep::AndEqz(5778, 1396), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16142PolyExtStep::AndEqz(5779, 2827), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16143PolyExtStep::AndEqz(5780, 2833), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16144PolyExtStep::AndEqz(5781, 1406), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16145PolyExtStep::AndEqz(5782, 1413), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16146PolyExtStep::AndEqz(5783, 2839), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16147PolyExtStep::AndEqz(5784, 2845), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16148PolyExtStep::AndEqz(5785, 2851), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16149PolyExtStep::AndEqz(5786, 2857), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16150PolyExtStep::AndEqz(5787, 7486), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16151PolyExtStep::AndEqz(5788, 2772), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16152PolyExtStep::AndEqz(5789, 7488), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16153PolyExtStep::AndEqz(5790, 7490), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16154PolyExtStep::AndEqz(5791, 2780), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16155PolyExtStep::AndEqz(5792, 7492), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16156PolyExtStep::AndEqz(5793, 7494), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16157PolyExtStep::AndEqz(5794, 7496), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16158PolyExtStep::AndEqz(5795, 7498), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16159PolyExtStep::AndEqz(5796, 7500), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16160PolyExtStep::AndEqz(5797, 7502), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16161PolyExtStep::AndEqz(5798, 7504), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16162PolyExtStep::Sub(9285, 10327), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16163PolyExtStep::AndEqz(5799, 10335), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16164PolyExtStep::Sub(9301, 10334), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16165PolyExtStep::AndEqz(5800, 10336), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16166PolyExtStep::Mul(10221, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16167PolyExtStep::Mul(10222, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16168PolyExtStep::Mul(10223, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16169PolyExtStep::Mul(10224, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16170PolyExtStep::Mul(10225, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16171PolyExtStep::Mul(10226, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16172PolyExtStep::Mul(10227, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16173PolyExtStep::Mul(10228, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16174PolyExtStep::Mul(10229, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16175PolyExtStep::Mul(10230, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16176PolyExtStep::Mul(10231, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16177PolyExtStep::Mul(10232, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16178PolyExtStep::Mul(10233, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16179PolyExtStep::Mul(10234, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16180PolyExtStep::Mul(10235, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16181PolyExtStep::Add(10220, 10337), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16182PolyExtStep::Add(10352, 10338), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16183PolyExtStep::Add(10353, 10339), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16184PolyExtStep::Add(10354, 10340), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16185PolyExtStep::Add(10355, 10341), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16186PolyExtStep::Add(10356, 10342), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16187PolyExtStep::Add(10357, 10343), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16188PolyExtStep::Add(10358, 10344), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16189PolyExtStep::Add(10359, 10345), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16190PolyExtStep::Add(10360, 10346), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16191PolyExtStep::Add(10361, 10347), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16192PolyExtStep::Add(10362, 10348), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16193PolyExtStep::Add(10363, 10349), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16194PolyExtStep::Add(10364, 10350), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16195PolyExtStep::Add(10365, 10351), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16196PolyExtStep::Mul(10237, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16197PolyExtStep::Mul(10238, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16198PolyExtStep::Mul(10239, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16199PolyExtStep::Mul(10240, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16200PolyExtStep::Mul(10241, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16201PolyExtStep::Mul(10242, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16202PolyExtStep::Mul(10243, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16203PolyExtStep::Mul(10244, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16204PolyExtStep::Mul(10245, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16205PolyExtStep::Mul(10246, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16206PolyExtStep::Mul(10247, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16207PolyExtStep::Mul(10248, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16208PolyExtStep::Mul(10249, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16209PolyExtStep::Mul(10250, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16210PolyExtStep::Mul(10251, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16211PolyExtStep::Add(10236, 10367), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16212PolyExtStep::Add(10382, 10368), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16213PolyExtStep::Add(10383, 10369), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16214PolyExtStep::Add(10384, 10370), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16215PolyExtStep::Add(10385, 10371), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16216PolyExtStep::Add(10386, 10372), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16217PolyExtStep::Add(10387, 10373), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16218PolyExtStep::Add(10388, 10374), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16219PolyExtStep::Add(10389, 10375), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16220PolyExtStep::Add(10390, 10376), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16221PolyExtStep::Add(10391, 10377), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16222PolyExtStep::Add(10392, 10378), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16223PolyExtStep::Add(10393, 10379), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16224PolyExtStep::Add(10394, 10380), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16225PolyExtStep::Add(10395, 10381), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16226PolyExtStep::Add(8369, 10366), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16227PolyExtStep::Add(8399, 10396), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16228PolyExtStep::AndEqz(5801, 4150), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16229PolyExtStep::AndEqz(5802, 2755), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16230PolyExtStep::AndEqz(5803, 4853), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16231PolyExtStep::Mul(2760, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16232PolyExtStep::Mul(2753, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16233PolyExtStep::Add(10399, 10400), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16234PolyExtStep::Add(10401, 2751), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16235PolyExtStep::Mul(10402, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16236PolyExtStep::Sub(10397, 10403), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16237PolyExtStep::Add(10398, 10402), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16238PolyExtStep::AndEqz(5804, 4861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16239PolyExtStep::AndEqz(5805, 2765), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16240PolyExtStep::AndEqz(5806, 10156), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16241PolyExtStep::Mul(10154, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16242PolyExtStep::Mul(2763, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16243PolyExtStep::Add(10406, 10407), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16244PolyExtStep::Add(10408, 2761), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16245PolyExtStep::Mul(10409, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16246PolyExtStep::Sub(10405, 10410), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16247PolyExtStep::AndEqz(5807, 7562), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16248PolyExtStep::AndEqz(5808, 593), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16249PolyExtStep::AndEqz(5809, 596), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16250PolyExtStep::AndEqz(5810, 603), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16251PolyExtStep::AndEqz(5811, 610), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16252PolyExtStep::AndEqz(5812, 617), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16253PolyExtStep::AndEqz(5813, 624), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16254PolyExtStep::AndEqz(5814, 631), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16255PolyExtStep::AndEqz(5815, 634), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16256PolyExtStep::AndEqz(5816, 641), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16257PolyExtStep::AndEqz(5817, 648), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16258PolyExtStep::AndEqz(5818, 651), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16259PolyExtStep::AndEqz(5819, 654), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16260PolyExtStep::AndEqz(5820, 661), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16261PolyExtStep::AndEqz(5821, 668), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16262PolyExtStep::AndEqz(5822, 675), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16263PolyExtStep::AndEqz(5823, 1679), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16264PolyExtStep::AndEqz(5824, 546), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16265PolyExtStep::AndEqz(5825, 7564), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16266PolyExtStep::AndEqz(5826, 1634), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16267PolyExtStep::AndEqz(5827, 558), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16268PolyExtStep::AndEqz(5828, 2927), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16269PolyExtStep::AndEqz(5829, 1642), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16270PolyExtStep::AndEqz(5830, 2089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16271PolyExtStep::AndEqz(5831, 2091), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16272PolyExtStep::AndEqz(5832, 2097), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16273PolyExtStep::AndEqz(5833, 2103), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16274PolyExtStep::AndEqz(5834, 2109), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16275PolyExtStep::AndEqz(5835, 2115), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16276PolyExtStep::AndEqz(5836, 2121), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16277PolyExtStep::AndEqz(5837, 2123), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16278PolyExtStep::AndEqz(5838, 2129), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16279PolyExtStep::Sub(9330, 10404), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16280PolyExtStep::AndEqz(5839, 10412), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16281PolyExtStep::Sub(9346, 10411), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16282PolyExtStep::AndEqz(5840, 10413), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16283PolyExtStep::AndEqz(5841, 4095), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :20:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16284PolyExtStep::AndEqz(5842, 4096), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :21:30) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16285PolyExtStep::AndEqz(5843, 4097), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16286PolyExtStep::Sub(10252, 1143), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16287PolyExtStep::AndEqz(5844, 10414), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16288PolyExtStep::AndEqz(5845, 4099), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :24:23) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16289PolyExtStep::AndEqz(5846, 7420), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :25:23) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16290PolyExtStep::Sub(10260, 810), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16291PolyExtStep::AndEqz(5847, 10415), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16292PolyExtStep::AndEqz(5848, 7331), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16293PolyExtStep::AndEqz(5849, 3893), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16294PolyExtStep::Sub(832, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16295PolyExtStep::AndEqz(5850, 10416), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16296PolyExtStep::AndEqz(5851, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16297PolyExtStep::Sub(817, 7408), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16298PolyExtStep::AndEqz(5852, 10417), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16299PolyExtStep::AndEqz(5853, 4828), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16300PolyExtStep::AndEqz(5854, 7336), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16301PolyExtStep::AndEqz(5855, 7507), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16302PolyExtStep::AndEqz(5856, 7510), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16303PolyExtStep::AndEqz(5857, 7340), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16304PolyExtStep::AndEqz(5858, 3992), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16305PolyExtStep::Sub(859, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16306PolyExtStep::AndEqz(5859, 10418), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16307PolyExtStep::AndEqz(5860, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16308PolyExtStep::Sub(844, 7413), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16309PolyExtStep::AndEqz(5861, 10419), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16310PolyExtStep::AndEqz(5862, 7347), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16311PolyExtStep::AndEqz(5863, 7348), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16312PolyExtStep::AndEqz(5864, 7567), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16313PolyExtStep::AndEqz(5865, 7570), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16314PolyExtStep::AndEqz(5866, 899), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16315PolyExtStep::AndEqz(5867, 914), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16316PolyExtStep::AndEqz(5868, 926), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16317PolyExtStep::AndEqz(5869, 972), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16318PolyExtStep::AndEqz(5870, 984), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16319PolyExtStep::AndEqz(5871, 999), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16320PolyExtStep::AndEqz(5872, 1054), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16321PolyExtStep::AndEqz(5873, 1060), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16322PolyExtStep::AndEqz(5874, 1066), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16323PolyExtStep::AndCond(5758, 389, 5875), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16324PolyExtStep::AndEqz(4191, 4954), // loc(callsite( Reg ( <preamble> :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :34:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :234:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16325PolyExtStep::AndEqz(5877, 814), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16326PolyExtStep::AndEqz(5878, 829), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16327PolyExtStep::AndEqz(5879, 841), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16328PolyExtStep::AndEqz(5880, 856), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16329PolyExtStep::AndEqz(5881, 899), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16330PolyExtStep::AndEqz(5882, 914), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16331PolyExtStep::AndEqz(5883, 926), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16332PolyExtStep::AndEqz(5884, 972), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16333PolyExtStep::AndEqz(5885, 984), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16334PolyExtStep::AndEqz(5886, 999), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16335PolyExtStep::AndEqz(5887, 1011), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16336PolyExtStep::AndEqz(5888, 1017), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16337PolyExtStep::AndEqz(5889, 1054), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16338PolyExtStep::AndEqz(5890, 1060), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16339PolyExtStep::AndEqz(5891, 1066), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16340PolyExtStep::AndCond(5876, 392, 5892), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16341PolyExtStep::AndCond(5893, 395, 5892), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16342PolyExtStep::AndCond(5894, 398, 5892), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16343PolyExtStep::AndCond(5243, 455, 5895), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16344PolyExtStep::Add(376, 53), // loc(callsite( builtin Add at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :172:40) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16345PolyExtStep::Sub(371, 10420), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :172:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16346PolyExtStep::Sub(935, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :171:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16347PolyExtStep::AndEqz(0, 10422), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :171:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16348PolyExtStep::Sub(972, 542), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :171:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16349PolyExtStep::AndEqz(5897, 10423), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :171:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16350PolyExtStep::AndEqz(5898, 10421), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :172:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16351PolyExtStep::Sub(1410, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16352PolyExtStep::AndEqz(0, 10424), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16353PolyExtStep::Sub(1428, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16354PolyExtStep::AndEqz(5900, 10425), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16355PolyExtStep::Sub(1829, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16356PolyExtStep::AndEqz(5901, 10426), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16357PolyExtStep::AndEqz(5902, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16358PolyExtStep::Sub(1411, 316), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16359PolyExtStep::AndEqz(5903, 10427), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16360PolyExtStep::Sub(1427, 1830), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16361PolyExtStep::AndEqz(5904, 10428), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16362PolyExtStep::Sub(1426, 1429), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16363PolyExtStep::AndEqz(5905, 10429), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16364PolyExtStep::Sub(1831, 1424), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16365PolyExtStep::AndEqz(5906, 3306), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16366PolyExtStep::Sub(742, 10430), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16367PolyExtStep::AndEqz(5907, 10431), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16368PolyExtStep::AndEqz(5908, 1429), // loc(callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :42:14) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16369PolyExtStep::Sub(1430, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16370PolyExtStep::AndEqz(5909, 10432), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16371PolyExtStep::AndEqz(5910, 1901), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16372PolyExtStep::AndEqz(5911, 541), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16373PolyExtStep::AndEqz(5912, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16374PolyExtStep::Sub(1431, 317), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16375PolyExtStep::AndEqz(5913, 10433), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16376PolyExtStep::Sub(1439, 2278), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16377PolyExtStep::AndEqz(5914, 10434), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16378PolyExtStep::Sub(1440, 539), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16379PolyExtStep::AndEqz(5915, 10435), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16380PolyExtStep::Sub(538, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16381PolyExtStep::Sub(10436, 1432), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16382PolyExtStep::AndEqz(5916, 2955), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16383PolyExtStep::Sub(744, 10437), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16384PolyExtStep::AndEqz(5917, 10438), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16385PolyExtStep::Mul(539, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16386PolyExtStep::Mul(2278, 63), // loc(callsite( builtin Mul at callsite( Div ( <preamble> :19:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16387PolyExtStep::Add(10439, 10440), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16388PolyExtStep::Sub(10441, 1), // loc(callsite( builtin Sub at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :49:13) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16389PolyExtStep::Sub(1, 807), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16390PolyExtStep::Mul(807, 10443), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16391PolyExtStep::AndEqz(5918, 10444), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16392PolyExtStep::AndEqz(5919, 10443), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16393PolyExtStep::Sub(1, 1137), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16394PolyExtStep::Mul(1137, 10445), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16395PolyExtStep::AndEqz(5920, 10446), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16396PolyExtStep::Sub(1830, 1137), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16397PolyExtStep::AndEqz(5921, 10447), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16398PolyExtStep::Sub(10442, 808), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :16:20) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16399PolyExtStep::AndEqz(5922, 10448), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :16:20) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16400PolyExtStep::AndEqz(5923, 4727), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :17:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16401PolyExtStep::AndEqz(5924, 4728), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :18:23) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16402PolyExtStep::AndEqz(5925, 4027), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16403PolyExtStep::AndEqz(5926, 4729), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16404PolyExtStep::AndEqz(5927, 3918), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16405PolyExtStep::AndEqz(5928, 3919), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16406PolyExtStep::AndEqz(5929, 3920), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16407PolyExtStep::AndEqz(5930, 4730), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16408PolyExtStep::AndEqz(5931, 3922), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16409PolyExtStep::AndEqz(5932, 3923), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16410PolyExtStep::AndEqz(5933, 3924), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16411PolyExtStep::AndEqz(5934, 3925), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16412PolyExtStep::AndEqz(5935, 3926), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16413PolyExtStep::AndEqz(5936, 3927), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16414PolyExtStep::AndEqz(5937, 3928), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16415PolyExtStep::AndEqz(5938, 3929), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16416PolyExtStep::AndEqz(5939, 3930), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16417PolyExtStep::AndEqz(5940, 3931), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16418PolyExtStep::Sub(318, 1404), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16419PolyExtStep::AndEqz(5941, 10449), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16420PolyExtStep::AndEqz(5942, 591), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16421PolyExtStep::AndEqz(5943, 622), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16422PolyExtStep::AndEqz(5944, 646), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16423PolyExtStep::AndEqz(5945, 673), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16424PolyExtStep::AndEqz(5946, 552), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16425PolyExtStep::AndEqz(5947, 571), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16426PolyExtStep::AndEqz(5948, 574), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16427PolyExtStep::AndEqz(5949, 587), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16428PolyExtStep::AndEqz(5950, 745), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16429PolyExtStep::AndEqz(5951, 747), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16430PolyExtStep::AndEqz(5952, 766), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16431PolyExtStep::AndEqz(5953, 768), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16432PolyExtStep::AndEqz(5954, 761), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16433PolyExtStep::AndEqz(5955, 771), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16434PolyExtStep::AndEqz(5956, 756), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16435PolyExtStep::AndEqz(5957, 762), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16436PolyExtStep::AndEqz(5958, 732), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16437PolyExtStep::AndEqz(5959, 764), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16438PolyExtStep::AndEqz(5960, 800), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16439PolyExtStep::AndEqz(5961, 804), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16440PolyExtStep::AndEqz(5962, 817), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16441PolyExtStep::AndEqz(5963, 823), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16442PolyExtStep::AndEqz(5964, 829), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16443PolyExtStep::AndEqz(5965, 835), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16444PolyExtStep::AndEqz(5966, 841), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16445PolyExtStep::AndEqz(5967, 847), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16446PolyExtStep::AndEqz(5968, 853), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16447PolyExtStep::AndEqz(5969, 859), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16448PolyExtStep::AndEqz(5970, 896), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16449PolyExtStep::AndEqz(5971, 902), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16450PolyExtStep::AndEqz(5972, 908), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16451PolyExtStep::AndEqz(5973, 914), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16452PolyExtStep::AndEqz(5974, 920), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16453PolyExtStep::AndEqz(5975, 926), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16454PolyExtStep::AndCond(5899, 377, 5976), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16455PolyExtStep::Sub(1411, 4732), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :118:26) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16456PolyExtStep::AndEqz(5903, 10450), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :118:26) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16457PolyExtStep::AndEqz(5978, 10428), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :118:26) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16458PolyExtStep::AndEqz(5979, 10429), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :118:26) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16459PolyExtStep::AndEqz(5980, 3306), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :118:26) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16460PolyExtStep::AndEqz(5981, 10431), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :118:26) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16461PolyExtStep::AndEqz(5982, 774), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :119:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16462PolyExtStep::AndEqz(5983, 1751), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :119:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16463PolyExtStep::Mul(772, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :119:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16464PolyExtStep::Add(10451, 770), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :119:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16465PolyExtStep::Sub(1429, 10452), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :119:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16466PolyExtStep::AndEqz(5984, 10453), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :119:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16467PolyExtStep::Mul(978, 23), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :126:4) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16468PolyExtStep::Add(10454, 975), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :126:12) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16469PolyExtStep::Sub(10455, 772), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :126:24) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16470PolyExtStep::AndEqz(5985, 10456), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :126:24) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16471PolyExtStep::AndEqz(5986, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :128:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16472PolyExtStep::AndEqz(5987, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :128:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16473PolyExtStep::AndEqz(5988, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :128:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16474PolyExtStep::AndEqz(5989, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :128:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16475PolyExtStep::AndEqz(5990, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :128:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16476PolyExtStep::Mul(987, 5), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :129:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16477PolyExtStep::Mul(990, 12), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :129:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16478PolyExtStep::Mul(993, 23), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :129:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16479PolyExtStep::Add(2322, 10457), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :129:11) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16480PolyExtStep::Add(10460, 10458), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :129:11) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16481PolyExtStep::Add(10461, 10459), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :129:11) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16482PolyExtStep::AndEqz(5991, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :131:44) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16483PolyExtStep::AndEqz(5992, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :131:44) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16484PolyExtStep::AndEqz(5993, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :131:44) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16485PolyExtStep::Mul(1002, 5), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :132:46) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16486PolyExtStep::Add(2483, 10463), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :132:13) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16487PolyExtStep::Mul(10464, 24), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :133:4) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16488PolyExtStep::Add(10465, 10462), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :133:9) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16489PolyExtStep::Sub(10466, 770), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :133:21) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16490PolyExtStep::AndEqz(5994, 10467), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :133:21) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16491PolyExtStep::Add(10462, 30), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:52) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16492PolyExtStep::AndEqz(5995, 10432), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16493PolyExtStep::AndEqz(5996, 1901), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16494PolyExtStep::AndEqz(5997, 541), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16495PolyExtStep::AndEqz(5998, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16496PolyExtStep::Sub(1431, 10468), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16497PolyExtStep::AndEqz(5999, 10469), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16498PolyExtStep::AndEqz(6000, 10434), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16499PolyExtStep::AndEqz(6001, 10435), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16500PolyExtStep::AndEqz(6002, 2955), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16501PolyExtStep::AndEqz(6003, 10438), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16502PolyExtStep::Mul(1830, 5), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:59) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16503PolyExtStep::Mul(10470, 5), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:68) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16504PolyExtStep::Add(2278, 10471), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:38) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16505PolyExtStep::Sub(908, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16506PolyExtStep::AndEqz(6004, 10473), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16507PolyExtStep::AndEqz(6005, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16508PolyExtStep::Add(2652, 911), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16509PolyExtStep::Sub(10472, 10474), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16510PolyExtStep::AndEqz(6006, 10475), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16511PolyExtStep::Add(539, 1005), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16512PolyExtStep::AndEqz(6007, 7353), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16513PolyExtStep::AndEqz(6008, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16514PolyExtStep::Add(2656, 917), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16515PolyExtStep::Sub(10476, 10477), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16516PolyExtStep::AndEqz(6009, 10478), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16517PolyExtStep::AndEqz(6010, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16518PolyExtStep::AndEqz(6011, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16519PolyExtStep::AndEqz(6012, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16520PolyExtStep::Add(1011, 1014), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16521PolyExtStep::Add(10479, 1017), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16522PolyExtStep::Sub(10480, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16523PolyExtStep::AndEqz(6013, 10481), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16524PolyExtStep::Mul(1017, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16525PolyExtStep::Add(1014, 10482), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16526PolyExtStep::Sub(10483, 978), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16527PolyExtStep::AndEqz(6014, 10484), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16528PolyExtStep::Sub(917, 15), // loc(callsite( builtin Sub at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:19) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16529PolyExtStep::Mul(4032, 16), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:24) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16530PolyExtStep::Sub(1, 4032), // loc(callsite( builtin Sub at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:41) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16531PolyExtStep::Mul(10487, 15), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:49) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16532PolyExtStep::Add(10486, 10488), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:31) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16533PolyExtStep::Sub(10489, 917), // loc(callsite( builtin Sub at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:53) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16534PolyExtStep::Mul(917, 14), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:19) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16535PolyExtStep::AndEqz(0, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16536PolyExtStep::Mul(10485, 1066), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16537PolyExtStep::Sub(10492, 1064), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16538PolyExtStep::AndEqz(6016, 10493), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16539PolyExtStep::Mul(1063, 10485), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16540PolyExtStep::AndEqz(6017, 10494), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16541PolyExtStep::AndEqz(6018, 3362), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16542PolyExtStep::AndEqz(6019, 1063), // loc(callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:34) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16543PolyExtStep::AndEqz(6020, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :81:31) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16544PolyExtStep::AndEqz(6021, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16545PolyExtStep::AndEqz(6022, 4777), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16546PolyExtStep::Sub(923, 10490), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16547PolyExtStep::AndEqz(6023, 10495), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16548PolyExtStep::AndEqz(6024, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16549PolyExtStep::Mul(917, 1060), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16550PolyExtStep::Sub(10496, 1058), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16551PolyExtStep::AndEqz(6025, 10497), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16552PolyExtStep::Mul(1057, 917), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))
16553PolyExtStep::AndEqz(6026, 10498), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16554PolyExtStep::AndEqz(6027, 3385), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16555PolyExtStep::AndEqz(6028, 1057), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:19) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16556PolyExtStep::Sub(926, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16557PolyExtStep::AndEqz(6029, 10499), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16558PolyExtStep::Mul(929, 5), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:4) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16559PolyExtStep::Add(10500, 1114), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:12) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16560PolyExtStep::Sub(10501, 911), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16561PolyExtStep::AndEqz(6030, 10502), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16562PolyExtStep::Add(10491, 929), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:30) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16563PolyExtStep::AndEqz(6031, 1114), // loc(callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :67:14) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16564PolyExtStep::Sub(591, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16565PolyExtStep::AndEqz(6032, 10504), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16566PolyExtStep::AndEqz(6033, 3958), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16567PolyExtStep::Sub(629, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16568PolyExtStep::AndEqz(6034, 10505), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16569PolyExtStep::AndEqz(6035, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16570PolyExtStep::Sub(594, 10503), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16571PolyExtStep::AndEqz(6036, 10506), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16572PolyExtStep::AndEqz(6037, 3957), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16573PolyExtStep::Sub(615, 639), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16574PolyExtStep::AndEqz(6038, 10507), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16575PolyExtStep::Sub(2295, 601), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16576PolyExtStep::AndEqz(6039, 754), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16577PolyExtStep::Sub(746, 10508), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16578PolyExtStep::AndEqz(6040, 10509), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16579PolyExtStep::AndEqz(6041, 758), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16580PolyExtStep::AndEqz(6042, 782), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16581PolyExtStep::Add(8324, 757), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16582PolyExtStep::Sub(632, 10510), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16583PolyExtStep::AndEqz(6043, 10511), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16584PolyExtStep::AndEqz(6044, 1758), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16585PolyExtStep::AndEqz(6045, 3020), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16586PolyExtStep::Mul(798, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16587PolyExtStep::Add(10512, 737), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16588PolyExtStep::Sub(639, 10513), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16589PolyExtStep::AndEqz(6046, 10514), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16590PolyExtStep::Add(10503, 1), // loc(callsite( builtin Add at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:33) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16591PolyExtStep::Sub(646, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16592PolyExtStep::AndEqz(6047, 10516), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16593PolyExtStep::AndEqz(6048, 2346), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16594PolyExtStep::Sub(676, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16595PolyExtStep::AndEqz(6049, 10517), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16596PolyExtStep::AndEqz(6050, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16597PolyExtStep::Sub(649, 10515), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16598PolyExtStep::AndEqz(6051, 10518), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16599PolyExtStep::AndEqz(6052, 3969), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16600PolyExtStep::AndEqz(6053, 3700), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16601PolyExtStep::Sub(2921, 652), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16602PolyExtStep::AndEqz(6054, 1745), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16603PolyExtStep::Sub(760, 10519), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16604PolyExtStep::AndEqz(6055, 10520), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16605PolyExtStep::Sub(800, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16606PolyExtStep::AndEqz(6056, 10521), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16607PolyExtStep::AndEqz(6057, 2216), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16608PolyExtStep::Mul(814, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16609PolyExtStep::Add(10522, 802), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16610PolyExtStep::Sub(544, 10523), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16611PolyExtStep::AndEqz(6058, 10524), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16612PolyExtStep::Sub(817, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16613PolyExtStep::AndEqz(6059, 10525), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16614PolyExtStep::AndEqz(6060, 3144), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16615PolyExtStep::Mul(826, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16616PolyExtStep::Add(10526, 820), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16617PolyExtStep::Sub(551, 10527), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16618PolyExtStep::AndEqz(6061, 10528), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16619PolyExtStep::Add(10503, 7), // loc(callsite( builtin Add at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:33) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16620PolyExtStep::Sub(552, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16621PolyExtStep::AndEqz(6062, 10530), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16622PolyExtStep::AndEqz(6063, 1647), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16623PolyExtStep::AndEqz(6064, 3555), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16624PolyExtStep::AndEqz(6065, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16625PolyExtStep::Sub(555, 10529), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16626PolyExtStep::AndEqz(6066, 10531), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16627PolyExtStep::AndEqz(6067, 3981), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16628PolyExtStep::Sub(564, 573), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16629PolyExtStep::AndEqz(6068, 10532), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16630PolyExtStep::Sub(3034, 556), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16631PolyExtStep::AndEqz(6069, 3339), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16632PolyExtStep::Sub(767, 10533), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16633PolyExtStep::AndEqz(6070, 10534), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16634PolyExtStep::AndEqz(6071, 3893), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16635PolyExtStep::AndEqz(6072, 2223), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16636PolyExtStep::Add(869, 832), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16637PolyExtStep::Sub(572, 10535), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16638PolyExtStep::AndEqz(6073, 10536), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16639PolyExtStep::Sub(841, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16640PolyExtStep::AndEqz(6074, 10537), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16641PolyExtStep::AndEqz(6075, 2218), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16642PolyExtStep::Mul(850, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16643PolyExtStep::Add(10538, 844), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16644PolyExtStep::Sub(573, 10539), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16645PolyExtStep::AndEqz(6076, 10540), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16646PolyExtStep::Add(10503, 6), // loc(callsite( builtin Add at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:33) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16647PolyExtStep::Sub(574, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16648PolyExtStep::AndEqz(6077, 10542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16649PolyExtStep::AndEqz(6078, 589), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16650PolyExtStep::Sub(588, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16651PolyExtStep::AndEqz(6079, 10543), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16652PolyExtStep::AndEqz(6080, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16653PolyExtStep::Sub(575, 10541), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16654PolyExtStep::AndEqz(6081, 10544), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16655PolyExtStep::AndEqz(6082, 3990), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16656PolyExtStep::Sub(578, 740), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16657PolyExtStep::AndEqz(6083, 10545), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16658PolyExtStep::Sub(3564, 576), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16659PolyExtStep::AndEqz(6084, 3347), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16660PolyExtStep::Sub(769, 10546), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16661PolyExtStep::AndEqz(6085, 10547), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16662PolyExtStep::AndEqz(6086, 2230), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16663PolyExtStep::AndEqz(6087, 7345), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16664PolyExtStep::Mul(893, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16665PolyExtStep::Add(10548, 856), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16666PolyExtStep::Sub(739, 10549), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16667PolyExtStep::AndEqz(6088, 10550), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16668PolyExtStep::Sub(896, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16669PolyExtStep::AndEqz(6089, 10551), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16670PolyExtStep::Sub(902, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16671PolyExtStep::AndEqz(6090, 10552), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16672PolyExtStep::Mul(905, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16673PolyExtStep::Add(10553, 899), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16674PolyExtStep::Sub(740, 10554), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16675PolyExtStep::AndEqz(6091, 10555), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16676PolyExtStep::AndCond(6015, 1011, 6092), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16677PolyExtStep::AndEqz(6032, 758), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16678PolyExtStep::AndEqz(6094, 782), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16679PolyExtStep::AndEqz(6095, 1758), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16680PolyExtStep::AndEqz(6096, 3020), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16681PolyExtStep::AndEqz(6097, 10521), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16682PolyExtStep::AndEqz(6098, 2216), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16683PolyExtStep::AndEqz(6099, 10525), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16684PolyExtStep::AndEqz(6100, 3144), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16685PolyExtStep::AndEqz(6101, 3893), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16686PolyExtStep::AndEqz(6102, 2223), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16687PolyExtStep::AndEqz(6103, 10537), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16688PolyExtStep::AndEqz(6104, 2218), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16689PolyExtStep::AndEqz(6105, 2230), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16690PolyExtStep::AndEqz(6106, 7345), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16691PolyExtStep::AndEqz(6107, 10551), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16692PolyExtStep::AndEqz(6108, 10552), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16693PolyExtStep::AndEqz(6109, 10504), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16694PolyExtStep::AndEqz(6110, 3958), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16695PolyExtStep::Sub(629, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16696PolyExtStep::AndEqz(6111, 10556), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16697PolyExtStep::AndEqz(6112, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16698PolyExtStep::AndEqz(6113, 10506), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16699PolyExtStep::AndEqz(6114, 754), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16700PolyExtStep::AndEqz(6115, 10509), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16701PolyExtStep::AndEqz(6116, 10511), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16702PolyExtStep::AndEqz(6117, 10514), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16703PolyExtStep::AndEqz(6118, 10516), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16704PolyExtStep::AndEqz(6119, 2346), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16705PolyExtStep::Sub(676, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16706PolyExtStep::AndEqz(6120, 10557), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16707PolyExtStep::AndEqz(6121, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16708PolyExtStep::AndEqz(6122, 10518), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16709PolyExtStep::AndEqz(6123, 1745), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16710PolyExtStep::AndEqz(6124, 10520), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16711PolyExtStep::AndEqz(6125, 10524), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16712PolyExtStep::AndEqz(6126, 10528), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16713PolyExtStep::AndEqz(6127, 10530), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16714PolyExtStep::AndEqz(6128, 1647), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16715PolyExtStep::Sub(570, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16716PolyExtStep::AndEqz(6129, 10558), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16717PolyExtStep::AndEqz(6130, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16718PolyExtStep::AndEqz(6131, 10531), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16719PolyExtStep::AndEqz(6132, 3339), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16720PolyExtStep::AndEqz(6133, 10534), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16721PolyExtStep::AndEqz(6134, 10536), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16722PolyExtStep::AndEqz(6135, 10540), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16723PolyExtStep::AndEqz(6136, 10542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16724PolyExtStep::AndEqz(6137, 589), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16725PolyExtStep::Sub(588, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16726PolyExtStep::AndEqz(6138, 10559), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16727PolyExtStep::AndEqz(6139, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16728PolyExtStep::AndEqz(6140, 10544), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16729PolyExtStep::AndEqz(6141, 3347), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16730PolyExtStep::AndEqz(6142, 10547), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16731PolyExtStep::AndEqz(6143, 10550), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16732PolyExtStep::AndEqz(6144, 10555), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16733PolyExtStep::AndCond(6093, 1014, 6145), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16734PolyExtStep::AndEqz(0, 758), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16735PolyExtStep::AndEqz(6147, 782), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16736PolyExtStep::AndEqz(6148, 1758), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16737PolyExtStep::AndEqz(6149, 3020), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16738PolyExtStep::AndEqz(6150, 10521), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16739PolyExtStep::AndEqz(6151, 2216), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16740PolyExtStep::AndEqz(6152, 10525), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16741PolyExtStep::AndEqz(6153, 3144), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16742PolyExtStep::AndEqz(6154, 3893), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16743PolyExtStep::AndEqz(6155, 2223), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16744PolyExtStep::AndEqz(6156, 10537), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16745PolyExtStep::AndEqz(6157, 2218), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16746PolyExtStep::AndEqz(6158, 2230), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16747PolyExtStep::AndEqz(6159, 7345), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16748PolyExtStep::AndEqz(6160, 10551), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16749PolyExtStep::AndEqz(6161, 10552), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16750PolyExtStep::AndEqz(6162, 920), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16751PolyExtStep::AndEqz(6163, 926), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16752PolyExtStep::AndEqz(6164, 591), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16753PolyExtStep::AndEqz(6165, 622), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16754PolyExtStep::AndEqz(6166, 646), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16755PolyExtStep::AndEqz(6167, 673), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16756PolyExtStep::AndEqz(6168, 552), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16757PolyExtStep::AndEqz(6169, 571), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16758PolyExtStep::AndEqz(6170, 574), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16759PolyExtStep::AndEqz(6171, 587), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16760PolyExtStep::AndEqz(6172, 745), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16761PolyExtStep::AndEqz(6173, 747), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16762PolyExtStep::AndEqz(6174, 766), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16763PolyExtStep::AndEqz(6175, 768), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16764PolyExtStep::AndCond(6146, 1017, 6176), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16765PolyExtStep::Mul(1771, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16766PolyExtStep::Mul(1771, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16767PolyExtStep::Mul(1771, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16768PolyExtStep::Add(10560, 10561), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16769PolyExtStep::Add(10563, 10562), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16770PolyExtStep::Mul(3793, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16771PolyExtStep::Mul(3793, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16772PolyExtStep::Mul(3793, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16773PolyExtStep::Add(10565, 10566), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16774PolyExtStep::Add(10568, 10567), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16775PolyExtStep::Mul(3794, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16776PolyExtStep::Mul(3794, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16777PolyExtStep::Mul(3794, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16778PolyExtStep::Add(10570, 10571), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16779PolyExtStep::Add(10573, 10572), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16780PolyExtStep::Mul(4348, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16781PolyExtStep::Mul(4348, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16782PolyExtStep::Mul(4348, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16783PolyExtStep::Add(10575, 10576), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16784PolyExtStep::Add(10578, 10577), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16785PolyExtStep::Mul(4340, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16786PolyExtStep::Mul(4340, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16787PolyExtStep::Mul(4340, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16788PolyExtStep::Add(10580, 10581), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16789PolyExtStep::Add(10583, 10582), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16790PolyExtStep::Mul(1182, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16791PolyExtStep::Mul(1182, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16792PolyExtStep::Mul(1182, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16793PolyExtStep::Add(10585, 10586), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16794PolyExtStep::Add(10588, 10587), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16795PolyExtStep::Mul(1184, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16796PolyExtStep::Mul(1184, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16797PolyExtStep::Mul(1184, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16798PolyExtStep::Add(10590, 10591), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16799PolyExtStep::Add(10593, 10592), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16800PolyExtStep::Mul(1186, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16801PolyExtStep::Mul(1186, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16802PolyExtStep::Mul(1186, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16803PolyExtStep::Add(10595, 10596), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16804PolyExtStep::Add(10598, 10597), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16805PolyExtStep::Mul(1188, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16806PolyExtStep::Mul(1188, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16807PolyExtStep::Mul(1188, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16808PolyExtStep::Add(10600, 10601), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16809PolyExtStep::Add(10603, 10602), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16810PolyExtStep::Mul(1190, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16811PolyExtStep::Mul(1190, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16812PolyExtStep::Mul(1190, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16813PolyExtStep::Add(10605, 10606), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16814PolyExtStep::Add(10608, 10607), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16815PolyExtStep::Mul(1192, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16816PolyExtStep::Mul(1192, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16817PolyExtStep::Mul(1192, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16818PolyExtStep::Add(10610, 10611), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16819PolyExtStep::Add(10613, 10612), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16820PolyExtStep::Mul(1194, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16821PolyExtStep::Mul(1194, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16822PolyExtStep::Mul(1194, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16823PolyExtStep::Add(10615, 10616), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16824PolyExtStep::Add(10618, 10617), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16825PolyExtStep::Mul(1196, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16826PolyExtStep::Mul(1196, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16827PolyExtStep::Mul(1196, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16828PolyExtStep::Add(10620, 10621), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16829PolyExtStep::Add(10623, 10622), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16830PolyExtStep::Mul(1198, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16831PolyExtStep::Mul(1198, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16832PolyExtStep::Mul(1198, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16833PolyExtStep::Add(10625, 10626), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16834PolyExtStep::Add(10628, 10627), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16835PolyExtStep::Mul(1200, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16836PolyExtStep::Mul(1200, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16837PolyExtStep::Mul(1200, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16838PolyExtStep::Add(10630, 10631), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16839PolyExtStep::Add(10633, 10632), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16840PolyExtStep::Mul(1202, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16841PolyExtStep::Mul(1202, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16842PolyExtStep::Mul(1202, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16843PolyExtStep::Add(10635, 10636), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16844PolyExtStep::Add(10638, 10637), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16845PolyExtStep::AndEqz(6177, 1071), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16846PolyExtStep::Mul(975, 1072), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16847PolyExtStep::Sub(10640, 1070), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16848PolyExtStep::AndEqz(6178, 10641), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16849PolyExtStep::Mul(1069, 975), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16850PolyExtStep::AndEqz(6179, 10642), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16851PolyExtStep::AndEqz(6180, 2729), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16852PolyExtStep::Mul(1069, 4740), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:27) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16853PolyExtStep::Sub(1, 10643), // loc(callsite( builtin Sub at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :152:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16854PolyExtStep::Mul(10643, 13), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :152:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16855PolyExtStep::Mul(10644, 318), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :152:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16856PolyExtStep::Add(10645, 10646), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :152:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16857PolyExtStep::AndEqz(6181, 10444), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16858PolyExtStep::AndEqz(6182, 3911), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16859PolyExtStep::AndEqz(6183, 10446), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16860PolyExtStep::AndEqz(6184, 4096), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16861PolyExtStep::AndEqz(6185, 9352), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :16:20) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16862PolyExtStep::Sub(975, 1143), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :17:24) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16863PolyExtStep::AndEqz(6186, 10648), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :17:24) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16864PolyExtStep::Sub(10464, 809), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :18:23) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16865PolyExtStep::AndEqz(6187, 10649), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :18:23) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16866PolyExtStep::Sub(10564, 1148), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16867PolyExtStep::AndEqz(6188, 10650), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16868PolyExtStep::Sub(10569, 810), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16869PolyExtStep::AndEqz(6189, 10651), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16870PolyExtStep::Sub(10574, 1154), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16871PolyExtStep::AndEqz(6190, 10652), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16872PolyExtStep::Sub(10579, 811), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16873PolyExtStep::AndEqz(6191, 10653), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16874PolyExtStep::Sub(10584, 1160), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16875PolyExtStep::AndEqz(6192, 10654), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16876PolyExtStep::Sub(10589, 1372), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16877PolyExtStep::AndEqz(6193, 10655), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16878PolyExtStep::Sub(10594, 1373), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16879PolyExtStep::AndEqz(6194, 10656), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16880PolyExtStep::Sub(10599, 1375), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16881PolyExtStep::AndEqz(6195, 10657), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16882PolyExtStep::Sub(10604, 1382), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16883PolyExtStep::AndEqz(6196, 10658), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16884PolyExtStep::Sub(10609, 1383), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16885PolyExtStep::AndEqz(6197, 10659), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16886PolyExtStep::Sub(10614, 1385), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16887PolyExtStep::AndEqz(6198, 10660), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16888PolyExtStep::Sub(10619, 1391), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16889PolyExtStep::AndEqz(6199, 10661), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16890PolyExtStep::Sub(10624, 1392), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16891PolyExtStep::AndEqz(6200, 10662), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16892PolyExtStep::Sub(10629, 1394), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16893PolyExtStep::AndEqz(6201, 10663), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16894PolyExtStep::Sub(10634, 1401), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16895PolyExtStep::AndEqz(6202, 10664), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16896PolyExtStep::Sub(10639, 1402), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16897PolyExtStep::AndEqz(6203, 10665), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16898PolyExtStep::Sub(10647, 1404), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16899PolyExtStep::AndEqz(6204, 10666), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16900PolyExtStep::AndCond(5977, 380, 6205), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16901PolyExtStep::AndEqz(1228, 10444), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16902PolyExtStep::AndEqz(6207, 3911), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16903PolyExtStep::AndEqz(6208, 10446), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16904PolyExtStep::AndEqz(6209, 3912), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16905PolyExtStep::AndEqz(6210, 4726), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :16:20) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16906PolyExtStep::AndEqz(6211, 4727), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :17:24) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16907PolyExtStep::AndEqz(6212, 4728), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :18:23) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16908PolyExtStep::AndEqz(6213, 4027), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16909PolyExtStep::AndEqz(6214, 4729), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16910PolyExtStep::AndEqz(6215, 3918), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16911PolyExtStep::AndEqz(6216, 3919), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16912PolyExtStep::AndEqz(6217, 3920), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16913PolyExtStep::AndEqz(6218, 4730), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16914PolyExtStep::AndEqz(6219, 3922), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16915PolyExtStep::AndEqz(6220, 3923), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16916PolyExtStep::AndEqz(6221, 3924), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16917PolyExtStep::AndEqz(6222, 3925), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16918PolyExtStep::AndEqz(6223, 3926), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16919PolyExtStep::AndEqz(6224, 3927), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16920PolyExtStep::AndEqz(6225, 3928), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16921PolyExtStep::AndEqz(6226, 3929), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16922PolyExtStep::AndEqz(6227, 3930), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16923PolyExtStep::AndEqz(6228, 3931), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16924PolyExtStep::Sub(13, 1404), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16925PolyExtStep::AndEqz(6229, 10667), // loc(callsite( Reg ( <preamble> :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
16926PolyExtStep::AndEqz(6230, 1410), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16927PolyExtStep::AndEqz(6231, 1428), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16928PolyExtStep::AndEqz(6232, 1430), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16929PolyExtStep::AndEqz(6233, 1900), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16930PolyExtStep::AndEqz(6234, 591), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16931PolyExtStep::AndEqz(6235, 622), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16932PolyExtStep::AndEqz(6236, 646), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16933PolyExtStep::AndEqz(6237, 673), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16934PolyExtStep::AndEqz(6238, 552), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16935PolyExtStep::AndEqz(6239, 571), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16936PolyExtStep::AndEqz(6240, 574), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16937PolyExtStep::AndEqz(6241, 587), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16938PolyExtStep::AndEqz(6242, 741), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16939PolyExtStep::AndEqz(6243, 743), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16940PolyExtStep::AndEqz(6244, 745), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16941PolyExtStep::AndEqz(6245, 747), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16942PolyExtStep::AndEqz(6246, 766), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16943PolyExtStep::AndEqz(6247, 768), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16944PolyExtStep::AndEqz(6248, 761), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16945PolyExtStep::AndEqz(6249, 771), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16946PolyExtStep::AndEqz(6250, 756), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16947PolyExtStep::AndEqz(6251, 762), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16948PolyExtStep::AndEqz(6252, 732), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16949PolyExtStep::AndEqz(6253, 764), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16950PolyExtStep::AndEqz(6254, 800), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16951PolyExtStep::AndEqz(6255, 804), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16952PolyExtStep::AndEqz(6256, 817), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16953PolyExtStep::AndEqz(6257, 823), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16954PolyExtStep::AndEqz(6258, 829), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16955PolyExtStep::AndEqz(6259, 835), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16956PolyExtStep::AndEqz(6260, 841), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16957PolyExtStep::AndEqz(6261, 847), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16958PolyExtStep::AndEqz(6262, 853), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16959PolyExtStep::AndEqz(6263, 859), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16960PolyExtStep::AndEqz(6264, 896), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16961PolyExtStep::AndEqz(6265, 902), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16962PolyExtStep::AndEqz(6266, 908), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16963PolyExtStep::AndEqz(6267, 914), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16964PolyExtStep::AndEqz(6268, 920), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16965PolyExtStep::AndEqz(6269, 926), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16966PolyExtStep::AndCond(6206, 383, 6270), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16967PolyExtStep::AndCond(6271, 386, 6270), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16968PolyExtStep::AndCond(6272, 389, 6270), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16969PolyExtStep::AndCond(6273, 392, 6270), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16970PolyExtStep::AndCond(6274, 395, 6270), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16971PolyExtStep::AndCond(6275, 398, 6270), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16972PolyExtStep::AndCond(5896, 458, 6276), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16973PolyExtStep::Mul(3810, 422), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16974PolyExtStep::Mul(3810, 425), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16975PolyExtStep::Mul(3810, 428), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16976PolyExtStep::Mul(1285, 431), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16977PolyExtStep::Get(780), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
16978PolyExtStep::Mul(10672, 434), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16979PolyExtStep::Mul(4348, 437), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16980PolyExtStep::Mul(1191, 440), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
16981PolyExtStep::Sub(1, 1298), // loc(callsite( builtin Sub at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16982PolyExtStep::Mul(2015, 1298), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16983PolyExtStep::Mul(368, 10676), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16984PolyExtStep::Add(10677, 10678), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16985PolyExtStep::Mul(10679, 380), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16986PolyExtStep::Get(221), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
16987PolyExtStep::Mul(10681, 383), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16988PolyExtStep::Mul(1771, 386), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16989PolyExtStep::Sub(1, 1301), // loc(callsite( builtin Sub at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16990PolyExtStep::Add(1300, 23), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :158:14) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
16991PolyExtStep::Mul(10685, 10676), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :160:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16992PolyExtStep::Mul(10686, 1301), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16993PolyExtStep::Mul(10686, 10684), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16994PolyExtStep::Add(10687, 10688), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
16995PolyExtStep::Mul(10689, 395), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16996PolyExtStep::Add(10680, 10682), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16997PolyExtStep::Add(10691, 10683), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16998PolyExtStep::Add(10692, 10690), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
16999PolyExtStep::Mul(10693, 443), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17000PolyExtStep::Mul(1188, 446), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17001PolyExtStep::Mul(368, 449), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17002PolyExtStep::Mul(368, 452), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17003PolyExtStep::Mul(368, 455), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17004PolyExtStep::Mul(368, 458), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17005PolyExtStep::Add(10668, 10669), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17006PolyExtStep::Add(10700, 10670), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17007PolyExtStep::Add(10701, 10671), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17008PolyExtStep::Add(10702, 10673), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17009PolyExtStep::Add(10703, 10674), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17010PolyExtStep::Add(10704, 10675), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17011PolyExtStep::Add(10705, 10694), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17012PolyExtStep::Add(10706, 10695), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17013PolyExtStep::Add(10707, 10696), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17014PolyExtStep::Add(10708, 10697), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17015PolyExtStep::Add(10709, 10698), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17016PolyExtStep::Add(10710, 10699), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17017PolyExtStep::Get(245), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
17018PolyExtStep::Mul(10712, 422), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17019PolyExtStep::Mul(10712, 425), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17020PolyExtStep::Mul(10712, 428), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17021PolyExtStep::Mul(1288, 431), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17022PolyExtStep::Get(783), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
17023PolyExtStep::Mul(10717, 434), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17024PolyExtStep::Get(706), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))
17025PolyExtStep::Mul(10719, 437), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17026PolyExtStep::Mul(1194, 440), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17027PolyExtStep::Get(173), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))
17028PolyExtStep::Mul(10722, 1298), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17029PolyExtStep::Mul(370, 10676), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17030PolyExtStep::Add(10723, 10724), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17031PolyExtStep::Mul(10725, 380), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17032PolyExtStep::Mul(3810, 383), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17033PolyExtStep::Mul(3793, 386), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17034PolyExtStep::Add(10726, 10727), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17035PolyExtStep::Add(10729, 10728), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17036PolyExtStep::Mul(10730, 443), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17037PolyExtStep::Mul(1191, 446), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17038PolyExtStep::Mul(370, 449), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17039PolyExtStep::Mul(370, 452), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17040PolyExtStep::Mul(370, 455), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17041PolyExtStep::Mul(370, 458), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17042PolyExtStep::Add(10713, 10714), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17043PolyExtStep::Add(10737, 10715), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17044PolyExtStep::Add(10738, 10716), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17045PolyExtStep::Add(10739, 10718), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17046PolyExtStep::Add(10740, 10720), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17047PolyExtStep::Add(10741, 10721), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17048PolyExtStep::Add(10742, 10731), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17049PolyExtStep::Add(10743, 10732), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17050PolyExtStep::Add(10744, 10733), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17051PolyExtStep::Add(10745, 10734), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17052PolyExtStep::Add(10746, 10735), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17053PolyExtStep::Add(10747, 10736), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17054PolyExtStep::Mul(422, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17055PolyExtStep::Mul(425, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17056PolyExtStep::Mul(428, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17057PolyExtStep::Mul(431, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17058PolyExtStep::Mul(434, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17059PolyExtStep::Mul(437, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17060PolyExtStep::Mul(440, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17061PolyExtStep::Get(120), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :49:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17062PolyExtStep::Sub(1, 10756), // loc(callsite( builtin Sub at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :32:8) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
17063PolyExtStep::Sub(1, 10757), // loc(callsite( builtin Sub at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :32:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
17064PolyExtStep::Mul(10758, 23), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :32:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17065PolyExtStep::Mul(10759, 377), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17066PolyExtStep::Mul(10676, 13), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17067PolyExtStep::Add(1298, 10761), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17068PolyExtStep::Mul(10762, 380), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17069PolyExtStep::Mul(383, 13), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17070PolyExtStep::Sub(1, 1299), // loc(callsite( builtin Sub at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))
17071PolyExtStep::Mul(1299, 23), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17072PolyExtStep::Mul(10765, 5), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17073PolyExtStep::Add(10766, 10767), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17074PolyExtStep::Mul(10768, 389), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17075PolyExtStep::Mul(392, 3), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17076PolyExtStep::Mul(1298, 2), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :160:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17077PolyExtStep::Mul(10676, 3), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :160:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17078PolyExtStep::Add(10771, 10772), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :160:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17079PolyExtStep::Mul(10773, 1301), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17080PolyExtStep::Mul(1298, 3), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17081PolyExtStep::Add(10775, 10772), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17082PolyExtStep::Mul(10776, 10684), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17083PolyExtStep::Add(10774, 10777), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17084PolyExtStep::Mul(10778, 395), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17085PolyExtStep::Add(10760, 10763), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17086PolyExtStep::Add(10780, 10764), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17087PolyExtStep::Add(10781, 3554), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17088PolyExtStep::Add(10782, 10769), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17089PolyExtStep::Add(10783, 10770), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17090PolyExtStep::Add(10784, 10779), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17091PolyExtStep::Add(10785, 414), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17092PolyExtStep::Mul(10786, 443), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17093PolyExtStep::Mul(3809, 446), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17094PolyExtStep::Get(166), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
17095PolyExtStep::Mul(10789, 449), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17096PolyExtStep::Mul(10789, 452), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17097PolyExtStep::Mul(10789, 455), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17098PolyExtStep::Get(251), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
17099PolyExtStep::Mul(10793, 458), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17100PolyExtStep::Add(10749, 10750), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17101PolyExtStep::Add(10795, 10751), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17102PolyExtStep::Add(10796, 10752), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17103PolyExtStep::Add(10797, 10753), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17104PolyExtStep::Add(10798, 10754), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17105PolyExtStep::Add(10799, 10755), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17106PolyExtStep::Add(10800, 10787), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17107PolyExtStep::Add(10801, 10788), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17108PolyExtStep::Add(10802, 10790), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17109PolyExtStep::Add(10803, 10791), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17110PolyExtStep::Add(10804, 10792), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17111PolyExtStep::Add(10805, 10794), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17112PolyExtStep::Mul(374, 422), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17113PolyExtStep::Mul(374, 425), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17114PolyExtStep::Mul(374, 428), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17115PolyExtStep::Mul(374, 431), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17116PolyExtStep::Mul(374, 434), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17117PolyExtStep::Mul(374, 437), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17118PolyExtStep::Mul(374, 440), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17119PolyExtStep::Mul(10681, 1298), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17120PolyExtStep::Mul(374, 10676), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17121PolyExtStep::Add(10814, 10815), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17122PolyExtStep::Mul(10816, 380), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17123PolyExtStep::Mul(1299, 6), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17124PolyExtStep::Mul(374, 10765), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17125PolyExtStep::Add(10818, 10819), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17126PolyExtStep::Mul(10820, 389), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17127PolyExtStep::Mul(10676, 1301), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17128PolyExtStep::Mul(1298, 10684), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17129PolyExtStep::Add(10822, 10823), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17130PolyExtStep::Mul(10824, 395), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17131PolyExtStep::Add(10817, 383), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17132PolyExtStep::Add(10826, 10821), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17133PolyExtStep::Add(10827, 10825), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17134PolyExtStep::Add(10828, 398), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17135PolyExtStep::Mul(10829, 443), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17136PolyExtStep::Get(185), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))
17137PolyExtStep::Mul(10831, 449), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17138PolyExtStep::Mul(10831, 452), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17139PolyExtStep::Mul(374, 455), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17140PolyExtStep::Mul(374, 458), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17141PolyExtStep::Add(10807, 10808), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17142PolyExtStep::Add(10836, 10809), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17143PolyExtStep::Add(10837, 10810), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17144PolyExtStep::Add(10838, 10811), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17145PolyExtStep::Add(10839, 10812), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17146PolyExtStep::Add(10840, 10813), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17147PolyExtStep::Add(10841, 10830), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17148PolyExtStep::Add(10842, 446), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17149PolyExtStep::Add(10843, 10832), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17150PolyExtStep::Add(10844, 10833), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17151PolyExtStep::Add(10845, 10834), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17152PolyExtStep::Add(10846, 10835), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))
17153PolyExtStep::Get(135), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :91:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17154PolyExtStep::Sub(10711, 10848), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :91:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17155PolyExtStep::AndEqz(6277, 10849), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :91:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17156PolyExtStep::Get(137), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :92:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17157PolyExtStep::Sub(10748, 10850), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :92:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17158PolyExtStep::AndEqz(6278, 10851), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :92:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17159PolyExtStep::Get(139), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :93:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17160PolyExtStep::Sub(10806, 10852), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :93:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17161PolyExtStep::AndEqz(6279, 10853), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :93:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17162PolyExtStep::Get(141), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :94:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))
17163PolyExtStep::Sub(10847, 10854), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :94:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17164PolyExtStep::AndEqz(6280, 10855), // loc(callsite( Reg ( <preamble> :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :94:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))
17165PolyExtStep::GetGlobal(1, 35), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17166PolyExtStep::GetGlobal(1, 34), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17167PolyExtStep::Mul(10856, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17168PolyExtStep::Add(10857, 10858), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17169PolyExtStep::GetGlobal(1, 33), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17170PolyExtStep::Mul(10859, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17171PolyExtStep::Add(10860, 10861), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17172PolyExtStep::GetGlobal(1, 32), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17173PolyExtStep::Mul(10862, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17174PolyExtStep::Add(10863, 10864), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17175PolyExtStep::Mul(2013, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))
17176PolyExtStep::Get(162), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :18:23) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17177PolyExtStep::Mul(10867, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))
17178PolyExtStep::Mul(2010, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))
17179PolyExtStep::Mul(10789, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))
17180PolyExtStep::Mul(2015, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))
17181PolyExtStep::Mul(10722, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))
17182PolyExtStep::Mul(2027, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))
17183PolyExtStep::Mul(10831, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))
17184PolyExtStep::Get(191), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17185PolyExtStep::Mul(10875, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))
17186PolyExtStep::Get(197), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17187PolyExtStep::Mul(10877, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))
17188PolyExtStep::Get(203), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17189PolyExtStep::Mul(10879, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))
17190PolyExtStep::Get(209), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17191PolyExtStep::Mul(10881, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))
17192PolyExtStep::Get(215), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17193PolyExtStep::Mul(10883, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))
17194PolyExtStep::Mul(10681, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))
17195PolyExtStep::Mul(3810, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))
17196PolyExtStep::Get(233), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17197PolyExtStep::Mul(10887, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))
17198PolyExtStep::Get(239), // loc(callsite( builtin NondetReg at callsite( Reg ( <preamble> :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17199PolyExtStep::Mul(10889, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))
17200PolyExtStep::Mul(10712, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))
17201PolyExtStep::Get(24), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17202PolyExtStep::Sub(1, 10892), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17203PolyExtStep::Mul(10892, 10893), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17204PolyExtStep::AndEqz(6281, 10894), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17205PolyExtStep::Get(25), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17206PolyExtStep::Sub(1, 10895), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17207PolyExtStep::Mul(10895, 10896), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17208PolyExtStep::AndEqz(6282, 10897), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17209PolyExtStep::Get(26), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17210PolyExtStep::Sub(1, 10898), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17211PolyExtStep::Mul(10898, 10899), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17212PolyExtStep::AndEqz(6283, 10900), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17213PolyExtStep::Get(27), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17214PolyExtStep::Sub(1, 10901), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17215PolyExtStep::Mul(10901, 10902), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17216PolyExtStep::AndEqz(6284, 10903), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17217PolyExtStep::Get(28), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17218PolyExtStep::Sub(1, 10904), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17219PolyExtStep::Mul(10904, 10905), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17220PolyExtStep::AndEqz(6285, 10906), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17221PolyExtStep::Get(29), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17222PolyExtStep::Sub(1, 10907), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17223PolyExtStep::Mul(10907, 10908), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17224PolyExtStep::AndEqz(6286, 10909), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17225PolyExtStep::Get(30), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17226PolyExtStep::Sub(1, 10910), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17227PolyExtStep::Mul(10910, 10911), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17228PolyExtStep::AndEqz(6287, 10912), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17229PolyExtStep::Add(10892, 10895), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17230PolyExtStep::Add(10913, 10898), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17231PolyExtStep::Add(10914, 10901), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17232PolyExtStep::Add(10915, 10904), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17233PolyExtStep::Add(10916, 10907), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17234PolyExtStep::Add(10917, 10910), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17235PolyExtStep::Sub(10918, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))
17236PolyExtStep::AndEqz(6288, 10919), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))
17237PolyExtStep::Mul(10898, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17238PolyExtStep::Mul(10901, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17239PolyExtStep::Mul(10904, 5), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17240PolyExtStep::Mul(10907, 4), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17241PolyExtStep::Mul(10910, 3), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17242PolyExtStep::Add(10895, 10920), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17243PolyExtStep::Add(10925, 10921), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17244PolyExtStep::Add(10926, 10922), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17245PolyExtStep::Add(10927, 10923), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17246PolyExtStep::Add(10928, 10924), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17247PolyExtStep::Sub(10929, 10866), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))
17248PolyExtStep::AndEqz(6289, 10930), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))
17249PolyExtStep::Get(6), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17250PolyExtStep::Get(4), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17251PolyExtStep::Mul(10931, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17252PolyExtStep::Add(10932, 10933), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17253PolyExtStep::Get(2), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17254PolyExtStep::Mul(10934, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17255PolyExtStep::Add(10935, 10936), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17256PolyExtStep::Get(0), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17257PolyExtStep::Mul(10937, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17258PolyExtStep::Add(10938, 10939), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17259PolyExtStep::Sub(10940, 58), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17260PolyExtStep::AndEqz(0, 10941), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17261PolyExtStep::Get(14), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17262PolyExtStep::Get(12), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17263PolyExtStep::Mul(10942, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17264PolyExtStep::Add(10943, 10944), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17265PolyExtStep::Get(10), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17266PolyExtStep::Mul(10945, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17267PolyExtStep::Add(10946, 10947), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17268PolyExtStep::Get(8), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17269PolyExtStep::Mul(10948, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17270PolyExtStep::Add(10949, 10950), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17271PolyExtStep::Sub(10951, 67), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17272PolyExtStep::AndEqz(6291, 10952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17273PolyExtStep::Get(22), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17274PolyExtStep::Get(20), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17275PolyExtStep::Mul(10953, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17276PolyExtStep::Add(10954, 10955), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17277PolyExtStep::Get(18), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17278PolyExtStep::Mul(10956, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17279PolyExtStep::Add(10957, 10958), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17280PolyExtStep::Get(16), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17281PolyExtStep::Mul(10959, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17282PolyExtStep::Add(10960, 10961), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17283PolyExtStep::Sub(10962, 58), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17284PolyExtStep::AndEqz(6292, 10963), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17285PolyExtStep::AndCond(6290, 10892, 6293), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))
17286PolyExtStep::Mul(10865, 67), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :210:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17287PolyExtStep::Mul(10964, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :211:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17288PolyExtStep::Mul(10965, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :212:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17289PolyExtStep::Mul(10966, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :213:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17290PolyExtStep::Mul(10967, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :214:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17291PolyExtStep::Mul(10968, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :215:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17292PolyExtStep::Mul(10969, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :216:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17293PolyExtStep::Mul(10970, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :217:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17294PolyExtStep::Mul(10971, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :218:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17295PolyExtStep::Mul(10972, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :219:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17296PolyExtStep::Mul(10973, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :220:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17297PolyExtStep::Mul(10974, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :221:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17298PolyExtStep::Mul(10975, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :222:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17299PolyExtStep::Mul(10976, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :223:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17300PolyExtStep::Mul(10977, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :224:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17301PolyExtStep::Mul(10978, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :225:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17302PolyExtStep::Add(10869, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17303PolyExtStep::Mul(10980, 67), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17304PolyExtStep::Add(10870, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17305PolyExtStep::Mul(10964, 10982), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17306PolyExtStep::Add(10871, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17307PolyExtStep::Mul(10965, 10984), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17308PolyExtStep::Add(10872, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17309PolyExtStep::Mul(10966, 10986), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17310PolyExtStep::Add(10873, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17311PolyExtStep::Mul(10967, 10988), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17312PolyExtStep::Add(10874, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17313PolyExtStep::Mul(10968, 10990), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17314PolyExtStep::Add(10876, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17315PolyExtStep::Mul(10969, 10992), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17316PolyExtStep::Add(10878, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17317PolyExtStep::Mul(10970, 10994), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17318PolyExtStep::Add(10880, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17319PolyExtStep::Mul(10971, 10996), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17320PolyExtStep::Add(10882, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17321PolyExtStep::Mul(10972, 10998), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17322PolyExtStep::Add(10884, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17323PolyExtStep::Mul(10973, 11000), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17324PolyExtStep::Add(10885, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17325PolyExtStep::Mul(10974, 11002), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17326PolyExtStep::Add(10886, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17327PolyExtStep::Mul(10975, 11004), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17328PolyExtStep::Add(10888, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17329PolyExtStep::Mul(10976, 11006), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17330PolyExtStep::Add(10890, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17331PolyExtStep::Mul(10977, 11008), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17332PolyExtStep::Add(10891, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17333PolyExtStep::Mul(10978, 11010), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17334PolyExtStep::Add(10981, 58), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17335PolyExtStep::Add(11012, 10983), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17336PolyExtStep::Add(11013, 10985), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17337PolyExtStep::Add(11014, 10987), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17338PolyExtStep::Add(11015, 10989), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17339PolyExtStep::Add(11016, 10991), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17340PolyExtStep::Add(11017, 10993), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17341PolyExtStep::Add(11018, 10995), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17342PolyExtStep::Add(11019, 10997), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17343PolyExtStep::Add(11020, 10999), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17344PolyExtStep::Add(11021, 11001), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17345PolyExtStep::Add(11022, 11003), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17346PolyExtStep::Add(11023, 11005), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17347PolyExtStep::Add(11024, 11007), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17348PolyExtStep::Add(11025, 11009), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17349PolyExtStep::Add(11026, 11011), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17350PolyExtStep::Get(7), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17351PolyExtStep::Get(5), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17352PolyExtStep::Mul(11028, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17353PolyExtStep::Add(11029, 11030), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17354PolyExtStep::Get(3), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17355PolyExtStep::Mul(11031, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17356PolyExtStep::Add(11032, 11033), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17357PolyExtStep::Get(1), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17358PolyExtStep::Mul(11034, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17359PolyExtStep::Add(11035, 11036), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17360PolyExtStep::Get(15), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17361PolyExtStep::Get(13), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17362PolyExtStep::Mul(11038, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17363PolyExtStep::Add(11039, 11040), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17364PolyExtStep::Get(11), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17365PolyExtStep::Mul(11041, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17366PolyExtStep::Add(11042, 11043), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17367PolyExtStep::Get(9), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17368PolyExtStep::Mul(11044, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17369PolyExtStep::Add(11045, 11046), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17370PolyExtStep::Get(23), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17371PolyExtStep::Get(21), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17372PolyExtStep::Mul(11048, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17373PolyExtStep::Add(11049, 11050), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17374PolyExtStep::Get(19), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17375PolyExtStep::Mul(11051, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17376PolyExtStep::Add(11052, 11053), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17377PolyExtStep::Get(17), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17378PolyExtStep::Mul(11054, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17379PolyExtStep::Add(11055, 11056), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17380PolyExtStep::Add(11037, 11027), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :246:28) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17381PolyExtStep::Mul(11058, 10979), // loc(callsite( builtin ExtMul at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :262:21) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17382PolyExtStep::Sub(10940, 11059), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :261:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17383PolyExtStep::AndEqz(0, 11060), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :261:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17384PolyExtStep::Sub(10951, 11047), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :261:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17385PolyExtStep::AndEqz(6295, 11061), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :261:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17386PolyExtStep::Sub(10962, 11057), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :261:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17387PolyExtStep::AndEqz(6296, 11062), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :261:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17388PolyExtStep::AndCond(6294, 10895, 6297), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))
17389PolyExtStep::Sub(10951, 11058), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpSetTerm ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :271:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :200:25) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17390PolyExtStep::AndEqz(6291, 11063), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpSetTerm ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :271:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :200:25) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17391PolyExtStep::AndEqz(6299, 11062), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpSetTerm ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :271:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :200:25) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17392PolyExtStep::AndCond(6298, 10898, 6300), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))
17393PolyExtStep::Sub(10868, 5), // loc(callsite( builtin Sub at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :280:30) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17394PolyExtStep::Add(11064, 58), // loc(callsite( builtin MakeExt at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :280:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17395PolyExtStep::Mul(11065, 11047), // loc(callsite( builtin ExtMul at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:24) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17396PolyExtStep::Get(34), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17397PolyExtStep::Get(33), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17398PolyExtStep::Mul(11067, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17399PolyExtStep::Add(11068, 11069), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17400PolyExtStep::Get(32), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17401PolyExtStep::Mul(11070, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17402PolyExtStep::Add(11071, 11072), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17403PolyExtStep::Get(31), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17404PolyExtStep::Mul(11073, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17405PolyExtStep::Add(11074, 11075), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( <preamble> :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17406PolyExtStep::Sub(11076, 11066), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17407PolyExtStep::AndEqz(0, 11077), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17408PolyExtStep::Mul(11076, 11058), // loc(callsite( builtin ExtMul at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :286:41) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17409PolyExtStep::Add(11057, 11078), // loc(callsite( builtin ExtAdd at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :286:22) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17410PolyExtStep::AndEqz(6302, 10941), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :283:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17411PolyExtStep::AndEqz(6303, 10952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :283:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17412PolyExtStep::Sub(10962, 11079), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :283:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17413PolyExtStep::AndEqz(6304, 11080), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :283:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17414PolyExtStep::AndCond(6301, 10901, 6305), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))
17415PolyExtStep::Mul(10964, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17416PolyExtStep::Mul(10965, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17417PolyExtStep::Mul(10966, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17418PolyExtStep::Mul(10967, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17419PolyExtStep::Mul(10968, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17420PolyExtStep::Mul(10969, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17421PolyExtStep::Mul(10970, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17422PolyExtStep::Mul(10971, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17423PolyExtStep::Mul(10972, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17424PolyExtStep::Mul(10973, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17425PolyExtStep::Mul(10974, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17426PolyExtStep::Mul(10975, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17427PolyExtStep::Mul(10976, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17428PolyExtStep::Mul(10977, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17429PolyExtStep::Mul(10978, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17430PolyExtStep::Add(11081, 319), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17431PolyExtStep::Add(11096, 11082), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17432PolyExtStep::Add(11097, 11083), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17433PolyExtStep::Add(11098, 11084), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17434PolyExtStep::Add(11099, 11085), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17435PolyExtStep::Add(11100, 11086), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17436PolyExtStep::Add(11101, 11087), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17437PolyExtStep::Add(11102, 11088), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17438PolyExtStep::Add(11103, 11089), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17439PolyExtStep::Add(11104, 11090), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17440PolyExtStep::Add(11105, 11091), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17441PolyExtStep::Add(11106, 11092), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17442PolyExtStep::Add(11107, 11093), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17443PolyExtStep::Add(11108, 11094), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17444PolyExtStep::Add(11109, 11095), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))
17445PolyExtStep::Sub(11027, 11110), // loc(callsite( builtin ExtSub at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :294:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17446PolyExtStep::Mul(11111, 320), // loc(callsite( builtin ExtMul at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :294:39) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17447PolyExtStep::Add(11037, 11112), // loc(callsite( builtin ExtAdd at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :294:21) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17448PolyExtStep::Sub(10940, 11113), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :293:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17449PolyExtStep::AndEqz(0, 11114), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :293:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17450PolyExtStep::AndEqz(6307, 11061), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :293:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17451PolyExtStep::AndEqz(6308, 11062), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :293:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17452PolyExtStep::AndCond(6306, 10904, 6309), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))
17453PolyExtStep::Mul(11027, 321), // loc(callsite( builtin ExtMul at callsite( BigIntPolyOpCarry2 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :304:39) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :203:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17454PolyExtStep::Add(11037, 11115), // loc(callsite( builtin ExtAdd at callsite( BigIntPolyOpCarry2 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :304:21) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :203:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17455PolyExtStep::Sub(10940, 11116), // loc(callsite( builtin ExtSub at callsite( ExtReg ( <preamble> :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpCarry2 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :303:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :203:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17456PolyExtStep::AndEqz(0, 11117), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpCarry2 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :303:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :203:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17457PolyExtStep::AndEqz(6311, 11061), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpCarry2 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :303:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :203:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17458PolyExtStep::AndEqz(6312, 11062), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpCarry2 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :303:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :203:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17459PolyExtStep::AndCond(6310, 10907, 6313), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))
17460PolyExtStep::Sub(10964, 321), // loc(callsite( builtin ExtSub at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :313:22) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17461PolyExtStep::Mul(11058, 11118), // loc(callsite( builtin ExtMul at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :314:41) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17462PolyExtStep::Add(11057, 11119), // loc(callsite( builtin ExtAdd at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :314:22) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17463PolyExtStep::AndEqz(0, 11120), // loc(callsite( builtin EqzExt at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :315:10) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))
17464PolyExtStep::AndEqz(6315, 10941), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :316:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17465PolyExtStep::AndEqz(6316, 10952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :316:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17466PolyExtStep::AndEqz(6317, 10963), // loc(callsite( builtin EqzExt at callsite( ExtReg ( <preamble> :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :316:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))))
17467PolyExtStep::AndCond(6314, 10910, 6318), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))
17468PolyExtStep::GetGlobal(1, 7), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17469PolyExtStep::GetGlobal(1, 6), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17470PolyExtStep::Mul(11121, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17471PolyExtStep::Add(11122, 11123), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17472PolyExtStep::GetGlobal(1, 5), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17473PolyExtStep::Mul(11124, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17474PolyExtStep::Add(11125, 11126), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17475PolyExtStep::GetGlobal(1, 4), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17476PolyExtStep::Mul(11127, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17477PolyExtStep::Add(11128, 11129), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17478PolyExtStep::GetGlobal(1, 11), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17479PolyExtStep::GetGlobal(1, 10), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17480PolyExtStep::Mul(11131, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17481PolyExtStep::Add(11132, 11133), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17482PolyExtStep::GetGlobal(1, 9), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17483PolyExtStep::Mul(11134, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17484PolyExtStep::Add(11135, 11136), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17485PolyExtStep::GetGlobal(1, 8), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17486PolyExtStep::Mul(11137, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17487PolyExtStep::Add(11138, 11139), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17488PolyExtStep::GetGlobal(1, 15), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17489PolyExtStep::GetGlobal(1, 14), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17490PolyExtStep::Mul(11141, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17491PolyExtStep::Add(11142, 11143), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17492PolyExtStep::GetGlobal(1, 13), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17493PolyExtStep::Mul(11144, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17494PolyExtStep::Add(11145, 11146), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17495PolyExtStep::GetGlobal(1, 12), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17496PolyExtStep::Mul(11147, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17497PolyExtStep::Add(11148, 11149), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17498PolyExtStep::GetGlobal(1, 19), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17499PolyExtStep::GetGlobal(1, 18), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17500PolyExtStep::Mul(11151, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17501PolyExtStep::Add(11152, 11153), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17502PolyExtStep::GetGlobal(1, 17), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17503PolyExtStep::Mul(11154, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17504PolyExtStep::Add(11155, 11156), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17505PolyExtStep::GetGlobal(1, 16), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17506PolyExtStep::Mul(11157, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17507PolyExtStep::Add(11158, 11159), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17508PolyExtStep::GetGlobal(1, 23), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17509PolyExtStep::GetGlobal(1, 22), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17510PolyExtStep::Mul(11161, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17511PolyExtStep::Add(11162, 11163), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17512PolyExtStep::GetGlobal(1, 21), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17513PolyExtStep::Mul(11164, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17514PolyExtStep::Add(11165, 11166), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17515PolyExtStep::GetGlobal(1, 20), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17516PolyExtStep::Mul(11167, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17517PolyExtStep::Add(11168, 11169), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17518PolyExtStep::GetGlobal(1, 27), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17519PolyExtStep::GetGlobal(1, 26), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17520PolyExtStep::Mul(11171, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17521PolyExtStep::Add(11172, 11173), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17522PolyExtStep::GetGlobal(1, 25), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17523PolyExtStep::Mul(11174, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17524PolyExtStep::Add(11175, 11176), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17525PolyExtStep::GetGlobal(1, 24), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17526PolyExtStep::Mul(11177, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17527PolyExtStep::Add(11178, 11179), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17528PolyExtStep::GetGlobal(1, 31), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17529PolyExtStep::GetGlobal(1, 30), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17530PolyExtStep::Mul(11181, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17531PolyExtStep::Add(11182, 11183), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17532PolyExtStep::GetGlobal(1, 29), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17533PolyExtStep::Mul(11184, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17534PolyExtStep::Add(11185, 11186), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17535PolyExtStep::GetGlobal(1, 28), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17536PolyExtStep::Mul(11187, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17537PolyExtStep::Add(11188, 11189), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17538PolyExtStep::Get(118), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17539PolyExtStep::Get(116), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17540PolyExtStep::Mul(11191, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17541PolyExtStep::Add(11192, 11193), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17542PolyExtStep::Get(114), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17543PolyExtStep::Mul(11194, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17544PolyExtStep::Add(11195, 11196), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17545PolyExtStep::Get(112), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17546PolyExtStep::Mul(11197, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17547PolyExtStep::Add(11198, 11199), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17548PolyExtStep::Mul(11130, 1373), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17549PolyExtStep::Add(11201, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17550PolyExtStep::Mul(11130, 1383), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17551PolyExtStep::Add(11203, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17552PolyExtStep::Mul(11202, 11204), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17553PolyExtStep::Mul(11202, 1382), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17554PolyExtStep::Mul(1372, 11204), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17555PolyExtStep::Mul(11130, 1392), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17556PolyExtStep::Add(11208, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17557PolyExtStep::Mul(11205, 11209), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17558PolyExtStep::Mul(11205, 1391), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17559PolyExtStep::Mul(11207, 11209), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17560PolyExtStep::Mul(11206, 11209), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17561PolyExtStep::Get(38), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17562PolyExtStep::Get(37), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17563PolyExtStep::Mul(11214, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17564PolyExtStep::Add(11215, 11216), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17565PolyExtStep::Get(36), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17566PolyExtStep::Mul(11217, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17567PolyExtStep::Add(11218, 11219), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17568PolyExtStep::Get(35), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17569PolyExtStep::Mul(11220, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17570PolyExtStep::Add(11221, 11222), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17571PolyExtStep::Sub(11223, 11200), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17572PolyExtStep::Mul(11224, 11210), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17573PolyExtStep::Sub(11225, 11212), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17574PolyExtStep::Sub(11226, 11213), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17575PolyExtStep::Sub(11227, 11211), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17576PolyExtStep::AndEqz(0, 11228), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17577PolyExtStep::Mul(11130, 1402), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17578PolyExtStep::Add(11229, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17579PolyExtStep::Mul(11140, 1427), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17580PolyExtStep::Mul(11150, 1428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17581PolyExtStep::Add(11231, 11232), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17582PolyExtStep::Mul(11160, 1829), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17583PolyExtStep::Add(11233, 11234), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17584PolyExtStep::Mul(11170, 1830), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17585PolyExtStep::Add(11235, 11236), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17586PolyExtStep::Add(11237, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17587PolyExtStep::Mul(11230, 11238), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17588PolyExtStep::Mul(11230, 1426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17589PolyExtStep::Mul(1401, 11238), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17590PolyExtStep::Mul(11150, 1430), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17591PolyExtStep::Add(11231, 11242), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17592PolyExtStep::Mul(11160, 1431), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17593PolyExtStep::Add(11243, 11244), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17594PolyExtStep::Mul(11170, 1432), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17595PolyExtStep::Add(11245, 11246), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17596PolyExtStep::Add(11247, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17597PolyExtStep::Mul(11239, 11248), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17598PolyExtStep::Mul(11239, 1429), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17599PolyExtStep::Mul(11241, 11248), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17600PolyExtStep::Mul(11240, 11248), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17601PolyExtStep::Get(42), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17602PolyExtStep::Get(41), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17603PolyExtStep::Mul(11253, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17604PolyExtStep::Add(11254, 11255), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17605PolyExtStep::Get(40), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17606PolyExtStep::Mul(11256, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17607PolyExtStep::Add(11257, 11258), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17608PolyExtStep::Get(39), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17609PolyExtStep::Mul(11259, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17610PolyExtStep::Add(11260, 11261), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17611PolyExtStep::Sub(11262, 11223), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17612PolyExtStep::Mul(11263, 11249), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17613PolyExtStep::Sub(11264, 11251), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17614PolyExtStep::Sub(11265, 11252), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17615PolyExtStep::Sub(11266, 11250), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17616PolyExtStep::AndEqz(6320, 11267), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17617PolyExtStep::Mul(11180, 1440), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17618PolyExtStep::Add(11268, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17619PolyExtStep::Mul(11180, 538), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17620PolyExtStep::Add(11270, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17621PolyExtStep::Mul(11269, 11271), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17622PolyExtStep::Mul(11269, 1900), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17623PolyExtStep::Mul(1439, 11271), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17624PolyExtStep::Mul(11180, 539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17625PolyExtStep::Add(11275, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17626PolyExtStep::Mul(11272, 11276), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17627PolyExtStep::Mul(11272, 2278), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17628PolyExtStep::Mul(11274, 11276), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17629PolyExtStep::Mul(11273, 11276), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17630PolyExtStep::Get(46), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17631PolyExtStep::Get(45), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17632PolyExtStep::Mul(11281, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17633PolyExtStep::Add(11282, 11283), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17634PolyExtStep::Get(44), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17635PolyExtStep::Mul(11284, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17636PolyExtStep::Add(11285, 11286), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17637PolyExtStep::Get(43), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17638PolyExtStep::Mul(11287, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17639PolyExtStep::Add(11288, 11289), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17640PolyExtStep::Sub(11290, 11262), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17641PolyExtStep::Mul(11291, 11277), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17642PolyExtStep::Sub(11292, 11279), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17643PolyExtStep::Sub(11293, 11280), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17644PolyExtStep::Sub(11294, 11278), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17645PolyExtStep::AndEqz(6321, 11295), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17646PolyExtStep::Mul(11130, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17647PolyExtStep::Add(11296, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17648PolyExtStep::Mul(11130, 564), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17649PolyExtStep::Add(11298, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17650PolyExtStep::Mul(11297, 11299), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17651PolyExtStep::Mul(11297, 563), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17652PolyExtStep::Mul(551, 11299), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17653PolyExtStep::Mul(11140, 571), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17654PolyExtStep::Mul(11150, 572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17655PolyExtStep::Add(11303, 11304), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17656PolyExtStep::Mul(11160, 573), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17657PolyExtStep::Add(11305, 11306), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17658PolyExtStep::Mul(11170, 574), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17659PolyExtStep::Add(11307, 11308), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17660PolyExtStep::Add(11309, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17661PolyExtStep::Mul(11300, 11310), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17662PolyExtStep::Mul(11300, 570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17663PolyExtStep::Mul(11302, 11310), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17664PolyExtStep::Mul(11301, 11310), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17665PolyExtStep::Get(50), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17666PolyExtStep::Get(49), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17667PolyExtStep::Mul(11315, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17668PolyExtStep::Add(11316, 11317), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17669PolyExtStep::Get(48), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17670PolyExtStep::Mul(11318, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17671PolyExtStep::Add(11319, 11320), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17672PolyExtStep::Get(47), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17673PolyExtStep::Mul(11321, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17674PolyExtStep::Add(11322, 11323), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17675PolyExtStep::Sub(11324, 11290), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17676PolyExtStep::Mul(11325, 11311), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17677PolyExtStep::Sub(11326, 11313), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17678PolyExtStep::Sub(11327, 11314), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17679PolyExtStep::Sub(11328, 11312), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17680PolyExtStep::AndEqz(6322, 11329), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17681PolyExtStep::Mul(11150, 576), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17682PolyExtStep::Add(11303, 11330), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17683PolyExtStep::Mul(11160, 577), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17684PolyExtStep::Add(11331, 11332), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17685PolyExtStep::Mul(11170, 578), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17686PolyExtStep::Add(11333, 11334), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17687PolyExtStep::Add(11335, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17688PolyExtStep::Mul(11180, 588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17689PolyExtStep::Add(11337, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17690PolyExtStep::Mul(11336, 11338), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17691PolyExtStep::Mul(11336, 587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17692PolyExtStep::Mul(575, 11338), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17693PolyExtStep::Mul(11140, 740), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17694PolyExtStep::Mul(11150, 741), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17695PolyExtStep::Add(11342, 11343), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17696PolyExtStep::Mul(11160, 742), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17697PolyExtStep::Add(11344, 11345), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17698PolyExtStep::Mul(11170, 743), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17699PolyExtStep::Add(11346, 11347), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17700PolyExtStep::Add(11348, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17701PolyExtStep::Mul(11339, 11349), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17702PolyExtStep::Mul(11339, 739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17703PolyExtStep::Mul(11341, 11349), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17704PolyExtStep::Mul(11340, 11349), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17705PolyExtStep::Get(54), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17706PolyExtStep::Get(53), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17707PolyExtStep::Mul(11354, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17708PolyExtStep::Add(11355, 11356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17709PolyExtStep::Get(52), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17710PolyExtStep::Mul(11357, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17711PolyExtStep::Add(11358, 11359), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17712PolyExtStep::Get(51), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17713PolyExtStep::Mul(11360, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17714PolyExtStep::Add(11361, 11362), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17715PolyExtStep::Sub(11363, 11324), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17716PolyExtStep::Mul(11364, 11350), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17717PolyExtStep::Sub(11365, 11352), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17718PolyExtStep::Sub(11366, 11353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17719PolyExtStep::Sub(11367, 11351), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17720PolyExtStep::AndEqz(6323, 11368), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17721PolyExtStep::Mul(11150, 745), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17722PolyExtStep::Add(11342, 11369), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17723PolyExtStep::Mul(11160, 746), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17724PolyExtStep::Add(11370, 11371), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17725PolyExtStep::Mul(11170, 747), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17726PolyExtStep::Add(11372, 11373), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17727PolyExtStep::Add(11374, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17728PolyExtStep::Mul(11140, 766), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17729PolyExtStep::Mul(11150, 767), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17730PolyExtStep::Add(11376, 11377), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17731PolyExtStep::Mul(11160, 768), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17732PolyExtStep::Add(11378, 11379), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17733PolyExtStep::Mul(11170, 769), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17734PolyExtStep::Add(11380, 11381), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17735PolyExtStep::Add(11382, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17736PolyExtStep::Mul(11375, 11383), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17737PolyExtStep::Mul(11375, 760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17738PolyExtStep::Mul(744, 11383), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17739PolyExtStep::Mul(11150, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17740PolyExtStep::Add(11376, 11387), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17741PolyExtStep::Mul(11160, 771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17742PolyExtStep::Add(11388, 11389), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17743PolyExtStep::Mul(11170, 772), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17744PolyExtStep::Add(11390, 11391), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17745PolyExtStep::Add(11392, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17746PolyExtStep::Mul(11384, 11393), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17747PolyExtStep::Mul(11384, 761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17748PolyExtStep::Mul(11386, 11393), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17749PolyExtStep::Mul(11385, 11393), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17750PolyExtStep::Get(58), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17751PolyExtStep::Get(57), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17752PolyExtStep::Mul(11398, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17753PolyExtStep::Add(11399, 11400), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17754PolyExtStep::Get(56), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17755PolyExtStep::Mul(11401, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17756PolyExtStep::Add(11402, 11403), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17757PolyExtStep::Get(55), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17758PolyExtStep::Mul(11404, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17759PolyExtStep::Add(11405, 11406), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17760PolyExtStep::Sub(11407, 11363), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17761PolyExtStep::Mul(11408, 11394), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17762PolyExtStep::Sub(11409, 11396), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17763PolyExtStep::Sub(11410, 11397), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17764PolyExtStep::Sub(11411, 11395), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17765PolyExtStep::AndEqz(6324, 11412), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17766PolyExtStep::Mul(11180, 757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17767PolyExtStep::Add(11413, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17768PolyExtStep::Mul(11180, 781), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17769PolyExtStep::Add(11415, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17770PolyExtStep::Mul(11414, 11416), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17771PolyExtStep::Mul(11414, 762), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17772PolyExtStep::Mul(756, 11416), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17773PolyExtStep::Mul(11130, 1137), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17774PolyExtStep::Add(11420, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17775PolyExtStep::Mul(11417, 11421), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17776PolyExtStep::Mul(11417, 807), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17777PolyExtStep::Mul(11419, 11421), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17778PolyExtStep::Mul(11418, 11421), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17779PolyExtStep::Get(62), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17780PolyExtStep::Get(61), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17781PolyExtStep::Mul(11426, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17782PolyExtStep::Add(11427, 11428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17783PolyExtStep::Get(60), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17784PolyExtStep::Mul(11429, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17785PolyExtStep::Add(11430, 11431), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17786PolyExtStep::Get(59), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17787PolyExtStep::Mul(11432, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17788PolyExtStep::Add(11433, 11434), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17789PolyExtStep::Sub(11435, 11407), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17790PolyExtStep::Mul(11436, 11422), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17791PolyExtStep::Sub(11437, 11424), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17792PolyExtStep::Sub(11438, 11425), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17793PolyExtStep::Sub(11439, 11423), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17794PolyExtStep::AndEqz(6325, 11440), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17795PolyExtStep::Mul(11130, 1143), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17796PolyExtStep::Add(11441, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17797PolyExtStep::Mul(11130, 1148), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17798PolyExtStep::Add(11443, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17799PolyExtStep::Mul(11442, 11444), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17800PolyExtStep::Mul(11442, 809), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17801PolyExtStep::Mul(808, 11444), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17802PolyExtStep::Mul(11130, 1154), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17803PolyExtStep::Add(11448, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17804PolyExtStep::Mul(11445, 11449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17805PolyExtStep::Mul(11445, 810), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17806PolyExtStep::Mul(11447, 11449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17807PolyExtStep::Mul(11446, 11449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17808PolyExtStep::Get(66), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17809PolyExtStep::Get(65), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17810PolyExtStep::Mul(11454, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17811PolyExtStep::Add(11455, 11456), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17812PolyExtStep::Get(64), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17813PolyExtStep::Mul(11457, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17814PolyExtStep::Add(11458, 11459), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17815PolyExtStep::Get(63), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17816PolyExtStep::Mul(11460, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17817PolyExtStep::Add(11461, 11462), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17818PolyExtStep::Sub(11463, 11435), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17819PolyExtStep::Mul(11464, 11450), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17820PolyExtStep::Sub(11465, 11452), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17821PolyExtStep::Sub(11466, 11453), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17822PolyExtStep::Sub(11467, 11451), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17823PolyExtStep::AndEqz(6326, 11468), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17824PolyExtStep::Mul(11130, 1160), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17825PolyExtStep::Add(11469, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17826PolyExtStep::Get(70), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17827PolyExtStep::Get(69), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17828PolyExtStep::Mul(11471, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17829PolyExtStep::Add(11472, 11473), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17830PolyExtStep::Get(68), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17831PolyExtStep::Mul(11474, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17832PolyExtStep::Add(11475, 11476), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17833PolyExtStep::Get(67), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17834PolyExtStep::Mul(11477, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17835PolyExtStep::Add(11478, 11479), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17836PolyExtStep::Sub(11480, 11463), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17837PolyExtStep::Mul(11481, 11470), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17838PolyExtStep::Sub(11482, 811), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17839PolyExtStep::AndEqz(6327, 11483), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17840PolyExtStep::Get(117), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17841PolyExtStep::Get(115), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17842PolyExtStep::Mul(11484, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17843PolyExtStep::Add(11485, 11486), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17844PolyExtStep::Get(113), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17845PolyExtStep::Mul(11487, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17846PolyExtStep::Add(11488, 11489), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17847PolyExtStep::Get(111), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17848PolyExtStep::Mul(11490, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17849PolyExtStep::Add(11491, 11492), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17850PolyExtStep::Sub(11493, 11480), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17851PolyExtStep::AndEqz(6328, 11494), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17852PolyExtStep::AndCond(6319, 422, 6329), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17853PolyExtStep::AndCond(6330, 425, 6329), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17854PolyExtStep::AndCond(6331, 428, 6329), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17855PolyExtStep::GetGlobal(1, 3), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17856PolyExtStep::GetGlobal(1, 2), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17857PolyExtStep::Mul(11495, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17858PolyExtStep::Add(11496, 11497), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17859PolyExtStep::GetGlobal(1, 1), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17860PolyExtStep::Mul(11498, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17861PolyExtStep::Add(11499, 11500), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17862PolyExtStep::GetGlobal(1, 0), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17863PolyExtStep::Mul(11501, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17864PolyExtStep::Add(11502, 11503), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17865PolyExtStep::Mul(11180, 594), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17866PolyExtStep::Add(11505, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17867PolyExtStep::Mul(11276, 11506), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17868PolyExtStep::Mul(11276, 591), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17869PolyExtStep::Mul(2278, 11506), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17870PolyExtStep::Mul(11130, 556), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17871PolyExtStep::Add(11510, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17872PolyExtStep::Mul(11507, 11511), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17873PolyExtStep::Mul(11507, 555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17874PolyExtStep::Mul(11509, 11511), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17875PolyExtStep::Mul(11508, 11511), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17876PolyExtStep::Mul(11224, 11512), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17877PolyExtStep::Sub(11516, 11514), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17878PolyExtStep::Sub(11517, 11515), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17879PolyExtStep::Sub(11518, 11513), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17880PolyExtStep::AndEqz(0, 11519), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17881PolyExtStep::Mul(11130, 570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17882PolyExtStep::Add(11520, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17883PolyExtStep::Mul(11140, 572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17884PolyExtStep::Mul(11150, 574), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17885PolyExtStep::Add(11522, 11523), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17886PolyExtStep::Mul(11160, 575), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17887PolyExtStep::Add(11524, 11525), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17888PolyExtStep::Mul(11170, 576), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17889PolyExtStep::Add(11526, 11527), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17890PolyExtStep::Add(11528, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17891PolyExtStep::Mul(11521, 11529), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17892PolyExtStep::Mul(11521, 573), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17893PolyExtStep::Mul(571, 11529), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17894PolyExtStep::Mul(11150, 578), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17895PolyExtStep::Add(11522, 11533), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17896PolyExtStep::Mul(11160, 587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17897PolyExtStep::Add(11534, 11535), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17898PolyExtStep::Mul(11170, 588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17899PolyExtStep::Add(11536, 11537), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17900PolyExtStep::Add(11538, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17901PolyExtStep::Mul(11530, 11539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17902PolyExtStep::Mul(11530, 577), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17903PolyExtStep::Mul(11532, 11539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17904PolyExtStep::Mul(11531, 11539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17905PolyExtStep::Mul(11263, 11540), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17906PolyExtStep::Sub(11544, 11542), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17907PolyExtStep::Sub(11545, 11543), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17908PolyExtStep::Sub(11546, 11541), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17909PolyExtStep::AndEqz(6333, 11547), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17910PolyExtStep::Mul(11180, 740), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17911PolyExtStep::Add(11548, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17912PolyExtStep::Mul(11140, 742), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17913PolyExtStep::Mul(11150, 743), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17914PolyExtStep::Add(11550, 11551), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17915PolyExtStep::Mul(11160, 744), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17916PolyExtStep::Add(11552, 11553), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17917PolyExtStep::Mul(11170, 745), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17918PolyExtStep::Add(11554, 11555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17919PolyExtStep::Add(11556, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17920PolyExtStep::Mul(11549, 11557), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17921PolyExtStep::Mul(11549, 741), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17922PolyExtStep::Mul(739, 11557), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17923PolyExtStep::Mul(11150, 747), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17924PolyExtStep::Add(11550, 11561), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17925PolyExtStep::Mul(11160, 760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17926PolyExtStep::Add(11562, 11563), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17927PolyExtStep::Mul(11170, 766), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17928PolyExtStep::Add(11564, 11565), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17929PolyExtStep::Add(11566, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17930PolyExtStep::Mul(11558, 11567), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17931PolyExtStep::Mul(11558, 746), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17932PolyExtStep::Mul(11560, 11567), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17933PolyExtStep::Mul(11559, 11567), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17934PolyExtStep::Mul(11291, 11568), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17935PolyExtStep::Sub(11572, 11570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17936PolyExtStep::Sub(11573, 11571), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17937PolyExtStep::Sub(11574, 11569), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17938PolyExtStep::AndEqz(6334, 11575), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17939PolyExtStep::Mul(11140, 768), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17940PolyExtStep::Mul(11150, 769), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17941PolyExtStep::Add(11576, 11577), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17942PolyExtStep::Mul(11160, 761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17943PolyExtStep::Add(11578, 11579), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17944PolyExtStep::Mul(11170, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17945PolyExtStep::Add(11580, 11581), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17946PolyExtStep::Add(11582, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17947PolyExtStep::Mul(11150, 772), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17948PolyExtStep::Add(11576, 11584), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17949PolyExtStep::Mul(11160, 756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17950PolyExtStep::Add(11585, 11586), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17951PolyExtStep::Mul(11170, 757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17952PolyExtStep::Add(11587, 11588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17953PolyExtStep::Add(11589, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17954PolyExtStep::Mul(11583, 11590), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17955PolyExtStep::Mul(11583, 771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17956PolyExtStep::Mul(767, 11590), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17957PolyExtStep::Mul(11591, 11416), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17958PolyExtStep::Mul(11591, 762), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17959PolyExtStep::Mul(11593, 11416), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17960PolyExtStep::Mul(11592, 11416), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17961PolyExtStep::Mul(11325, 11594), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17962PolyExtStep::Sub(11598, 11596), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17963PolyExtStep::Sub(11599, 11597), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17964PolyExtStep::Sub(11600, 11595), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17965PolyExtStep::AndEqz(6335, 11601), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17966PolyExtStep::Mul(11180, 737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17967PolyExtStep::Add(11602, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17968PolyExtStep::Mul(11603, 11421), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17969PolyExtStep::Mul(11603, 807), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17970PolyExtStep::Mul(732, 11421), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17971PolyExtStep::Mul(11604, 11442), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17972PolyExtStep::Mul(11604, 808), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17973PolyExtStep::Mul(11606, 11442), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17974PolyExtStep::Mul(11605, 11442), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17975PolyExtStep::Mul(11364, 11607), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17976PolyExtStep::Sub(11611, 11609), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17977PolyExtStep::Sub(11612, 11610), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17978PolyExtStep::Sub(11613, 11608), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17979PolyExtStep::AndEqz(6336, 11614), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17980PolyExtStep::Mul(11444, 11449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17981PolyExtStep::Mul(11444, 810), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17982PolyExtStep::Mul(809, 11449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17983PolyExtStep::Mul(11615, 11470), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17984PolyExtStep::Mul(11615, 811), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17985PolyExtStep::Mul(11617, 11470), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17986PolyExtStep::Mul(11616, 11470), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17987PolyExtStep::Mul(11408, 11618), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17988PolyExtStep::Sub(11622, 11620), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17989PolyExtStep::Sub(11623, 11621), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17990PolyExtStep::Sub(11624, 11619), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17991PolyExtStep::AndEqz(6337, 11625), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17992PolyExtStep::Mul(11504, 1382), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17993PolyExtStep::Add(11626, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17994PolyExtStep::Mul(11202, 11627), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17995PolyExtStep::Mul(11202, 1375), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17996PolyExtStep::Mul(1372, 11627), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17997PolyExtStep::Mul(11504, 1385), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17998PolyExtStep::Add(11631, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
17999PolyExtStep::Mul(11628, 11632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18000PolyExtStep::Mul(11628, 1383), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18001PolyExtStep::Mul(11630, 11632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18002PolyExtStep::Mul(11629, 11632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18003PolyExtStep::Mul(11436, 11633), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18004PolyExtStep::Sub(11637, 11635), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18005PolyExtStep::Sub(11638, 11636), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18006PolyExtStep::Sub(11639, 11634), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18007PolyExtStep::AndEqz(6338, 11640), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18008PolyExtStep::Mul(11504, 1392), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18009PolyExtStep::Add(11641, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18010PolyExtStep::Mul(11504, 1401), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18011PolyExtStep::Add(11643, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18012PolyExtStep::Mul(11642, 11644), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18013PolyExtStep::Mul(11642, 1394), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18014PolyExtStep::Mul(1391, 11644), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18015PolyExtStep::Mul(11504, 1404), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18016PolyExtStep::Add(11648, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18017PolyExtStep::Mul(11645, 11649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18018PolyExtStep::Mul(11645, 1402), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18019PolyExtStep::Mul(11647, 11649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18020PolyExtStep::Mul(11646, 11649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18021PolyExtStep::Mul(11464, 11650), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18022PolyExtStep::Sub(11654, 11652), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18023PolyExtStep::Sub(11655, 11653), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18024PolyExtStep::Sub(11656, 11651), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18025PolyExtStep::AndEqz(6339, 11657), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18026PolyExtStep::Mul(11504, 1411), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18027PolyExtStep::Add(11658, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18028PolyExtStep::Mul(11504, 1427), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18029PolyExtStep::Add(11660, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18030PolyExtStep::Mul(11659, 11661), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18031PolyExtStep::Mul(11659, 1424), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18032PolyExtStep::Mul(1410, 11661), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18033PolyExtStep::Mul(11504, 1428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18034PolyExtStep::Add(11665, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18035PolyExtStep::Mul(11662, 11666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18036PolyExtStep::Mul(11662, 1426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18037PolyExtStep::Mul(11664, 11666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18038PolyExtStep::Mul(11663, 11666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18039PolyExtStep::Mul(11481, 11667), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18040PolyExtStep::Sub(11671, 11669), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18041PolyExtStep::Sub(11672, 11670), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18042PolyExtStep::Sub(11673, 11668), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18043PolyExtStep::AndEqz(6340, 11674), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18044PolyExtStep::Mul(11504, 1830), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18045PolyExtStep::Add(11675, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18046PolyExtStep::Mul(11504, 1430), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18047PolyExtStep::Add(11677, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18048PolyExtStep::Mul(11676, 11678), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18049PolyExtStep::Mul(11676, 1429), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18050PolyExtStep::Mul(1829, 11678), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18051PolyExtStep::Mul(11504, 1432), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18052PolyExtStep::Add(11682, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18053PolyExtStep::Mul(11679, 11683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18054PolyExtStep::Mul(11679, 1431), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18055PolyExtStep::Mul(11681, 11683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18056PolyExtStep::Mul(11680, 11683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18057PolyExtStep::Get(74), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18058PolyExtStep::Get(73), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18059PolyExtStep::Mul(11688, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18060PolyExtStep::Add(11689, 11690), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18061PolyExtStep::Get(72), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18062PolyExtStep::Mul(11691, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18063PolyExtStep::Add(11692, 11693), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18064PolyExtStep::Get(71), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18065PolyExtStep::Mul(11694, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18066PolyExtStep::Add(11695, 11696), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18067PolyExtStep::Sub(11697, 11480), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18068PolyExtStep::Mul(11698, 11684), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18069PolyExtStep::Sub(11699, 11686), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18070PolyExtStep::Sub(11700, 11687), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18071PolyExtStep::Sub(11701, 11685), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18072PolyExtStep::AndEqz(6341, 11702), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18073PolyExtStep::Mul(11504, 1440), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18074PolyExtStep::Add(11703, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18075PolyExtStep::Mul(11504, 538), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18076PolyExtStep::Add(11705, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18077PolyExtStep::Mul(11704, 11706), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18078PolyExtStep::Mul(11704, 1900), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18079PolyExtStep::Mul(1439, 11706), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18080PolyExtStep::Mul(11140, 917), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18081PolyExtStep::Mul(11150, 923), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18082PolyExtStep::Add(11710, 11711), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18083PolyExtStep::Mul(11160, 926), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18084PolyExtStep::Add(11712, 11713), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18085PolyExtStep::Mul(11170, 929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18086PolyExtStep::Add(11714, 11715), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18087PolyExtStep::Add(11716, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18088PolyExtStep::Mul(11707, 11717), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18089PolyExtStep::Mul(11707, 920), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18090PolyExtStep::Mul(11709, 11717), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18091PolyExtStep::Mul(11708, 11717), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18092PolyExtStep::Get(78), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18093PolyExtStep::Get(77), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18094PolyExtStep::Mul(11722, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18095PolyExtStep::Add(11723, 11724), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18096PolyExtStep::Get(76), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18097PolyExtStep::Mul(11725, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18098PolyExtStep::Add(11726, 11727), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18099PolyExtStep::Get(75), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18100PolyExtStep::Mul(11728, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18101PolyExtStep::Add(11729, 11730), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18102PolyExtStep::Sub(11731, 11697), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18103PolyExtStep::Mul(11732, 11718), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18104PolyExtStep::Sub(11733, 11720), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18105PolyExtStep::Sub(11734, 11721), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18106PolyExtStep::Sub(11735, 11719), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18107PolyExtStep::AndEqz(6342, 11736), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18108PolyExtStep::Mul(11150, 935), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18109PolyExtStep::Add(11710, 11737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18110PolyExtStep::Mul(11160, 938), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18111PolyExtStep::Add(11738, 11739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18112PolyExtStep::Mul(11170, 972), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18113PolyExtStep::Add(11740, 11741), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18114PolyExtStep::Add(11742, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18115PolyExtStep::Mul(11180, 978), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18116PolyExtStep::Add(11744, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18117PolyExtStep::Mul(11743, 11745), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18118PolyExtStep::Mul(11743, 975), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18119PolyExtStep::Mul(932, 11745), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18120PolyExtStep::Mul(11130, 984), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18121PolyExtStep::Add(11749, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18122PolyExtStep::Mul(11746, 11750), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18123PolyExtStep::Mul(11746, 981), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18124PolyExtStep::Mul(11748, 11750), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18125PolyExtStep::Mul(11747, 11750), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18126PolyExtStep::Get(82), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18127PolyExtStep::Get(81), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18128PolyExtStep::Mul(11755, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18129PolyExtStep::Add(11756, 11757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18130PolyExtStep::Get(80), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18131PolyExtStep::Mul(11758, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18132PolyExtStep::Add(11759, 11760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18133PolyExtStep::Get(79), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18134PolyExtStep::Mul(11761, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18135PolyExtStep::Add(11762, 11763), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18136PolyExtStep::Sub(11764, 11731), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18137PolyExtStep::Mul(11765, 11751), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18138PolyExtStep::Sub(11766, 11753), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18139PolyExtStep::Sub(11767, 11754), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18140PolyExtStep::Sub(11768, 11752), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18141PolyExtStep::AndEqz(6343, 11769), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18142PolyExtStep::Mul(11130, 993), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18143PolyExtStep::Add(11770, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18144PolyExtStep::Get(86), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18145PolyExtStep::Get(85), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18146PolyExtStep::Mul(11772, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18147PolyExtStep::Add(11773, 11774), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18148PolyExtStep::Get(84), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18149PolyExtStep::Mul(11775, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18150PolyExtStep::Add(11776, 11777), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18151PolyExtStep::Get(83), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18152PolyExtStep::Mul(11778, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18153PolyExtStep::Add(11779, 11780), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18154PolyExtStep::Sub(11781, 11764), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18155PolyExtStep::Mul(11782, 11771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18156PolyExtStep::Sub(11783, 990), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18157PolyExtStep::AndEqz(6344, 11784), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18158PolyExtStep::Sub(11493, 11781), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18159PolyExtStep::AndEqz(6345, 11785), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18160PolyExtStep::AndCond(6332, 431, 6346), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18161PolyExtStep::Mul(11180, 555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18162PolyExtStep::Add(11786, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18163PolyExtStep::Mul(11180, 563), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18164PolyExtStep::Add(11788, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18165PolyExtStep::Mul(11787, 11789), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18166PolyExtStep::Mul(11787, 556), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18167PolyExtStep::Mul(552, 11789), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18168PolyExtStep::Mul(11130, 745), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18169PolyExtStep::Add(11793, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18170PolyExtStep::Mul(11790, 11794), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18171PolyExtStep::Mul(11790, 744), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18172PolyExtStep::Mul(11792, 11794), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18173PolyExtStep::Mul(11791, 11794), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18174PolyExtStep::Mul(11224, 11795), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18175PolyExtStep::Sub(11799, 11797), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18176PolyExtStep::Sub(11800, 11798), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18177PolyExtStep::Sub(11801, 11796), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18178PolyExtStep::AndEqz(0, 11802), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18179PolyExtStep::Mul(11130, 766), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18180PolyExtStep::Add(11803, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18181PolyExtStep::Mul(11140, 767), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18182PolyExtStep::Add(11805, 11577), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18183PolyExtStep::Add(11806, 11579), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18184PolyExtStep::Add(11807, 11581), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18185PolyExtStep::Add(11808, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18186PolyExtStep::Mul(11804, 11809), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18187PolyExtStep::Mul(11804, 768), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18188PolyExtStep::Mul(760, 11809), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18189PolyExtStep::Add(11805, 11584), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18190PolyExtStep::Add(11813, 11586), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18191PolyExtStep::Add(11814, 11588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18192PolyExtStep::Add(11815, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18193PolyExtStep::Mul(11810, 11816), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18194PolyExtStep::Mul(11810, 771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18195PolyExtStep::Mul(11812, 11816), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18196PolyExtStep::Mul(11811, 11816), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18197PolyExtStep::Mul(11263, 11817), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18198PolyExtStep::Sub(11821, 11819), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18199PolyExtStep::Sub(11822, 11820), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18200PolyExtStep::Sub(11823, 11818), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18201PolyExtStep::AndEqz(6348, 11824), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18202PolyExtStep::Mul(11140, 737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18203PolyExtStep::Mul(11150, 764), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18204PolyExtStep::Add(11825, 11826), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18205PolyExtStep::Mul(11160, 798), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18206PolyExtStep::Add(11827, 11828), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18207PolyExtStep::Mul(11170, 800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18208PolyExtStep::Add(11829, 11830), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18209PolyExtStep::Add(11831, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18210PolyExtStep::Mul(11416, 11832), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18211PolyExtStep::Mul(11416, 732), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18212PolyExtStep::Mul(762, 11832), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18213PolyExtStep::Mul(11150, 804), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18214PolyExtStep::Add(11825, 11836), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18215PolyExtStep::Mul(11160, 814), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18216PolyExtStep::Add(11837, 11838), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18217PolyExtStep::Mul(11170, 817), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18218PolyExtStep::Add(11839, 11840), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18219PolyExtStep::Add(11841, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18220PolyExtStep::Mul(11833, 11842), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18221PolyExtStep::Mul(11833, 802), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18222PolyExtStep::Mul(11835, 11842), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18223PolyExtStep::Mul(11834, 11842), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18224PolyExtStep::Mul(11291, 11843), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18225PolyExtStep::Sub(11847, 11845), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18226PolyExtStep::Sub(11848, 11846), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18227PolyExtStep::Sub(11849, 11844), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18228PolyExtStep::AndEqz(6349, 11850), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18229PolyExtStep::Mul(11140, 823), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18230PolyExtStep::Mul(11150, 826), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18231PolyExtStep::Add(11851, 11852), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18232PolyExtStep::Mul(11160, 829), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18233PolyExtStep::Add(11853, 11854), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18234PolyExtStep::Mul(11170, 832), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18235PolyExtStep::Add(11855, 11856), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18236PolyExtStep::Add(11857, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18237PolyExtStep::Mul(11150, 838), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18238PolyExtStep::Add(11851, 11859), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18239PolyExtStep::Mul(11160, 841), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18240PolyExtStep::Add(11860, 11861), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18241PolyExtStep::Mul(11170, 844), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18242PolyExtStep::Add(11862, 11863), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18243PolyExtStep::Add(11864, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18244PolyExtStep::Mul(11858, 11865), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18245PolyExtStep::Mul(11858, 835), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18246PolyExtStep::Mul(820, 11865), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18247PolyExtStep::Mul(11180, 850), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18248PolyExtStep::Add(11869, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18249PolyExtStep::Mul(11866, 11870), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18250PolyExtStep::Mul(11866, 847), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18251PolyExtStep::Mul(11868, 11870), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18252PolyExtStep::Mul(11867, 11870), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18253PolyExtStep::Mul(11325, 11871), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18254PolyExtStep::Sub(11875, 11873), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18255PolyExtStep::Sub(11876, 11874), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18256PolyExtStep::Sub(11877, 11872), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18257PolyExtStep::AndEqz(6350, 11878), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18258PolyExtStep::Mul(11180, 856), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18259PolyExtStep::Add(11879, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18260PolyExtStep::Mul(11880, 11421), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18261PolyExtStep::Mul(11880, 807), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18262PolyExtStep::Mul(853, 11421), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18263PolyExtStep::Mul(11881, 11442), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18264PolyExtStep::Mul(11881, 808), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18265PolyExtStep::Mul(11883, 11442), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18266PolyExtStep::Mul(11882, 11442), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18267PolyExtStep::Mul(11364, 11884), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18268PolyExtStep::Sub(11888, 11886), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18269PolyExtStep::Sub(11889, 11887), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18270PolyExtStep::Sub(11890, 11885), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18271PolyExtStep::AndEqz(6351, 11891), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18272PolyExtStep::AndEqz(6352, 11625), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18273PolyExtStep::Mul(11130, 1382), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18274PolyExtStep::Add(11892, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18275PolyExtStep::Mul(11202, 11893), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18276PolyExtStep::Mul(1372, 11893), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18277PolyExtStep::Mul(11130, 1385), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18278PolyExtStep::Add(11896, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18279PolyExtStep::Mul(11894, 11897), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18280PolyExtStep::Mul(11894, 1383), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18281PolyExtStep::Mul(11895, 11897), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18282PolyExtStep::Mul(11629, 11897), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18283PolyExtStep::Mul(11436, 11898), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18284PolyExtStep::Sub(11902, 11900), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18285PolyExtStep::Sub(11903, 11901), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18286PolyExtStep::Sub(11904, 11899), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18287PolyExtStep::AndEqz(6353, 11905), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18288PolyExtStep::Mul(11130, 1401), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18289PolyExtStep::Add(11906, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18290PolyExtStep::Mul(11209, 11907), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18291PolyExtStep::Mul(11209, 1394), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18292PolyExtStep::Mul(1391, 11907), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18293PolyExtStep::Mul(11130, 1404), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18294PolyExtStep::Add(11911, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18295PolyExtStep::Mul(11908, 11912), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18296PolyExtStep::Mul(11908, 1402), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18297PolyExtStep::Mul(11910, 11912), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18298PolyExtStep::Mul(11909, 11912), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18299PolyExtStep::Mul(11464, 11913), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18300PolyExtStep::Sub(11917, 11915), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18301PolyExtStep::Sub(11918, 11916), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18302PolyExtStep::Sub(11919, 11914), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18303PolyExtStep::AndEqz(6354, 11920), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18304PolyExtStep::Mul(11130, 1411), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18305PolyExtStep::Add(11921, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18306PolyExtStep::Mul(11130, 1427), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18307PolyExtStep::Add(11923, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18308PolyExtStep::Mul(11922, 11924), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18309PolyExtStep::Mul(11922, 1424), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18310PolyExtStep::Mul(1410, 11924), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18311PolyExtStep::Mul(11130, 1428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18312PolyExtStep::Add(11928, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18313PolyExtStep::Mul(11925, 11929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18314PolyExtStep::Mul(11925, 1426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18315PolyExtStep::Mul(11927, 11929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18316PolyExtStep::Mul(11926, 11929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18317PolyExtStep::Mul(11481, 11930), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18318PolyExtStep::Sub(11934, 11932), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18319PolyExtStep::Sub(11935, 11933), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18320PolyExtStep::Sub(11936, 11931), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18321PolyExtStep::AndEqz(6355, 11937), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18322PolyExtStep::Mul(11130, 1830), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18323PolyExtStep::Add(11938, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18324PolyExtStep::Mul(11130, 1430), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18325PolyExtStep::Add(11940, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18326PolyExtStep::Mul(11939, 11941), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18327PolyExtStep::Mul(11939, 1429), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18328PolyExtStep::Mul(1829, 11941), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18329PolyExtStep::Mul(11942, 11683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18330PolyExtStep::Mul(11942, 1431), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18331PolyExtStep::Mul(11944, 11683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18332PolyExtStep::Mul(11943, 11683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18333PolyExtStep::Mul(11698, 11945), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18334PolyExtStep::Sub(11949, 11947), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18335PolyExtStep::Sub(11950, 11948), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18336PolyExtStep::Sub(11951, 11946), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18337PolyExtStep::AndEqz(6356, 11952), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18338PolyExtStep::Mul(11504, 539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18339PolyExtStep::Add(11953, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18340PolyExtStep::Mul(11707, 11954), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18341PolyExtStep::Mul(11707, 2278), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18342PolyExtStep::Mul(11709, 11954), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18343PolyExtStep::Mul(11708, 11954), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18344PolyExtStep::Mul(11732, 11955), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18345PolyExtStep::Sub(11959, 11957), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18346PolyExtStep::Sub(11960, 11958), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18347PolyExtStep::Sub(11961, 11956), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18348PolyExtStep::AndEqz(6357, 11962), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18349PolyExtStep::Mul(11504, 594), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18350PolyExtStep::Add(11963, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18351PolyExtStep::Mul(11504, 608), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18352PolyExtStep::Add(11965, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18353PolyExtStep::Mul(11964, 11966), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18354PolyExtStep::Mul(11964, 601), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18355PolyExtStep::Mul(591, 11966), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18356PolyExtStep::Mul(11504, 622), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18357PolyExtStep::Add(11970, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18358PolyExtStep::Mul(11967, 11971), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18359PolyExtStep::Mul(11967, 615), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18360PolyExtStep::Mul(11969, 11971), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18361PolyExtStep::Mul(11968, 11971), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18362PolyExtStep::Mul(11765, 11972), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18363PolyExtStep::Sub(11976, 11974), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18364PolyExtStep::Sub(11977, 11975), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18365PolyExtStep::Sub(11978, 11973), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18366PolyExtStep::AndEqz(6358, 11979), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18367PolyExtStep::Mul(11504, 632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18368PolyExtStep::Add(11980, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18369PolyExtStep::Mul(11504, 646), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18370PolyExtStep::Add(11982, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18371PolyExtStep::Mul(11981, 11983), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18372PolyExtStep::Mul(11981, 639), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18373PolyExtStep::Mul(629, 11983), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18374PolyExtStep::Mul(11504, 652), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18375PolyExtStep::Add(11987, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18376PolyExtStep::Mul(11984, 11988), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18377PolyExtStep::Mul(11984, 649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18378PolyExtStep::Mul(11986, 11988), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18379PolyExtStep::Mul(11985, 11988), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18380PolyExtStep::Mul(11782, 11989), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18381PolyExtStep::Sub(11993, 11991), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18382PolyExtStep::Sub(11994, 11992), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18383PolyExtStep::Sub(11995, 11990), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18384PolyExtStep::AndEqz(6359, 11996), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18385PolyExtStep::Mul(11504, 666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18386PolyExtStep::Add(11997, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18387PolyExtStep::Mul(11504, 676), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18388PolyExtStep::Add(11999, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18389PolyExtStep::Mul(11998, 12000), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18390PolyExtStep::Mul(11998, 673), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18391PolyExtStep::Mul(659, 12000), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18392PolyExtStep::Mul(11504, 551), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18393PolyExtStep::Add(12004, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18394PolyExtStep::Mul(12001, 12005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18395PolyExtStep::Mul(12001, 544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18396PolyExtStep::Mul(12003, 12005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18397PolyExtStep::Mul(12002, 12005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18398PolyExtStep::Get(90), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18399PolyExtStep::Get(89), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18400PolyExtStep::Mul(12010, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18401PolyExtStep::Add(12011, 12012), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18402PolyExtStep::Get(88), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18403PolyExtStep::Mul(12013, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18404PolyExtStep::Add(12014, 12015), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18405PolyExtStep::Get(87), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18406PolyExtStep::Mul(12016, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18407PolyExtStep::Add(12017, 12018), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18408PolyExtStep::Sub(12019, 11781), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18409PolyExtStep::Mul(12020, 12006), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18410PolyExtStep::Sub(12021, 12008), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18411PolyExtStep::Sub(12022, 12009), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18412PolyExtStep::Sub(12023, 12007), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18413PolyExtStep::AndEqz(6360, 12024), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18414PolyExtStep::Mul(11140, 1078), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18415PolyExtStep::Mul(11150, 1084), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18416PolyExtStep::Add(12025, 12026), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18417PolyExtStep::Mul(11160, 1087), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18418PolyExtStep::Add(12027, 12028), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18419PolyExtStep::Mul(11170, 1090), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18420PolyExtStep::Add(12029, 12030), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18421PolyExtStep::Add(12031, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18422PolyExtStep::Mul(11150, 1096), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18423PolyExtStep::Add(12025, 12033), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18424PolyExtStep::Mul(11160, 2736), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18425PolyExtStep::Add(12034, 12035), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18426PolyExtStep::Mul(11170, 2737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18427PolyExtStep::Add(12036, 12037), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18428PolyExtStep::Add(12038, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18429PolyExtStep::Mul(12032, 12039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18430PolyExtStep::Mul(12032, 1093), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18431PolyExtStep::Mul(1081, 12039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18432PolyExtStep::Mul(11180, 2745), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18433PolyExtStep::Add(12043, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18434PolyExtStep::Mul(12040, 12044), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18435PolyExtStep::Mul(12040, 2744), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18436PolyExtStep::Mul(12042, 12044), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18437PolyExtStep::Mul(12041, 12044), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18438PolyExtStep::Get(94), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18439PolyExtStep::Get(93), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18440PolyExtStep::Mul(12049, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18441PolyExtStep::Add(12050, 12051), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18442PolyExtStep::Get(92), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18443PolyExtStep::Mul(12052, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18444PolyExtStep::Add(12053, 12054), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18445PolyExtStep::Get(91), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18446PolyExtStep::Mul(12055, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18447PolyExtStep::Add(12056, 12057), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18448PolyExtStep::Sub(12058, 12019), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18449PolyExtStep::Mul(12059, 12045), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18450PolyExtStep::Sub(12060, 12047), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18451PolyExtStep::Sub(12061, 12048), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18452PolyExtStep::Sub(12062, 12046), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18453PolyExtStep::AndEqz(6361, 12063), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18454PolyExtStep::Mul(11130, 2751), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18455PolyExtStep::Add(12064, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18456PolyExtStep::Mul(11130, 2761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18457PolyExtStep::Add(12066, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18458PolyExtStep::Mul(12065, 12067), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18459PolyExtStep::Mul(12065, 2760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18460PolyExtStep::Mul(2750, 12067), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18461PolyExtStep::Get(98), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18462PolyExtStep::Get(97), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18463PolyExtStep::Mul(12071, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18464PolyExtStep::Add(12072, 12073), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18465PolyExtStep::Get(96), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18466PolyExtStep::Mul(12074, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18467PolyExtStep::Add(12075, 12076), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18468PolyExtStep::Get(95), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18469PolyExtStep::Mul(12077, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18470PolyExtStep::Add(12078, 12079), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18471PolyExtStep::Sub(12080, 12058), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18472PolyExtStep::Mul(12081, 12068), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18473PolyExtStep::Sub(12082, 12070), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18474PolyExtStep::Sub(12083, 12069), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18475PolyExtStep::AndEqz(6362, 12084), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18476PolyExtStep::Sub(11493, 12080), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18477PolyExtStep::AndEqz(6363, 12085), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18478PolyExtStep::AndCond(6347, 434, 6364), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18479PolyExtStep::Mul(11180, 1160), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18480PolyExtStep::Add(12086, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18481PolyExtStep::Mul(11180, 1373), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18482PolyExtStep::Add(12088, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18483PolyExtStep::Mul(12087, 12089), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18484PolyExtStep::Mul(12087, 1372), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18485PolyExtStep::Mul(811, 12089), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18486PolyExtStep::Mul(11130, 1429), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18487PolyExtStep::Add(12093, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18488PolyExtStep::Mul(12090, 12094), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18489PolyExtStep::Mul(12090, 1830), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18490PolyExtStep::Mul(12092, 12094), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18491PolyExtStep::Mul(12091, 12094), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18492PolyExtStep::Mul(11224, 12095), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18493PolyExtStep::Sub(12099, 12097), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18494PolyExtStep::Sub(12100, 12098), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18495PolyExtStep::Sub(12101, 12096), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18496PolyExtStep::AndEqz(0, 12102), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18497PolyExtStep::Mul(11130, 1439), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18498PolyExtStep::Add(12103, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18499PolyExtStep::Mul(11140, 1440), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18500PolyExtStep::Mul(11150, 538), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18501PolyExtStep::Add(12105, 12106), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18502PolyExtStep::Mul(11160, 2278), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18503PolyExtStep::Add(12107, 12108), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18504PolyExtStep::Mul(11170, 539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18505PolyExtStep::Add(12109, 12110), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18506PolyExtStep::Add(12111, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18507PolyExtStep::Mul(12104, 12112), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18508PolyExtStep::Mul(12104, 1900), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18509PolyExtStep::Mul(1432, 12112), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18510PolyExtStep::Mul(11150, 594), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18511PolyExtStep::Add(12105, 12116), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18512PolyExtStep::Mul(11160, 601), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18513PolyExtStep::Add(12117, 12118), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18514PolyExtStep::Mul(11170, 608), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18515PolyExtStep::Add(12119, 12120), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18516PolyExtStep::Add(12121, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18517PolyExtStep::Mul(12113, 12122), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18518PolyExtStep::Mul(12113, 591), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18519PolyExtStep::Mul(12115, 12122), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18520PolyExtStep::Mul(12114, 12122), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18521PolyExtStep::Mul(11263, 12123), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18522PolyExtStep::Sub(12127, 12125), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18523PolyExtStep::Sub(12128, 12126), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18524PolyExtStep::Sub(12129, 12124), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18525PolyExtStep::AndEqz(6366, 12130), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18526PolyExtStep::Mul(11180, 622), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18527PolyExtStep::Add(12131, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18528PolyExtStep::Mul(11140, 629), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18529PolyExtStep::Mul(11150, 639), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18530PolyExtStep::Add(12133, 12134), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18531PolyExtStep::Mul(11160, 646), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18532PolyExtStep::Add(12135, 12136), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18533PolyExtStep::Mul(11170, 649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18534PolyExtStep::Add(12137, 12138), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18535PolyExtStep::Add(12139, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18536PolyExtStep::Mul(12132, 12140), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18537PolyExtStep::Mul(12132, 632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18538PolyExtStep::Mul(615, 12140), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18539PolyExtStep::Mul(11150, 659), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18540PolyExtStep::Add(12133, 12144), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18541PolyExtStep::Mul(11160, 666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18542PolyExtStep::Add(12145, 12146), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18543PolyExtStep::Mul(11170, 673), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18544PolyExtStep::Add(12147, 12148), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18545PolyExtStep::Add(12149, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18546PolyExtStep::Mul(12141, 12150), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18547PolyExtStep::Mul(12141, 652), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18548PolyExtStep::Mul(12143, 12150), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18549PolyExtStep::Mul(12142, 12150), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18550PolyExtStep::Mul(11291, 12151), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18551PolyExtStep::Sub(12155, 12153), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18552PolyExtStep::Sub(12156, 12154), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18553PolyExtStep::Sub(12157, 12152), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18554PolyExtStep::AndEqz(6367, 12158), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18555PolyExtStep::Mul(11180, 544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18556PolyExtStep::Add(12159, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18557PolyExtStep::Mul(11130, 555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18558PolyExtStep::Add(12161, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18559PolyExtStep::Mul(12160, 12162), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18560PolyExtStep::Mul(12160, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18561PolyExtStep::Mul(676, 12162), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18562PolyExtStep::Mul(12163, 11299), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18563PolyExtStep::Mul(12163, 563), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18564PolyExtStep::Mul(12165, 11299), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18565PolyExtStep::Mul(12164, 11299), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18566PolyExtStep::Mul(11325, 12166), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18567PolyExtStep::Sub(12170, 12168), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18568PolyExtStep::Sub(12171, 12169), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18569PolyExtStep::Sub(12172, 12167), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18570PolyExtStep::AndEqz(6368, 12173), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18571PolyExtStep::Mul(11130, 574), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18572PolyExtStep::Add(12174, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18573PolyExtStep::Mul(11130, 578), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18574PolyExtStep::Add(12176, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18575PolyExtStep::Mul(12175, 12177), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18576PolyExtStep::Mul(12175, 577), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18577PolyExtStep::Mul(573, 12177), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18578PolyExtStep::Mul(11140, 587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18579PolyExtStep::Mul(11150, 739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18580PolyExtStep::Add(12181, 12182), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18581PolyExtStep::Mul(11160, 740), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18582PolyExtStep::Add(12183, 12184), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18583PolyExtStep::Mul(11170, 741), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18584PolyExtStep::Add(12185, 12186), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18585PolyExtStep::Add(12187, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18586PolyExtStep::Mul(12178, 12188), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18587PolyExtStep::Mul(12178, 588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18588PolyExtStep::Mul(12180, 12188), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18589PolyExtStep::Mul(12179, 12188), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18590PolyExtStep::Mul(11364, 12189), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18591PolyExtStep::Sub(12193, 12191), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18592PolyExtStep::Sub(12194, 12192), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18593PolyExtStep::Sub(12195, 12190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18594PolyExtStep::AndEqz(6369, 12196), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18595PolyExtStep::Add(12181, 11551), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18596PolyExtStep::Add(12197, 11553), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18597PolyExtStep::Add(12198, 11555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18598PolyExtStep::Add(12199, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18599PolyExtStep::Mul(11180, 747), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18600PolyExtStep::Add(12201, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18601PolyExtStep::Mul(12200, 12202), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18602PolyExtStep::Mul(12200, 746), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18603PolyExtStep::Mul(742, 12202), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18604PolyExtStep::Mul(11504, 1137), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18605PolyExtStep::Add(12206, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18606PolyExtStep::Mul(12203, 12207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18607PolyExtStep::Mul(12203, 807), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18608PolyExtStep::Mul(12205, 12207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18609PolyExtStep::Mul(12204, 12207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18610PolyExtStep::Mul(11408, 12208), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18611PolyExtStep::Sub(12212, 12210), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18612PolyExtStep::Sub(12213, 12211), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18613PolyExtStep::Sub(12214, 12209), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18614PolyExtStep::AndEqz(6370, 12215), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18615PolyExtStep::Mul(11504, 1143), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18616PolyExtStep::Add(12216, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18617PolyExtStep::Mul(11504, 1148), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18618PolyExtStep::Add(12218, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18619PolyExtStep::Mul(12217, 12219), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18620PolyExtStep::Mul(12217, 809), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18621PolyExtStep::Mul(808, 12219), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18622PolyExtStep::Mul(12220, 11449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18623PolyExtStep::Mul(12220, 810), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18624PolyExtStep::Mul(12222, 11449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18625PolyExtStep::Mul(12221, 11449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18626PolyExtStep::Mul(11436, 12223), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18627PolyExtStep::Sub(12227, 12225), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18628PolyExtStep::Sub(12228, 12226), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18629PolyExtStep::Sub(12229, 12224), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18630PolyExtStep::AndEqz(6371, 12230), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18631PolyExtStep::Mul(11140, 769), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18632PolyExtStep::Add(12231, 11387), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18633PolyExtStep::Add(12232, 11389), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18634PolyExtStep::Add(12233, 11391), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18635PolyExtStep::Add(12234, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18636PolyExtStep::Mul(11150, 757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18637PolyExtStep::Add(12231, 12236), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18638PolyExtStep::Mul(11160, 762), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18639PolyExtStep::Add(12237, 12238), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18640PolyExtStep::Mul(11170, 781), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18641PolyExtStep::Add(12239, 12240), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18642PolyExtStep::Add(12241, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18643PolyExtStep::Mul(12235, 12242), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18644PolyExtStep::Mul(12235, 756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18645PolyExtStep::Mul(761, 12242), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18646PolyExtStep::Mul(12243, 11603), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18647PolyExtStep::Mul(12243, 732), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18648PolyExtStep::Mul(12245, 11603), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18649PolyExtStep::Mul(12244, 11603), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18650PolyExtStep::Mul(11464, 12246), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18651PolyExtStep::Sub(12250, 12248), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18652PolyExtStep::Sub(12251, 12249), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18653PolyExtStep::Sub(12252, 12247), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18654PolyExtStep::AndEqz(6372, 12253), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18655PolyExtStep::Mul(11130, 798), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18656PolyExtStep::Add(12254, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18657PolyExtStep::Mul(11130, 804), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18658PolyExtStep::Add(12256, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18659PolyExtStep::Mul(12255, 12257), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18660PolyExtStep::Mul(12255, 802), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18661PolyExtStep::Mul(764, 12257), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18662PolyExtStep::Mul(11481, 12258), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18663PolyExtStep::Sub(12261, 12260), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18664PolyExtStep::Sub(12262, 12259), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18665PolyExtStep::AndEqz(6373, 12263), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18666PolyExtStep::AndEqz(6374, 11494), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18667PolyExtStep::AndCond(6365, 437, 6375), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18668PolyExtStep::Mul(11140, 632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18669PolyExtStep::Add(12264, 12134), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18670PolyExtStep::Add(12265, 12136), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18671PolyExtStep::Add(12266, 12138), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18672PolyExtStep::Add(12267, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18673PolyExtStep::Mul(12132, 12268), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18674PolyExtStep::Mul(12132, 629), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18675PolyExtStep::Mul(615, 12268), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18676PolyExtStep::Add(12264, 12144), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18677PolyExtStep::Add(12272, 12146), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18678PolyExtStep::Add(12273, 12148), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18679PolyExtStep::Add(12274, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18680PolyExtStep::Mul(12269, 12275), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18681PolyExtStep::Mul(12269, 652), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18682PolyExtStep::Mul(12271, 12275), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18683PolyExtStep::Mul(12270, 12275), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18684PolyExtStep::Mul(11291, 12276), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18685PolyExtStep::Sub(12280, 12278), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18686PolyExtStep::Sub(12281, 12279), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18687PolyExtStep::Sub(12282, 12277), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18688PolyExtStep::AndEqz(6367, 12283), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18689PolyExtStep::Mul(11140, 544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18690PolyExtStep::Mul(11150, 551), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18691PolyExtStep::Add(12284, 12285), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18692PolyExtStep::Mul(11160, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18693PolyExtStep::Add(12286, 12287), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18694PolyExtStep::Mul(11170, 555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18695PolyExtStep::Add(12288, 12289), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18696PolyExtStep::Add(12290, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18697PolyExtStep::Mul(11150, 563), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18698PolyExtStep::Add(12284, 12292), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18699PolyExtStep::Mul(11160, 564), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18700PolyExtStep::Add(12293, 12294), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18701PolyExtStep::Mul(11170, 571), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18702PolyExtStep::Add(12295, 12296), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18703PolyExtStep::Add(12297, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18704PolyExtStep::Mul(12291, 12298), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18705PolyExtStep::Mul(12291, 556), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18706PolyExtStep::Mul(676, 12298), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18707PolyExtStep::Mul(11180, 572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18708PolyExtStep::Add(12302, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18709PolyExtStep::Mul(12299, 12303), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18710PolyExtStep::Mul(12299, 570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18711PolyExtStep::Mul(12301, 12303), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18712PolyExtStep::Mul(12300, 12303), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18713PolyExtStep::Mul(11325, 12304), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18714PolyExtStep::Sub(12308, 12306), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18715PolyExtStep::Sub(12309, 12307), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18716PolyExtStep::Sub(12310, 12305), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18717PolyExtStep::AndEqz(6377, 12311), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18718PolyExtStep::Mul(11180, 574), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18719PolyExtStep::Add(12312, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18720PolyExtStep::Mul(11130, 741), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18721PolyExtStep::Add(12314, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18722PolyExtStep::Mul(12313, 12315), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18723PolyExtStep::Mul(12313, 740), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18724PolyExtStep::Mul(573, 12315), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18725PolyExtStep::Mul(11130, 744), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18726PolyExtStep::Add(12319, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18727PolyExtStep::Mul(12316, 12320), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18728PolyExtStep::Mul(12316, 743), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18729PolyExtStep::Mul(12318, 12320), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18730PolyExtStep::Mul(12317, 12320), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18731PolyExtStep::Mul(11364, 12321), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18732PolyExtStep::Sub(12325, 12323), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18733PolyExtStep::Sub(12326, 12324), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18734PolyExtStep::Sub(12327, 12322), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18735PolyExtStep::AndEqz(6378, 12328), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18736PolyExtStep::Mul(11130, 761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18737PolyExtStep::Add(12329, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18738PolyExtStep::Mul(11804, 12330), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18739PolyExtStep::Mul(11804, 769), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18740PolyExtStep::Mul(760, 12330), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18741PolyExtStep::Mul(11140, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18742PolyExtStep::Add(12334, 11584), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18743PolyExtStep::Add(12335, 11586), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18744PolyExtStep::Add(12336, 11588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18745PolyExtStep::Add(12337, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18746PolyExtStep::Mul(12331, 12338), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18747PolyExtStep::Mul(12331, 771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18748PolyExtStep::Mul(12333, 12338), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18749PolyExtStep::Mul(12332, 12338), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18750PolyExtStep::Mul(11408, 12339), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18751PolyExtStep::Sub(12343, 12341), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18752PolyExtStep::Sub(12344, 12342), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18753PolyExtStep::Sub(12345, 12340), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18754PolyExtStep::AndEqz(6379, 12346), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18755PolyExtStep::Mul(11150, 781), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18756PolyExtStep::Add(12334, 12347), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18757PolyExtStep::Mul(11160, 732), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18758PolyExtStep::Add(12348, 12349), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18759PolyExtStep::Mul(11170, 737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18760PolyExtStep::Add(12350, 12351), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18761PolyExtStep::Add(12352, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18762PolyExtStep::Mul(11180, 798), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18763PolyExtStep::Add(12354, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18764PolyExtStep::Mul(12353, 12355), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18765PolyExtStep::Mul(12353, 764), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18766PolyExtStep::Mul(762, 12355), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18767PolyExtStep::Mul(12356, 12207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18768PolyExtStep::Mul(12356, 807), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18769PolyExtStep::Mul(12358, 12207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18770PolyExtStep::Mul(12357, 12207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18771PolyExtStep::Mul(11436, 12359), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18772PolyExtStep::Sub(12363, 12361), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18773PolyExtStep::Sub(12364, 12362), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18774PolyExtStep::Sub(12365, 12360), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18775PolyExtStep::AndEqz(6380, 12366), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18776PolyExtStep::Mul(11504, 1154), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18777PolyExtStep::Add(12367, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18778PolyExtStep::Mul(12220, 12368), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18779PolyExtStep::Mul(12222, 12368), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18780PolyExtStep::Mul(12221, 12368), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18781PolyExtStep::Mul(11464, 12369), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18782PolyExtStep::Sub(12372, 12370), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18783PolyExtStep::Sub(12373, 12371), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18784PolyExtStep::Sub(12374, 12224), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18785PolyExtStep::AndEqz(6381, 12375), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18786PolyExtStep::Mul(11140, 800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18787PolyExtStep::Add(12376, 11836), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18788PolyExtStep::Add(12377, 11838), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18789PolyExtStep::Add(12378, 11840), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18790PolyExtStep::Add(12379, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18791PolyExtStep::Mul(11150, 823), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18792PolyExtStep::Add(12376, 12381), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18793PolyExtStep::Mul(11160, 826), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18794PolyExtStep::Add(12382, 12383), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18795PolyExtStep::Mul(11170, 829), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18796PolyExtStep::Add(12384, 12385), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18797PolyExtStep::Add(12386, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18798PolyExtStep::Mul(12380, 12387), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18799PolyExtStep::Mul(12380, 820), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18800PolyExtStep::Mul(802, 12387), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18801PolyExtStep::Mul(11180, 835), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18802PolyExtStep::Add(12391, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18803PolyExtStep::Mul(12388, 12392), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18804PolyExtStep::Mul(12388, 832), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18805PolyExtStep::Mul(12390, 12392), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18806PolyExtStep::Mul(12389, 12392), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18807PolyExtStep::Mul(11481, 12393), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18808PolyExtStep::Sub(12397, 12395), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18809PolyExtStep::Sub(12398, 12396), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18810PolyExtStep::Sub(12399, 12394), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18811PolyExtStep::AndEqz(6382, 12400), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18812PolyExtStep::Mul(11130, 841), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18813PolyExtStep::Add(12401, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18814PolyExtStep::Mul(11130, 850), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18815PolyExtStep::Add(12403, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18816PolyExtStep::Mul(12402, 12404), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18817PolyExtStep::Mul(12402, 847), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18818PolyExtStep::Mul(838, 12404), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18819PolyExtStep::Mul(11698, 12405), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18820PolyExtStep::Sub(12408, 12407), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18821PolyExtStep::Sub(12409, 12406), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18822PolyExtStep::AndEqz(6383, 12410), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18823PolyExtStep::Sub(11493, 11697), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18824PolyExtStep::AndEqz(6384, 12411), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18825PolyExtStep::AndCond(6376, 440, 6385), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18826PolyExtStep::Mul(11180, 1078), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18827PolyExtStep::Add(12412, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18828PolyExtStep::Mul(11180, 1084), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18829PolyExtStep::Add(12414, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18830PolyExtStep::Mul(12413, 12415), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18831PolyExtStep::Mul(12413, 1081), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18832PolyExtStep::Mul(1075, 12415), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18833PolyExtStep::Mul(11140, 1137), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18834PolyExtStep::Mul(11150, 808), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18835PolyExtStep::Add(12419, 12420), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18836PolyExtStep::Mul(11160, 1143), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18837PolyExtStep::Add(12421, 12422), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18838PolyExtStep::Mul(11170, 809), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18839PolyExtStep::Add(12423, 12424), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18840PolyExtStep::Add(12425, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18841PolyExtStep::Mul(12416, 12426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18842PolyExtStep::Mul(12416, 807), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18843PolyExtStep::Mul(12418, 12426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18844PolyExtStep::Mul(12417, 12426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18845PolyExtStep::Mul(11224, 12427), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18846PolyExtStep::Sub(12431, 12429), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18847PolyExtStep::Sub(12432, 12430), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18848PolyExtStep::Sub(12433, 12428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18849PolyExtStep::AndEqz(0, 12434), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18850PolyExtStep::Mul(11150, 810), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18851PolyExtStep::Add(12419, 12435), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18852PolyExtStep::Mul(11160, 1154), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18853PolyExtStep::Add(12436, 12437), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18854PolyExtStep::Mul(11170, 811), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18855PolyExtStep::Add(12438, 12439), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18856PolyExtStep::Add(12440, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18857PolyExtStep::Mul(11140, 1372), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18858PolyExtStep::Mul(11150, 1373), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18859PolyExtStep::Add(12442, 12443), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18860PolyExtStep::Mul(11160, 1375), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18861PolyExtStep::Add(12444, 12445), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18862PolyExtStep::Mul(11170, 1382), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18863PolyExtStep::Add(12446, 12447), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18864PolyExtStep::Add(12448, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18865PolyExtStep::Mul(12441, 12449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18866PolyExtStep::Mul(12441, 1160), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18867PolyExtStep::Mul(1148, 12449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18868PolyExtStep::Mul(11150, 1385), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18869PolyExtStep::Add(12442, 12453), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18870PolyExtStep::Mul(11160, 1391), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18871PolyExtStep::Add(12454, 12455), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18872PolyExtStep::Mul(11170, 1392), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18873PolyExtStep::Add(12456, 12457), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18874PolyExtStep::Add(12458, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18875PolyExtStep::Mul(12450, 12459), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18876PolyExtStep::Mul(12450, 1383), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18877PolyExtStep::Mul(12452, 12459), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18878PolyExtStep::Mul(12451, 12459), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18879PolyExtStep::Mul(11263, 12460), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18880PolyExtStep::Sub(12464, 12462), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18881PolyExtStep::Sub(12465, 12463), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18882PolyExtStep::Sub(12466, 12461), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18883PolyExtStep::AndEqz(6387, 12467), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18884PolyExtStep::Mul(11140, 1401), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18885PolyExtStep::Mul(11150, 1402), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18886PolyExtStep::Add(12468, 12469), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18887PolyExtStep::Mul(11160, 1404), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18888PolyExtStep::Add(12470, 12471), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18889PolyExtStep::Mul(11170, 1410), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18890PolyExtStep::Add(12472, 12473), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18891PolyExtStep::Add(12474, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18892PolyExtStep::Mul(11150, 1424), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18893PolyExtStep::Add(12468, 12476), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18894PolyExtStep::Mul(11160, 1427), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18895PolyExtStep::Add(12477, 12478), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18896PolyExtStep::Mul(11170, 1426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18897PolyExtStep::Add(12479, 12480), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18898PolyExtStep::Add(12481, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18899PolyExtStep::Mul(12475, 12482), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18900PolyExtStep::Mul(12475, 1411), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18901PolyExtStep::Mul(1394, 12482), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18902PolyExtStep::Mul(11140, 1829), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18903PolyExtStep::Mul(11150, 1830), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18904PolyExtStep::Add(12486, 12487), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18905PolyExtStep::Mul(11160, 1429), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18906PolyExtStep::Add(12488, 12489), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18907PolyExtStep::Mul(11170, 1430), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18908PolyExtStep::Add(12490, 12491), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18909PolyExtStep::Add(12492, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18910PolyExtStep::Mul(12483, 12493), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18911PolyExtStep::Mul(12483, 1428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18912PolyExtStep::Mul(12485, 12493), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18913PolyExtStep::Mul(12484, 12493), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18914PolyExtStep::Mul(11291, 12494), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18915PolyExtStep::Sub(12498, 12496), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18916PolyExtStep::Sub(12499, 12497), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18917PolyExtStep::Sub(12500, 12495), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18918PolyExtStep::AndEqz(6388, 12501), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18919PolyExtStep::Mul(11150, 1432), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18920PolyExtStep::Add(12486, 12502), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18921PolyExtStep::Mul(11160, 1439), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18922PolyExtStep::Add(12503, 12504), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18923PolyExtStep::Mul(11170, 1440), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18924PolyExtStep::Add(12505, 12506), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18925PolyExtStep::Add(12507, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18926PolyExtStep::Mul(11140, 538), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18927PolyExtStep::Mul(11150, 2278), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18928PolyExtStep::Add(12509, 12510), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18929PolyExtStep::Mul(11160, 539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18930PolyExtStep::Add(12511, 12512), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18931PolyExtStep::Mul(11170, 591), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18932PolyExtStep::Add(12513, 12514), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18933PolyExtStep::Add(12515, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18934PolyExtStep::Mul(12508, 12516), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18935PolyExtStep::Mul(12508, 1900), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18936PolyExtStep::Mul(1431, 12516), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18937PolyExtStep::Mul(11150, 601), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18938PolyExtStep::Add(12509, 12520), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18939PolyExtStep::Mul(11160, 608), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18940PolyExtStep::Add(12521, 12522), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18941PolyExtStep::Mul(11170, 615), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18942PolyExtStep::Add(12523, 12524), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18943PolyExtStep::Add(12525, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18944PolyExtStep::Mul(12517, 12526), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18945PolyExtStep::Mul(12517, 594), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18946PolyExtStep::Mul(12519, 12526), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18947PolyExtStep::Mul(12518, 12526), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18948PolyExtStep::Mul(11325, 12527), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18949PolyExtStep::Sub(12531, 12529), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18950PolyExtStep::Sub(12532, 12530), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18951PolyExtStep::Sub(12533, 12528), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18952PolyExtStep::AndEqz(6389, 12534), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18953PolyExtStep::Mul(11150, 632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18954PolyExtStep::Add(12133, 12535), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18955PolyExtStep::Mul(11160, 639), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18956PolyExtStep::Add(12536, 12537), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18957PolyExtStep::Mul(11170, 646), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18958PolyExtStep::Add(12538, 12539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18959PolyExtStep::Add(12540, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18960PolyExtStep::Mul(11150, 652), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18961PolyExtStep::Add(12133, 12542), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18962PolyExtStep::Mul(11160, 659), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18963PolyExtStep::Add(12543, 12544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18964PolyExtStep::Mul(11170, 666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18965PolyExtStep::Add(12545, 12546), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18966PolyExtStep::Add(12547, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18967PolyExtStep::Mul(12541, 12548), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18968PolyExtStep::Mul(12541, 649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18969PolyExtStep::Mul(622, 12548), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18970PolyExtStep::Mul(11140, 676), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18971PolyExtStep::Mul(11150, 544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18972PolyExtStep::Add(12552, 12553), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18973PolyExtStep::Mul(11160, 551), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18974PolyExtStep::Add(12554, 12555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18975PolyExtStep::Mul(11170, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18976PolyExtStep::Add(12556, 12557), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18977PolyExtStep::Add(12558, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18978PolyExtStep::Mul(12549, 12559), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18979PolyExtStep::Mul(12549, 673), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18980PolyExtStep::Mul(12551, 12559), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18981PolyExtStep::Mul(12550, 12559), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18982PolyExtStep::Mul(11364, 12560), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18983PolyExtStep::Sub(12564, 12562), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18984PolyExtStep::Sub(12565, 12563), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18985PolyExtStep::Sub(12566, 12561), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18986PolyExtStep::AndEqz(6390, 12567), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18987PolyExtStep::Mul(11150, 556), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18988PolyExtStep::Add(12552, 12568), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18989PolyExtStep::Mul(11160, 563), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18990PolyExtStep::Add(12569, 12570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18991PolyExtStep::Mul(11170, 564), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18992PolyExtStep::Add(12571, 12572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18993PolyExtStep::Add(12573, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18994PolyExtStep::Mul(11140, 570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18995PolyExtStep::Add(12575, 11304), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18996PolyExtStep::Add(12576, 11306), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18997PolyExtStep::Add(12577, 11308), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18998PolyExtStep::Add(12578, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
18999PolyExtStep::Mul(12574, 12579), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19000PolyExtStep::Mul(12574, 571), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19001PolyExtStep::Mul(555, 12579), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19002PolyExtStep::Add(12575, 11330), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19003PolyExtStep::Add(12583, 11332), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19004PolyExtStep::Add(12584, 11334), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19005PolyExtStep::Add(12585, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19006PolyExtStep::Mul(12580, 12586), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19007PolyExtStep::Mul(12580, 575), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19008PolyExtStep::Mul(12582, 12586), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19009PolyExtStep::Mul(12581, 12586), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19010PolyExtStep::Mul(11408, 12587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19011PolyExtStep::Sub(12591, 12589), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19012PolyExtStep::Sub(12592, 12590), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19013PolyExtStep::Sub(12593, 12588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19014PolyExtStep::AndEqz(6391, 12594), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19015PolyExtStep::Mul(11338, 11549), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19016PolyExtStep::Mul(11338, 739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19017PolyExtStep::Mul(587, 11549), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19018PolyExtStep::Mul(11180, 742), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19019PolyExtStep::Add(12598, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19020PolyExtStep::Mul(12595, 12599), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19021PolyExtStep::Mul(12595, 741), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19022PolyExtStep::Mul(12597, 12599), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19023PolyExtStep::Mul(12596, 12599), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19024PolyExtStep::Mul(11436, 12600), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19025PolyExtStep::Sub(12604, 12602), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19026PolyExtStep::Sub(12605, 12603), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19027PolyExtStep::Sub(12606, 12601), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19028PolyExtStep::AndEqz(6392, 12607), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19029PolyExtStep::Mul(11180, 744), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19030PolyExtStep::Add(12608, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19031PolyExtStep::Mul(11180, 746), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19032PolyExtStep::Add(12610, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19033PolyExtStep::Mul(12609, 12611), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19034PolyExtStep::Mul(12609, 745), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19035PolyExtStep::Mul(743, 12611), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19036PolyExtStep::Mul(11180, 760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19037PolyExtStep::Add(12615, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19038PolyExtStep::Mul(12612, 12616), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19039PolyExtStep::Mul(12612, 747), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19040PolyExtStep::Mul(12614, 12616), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19041PolyExtStep::Mul(12613, 12616), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19042PolyExtStep::Mul(11464, 12617), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19043PolyExtStep::Sub(12621, 12619), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19044PolyExtStep::Sub(12622, 12620), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19045PolyExtStep::Sub(12623, 12618), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19046PolyExtStep::AndEqz(6393, 12624), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19047PolyExtStep::Mul(11180, 767), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19048PolyExtStep::Add(12625, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19049PolyExtStep::Mul(11180, 769), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19050PolyExtStep::Add(12627, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19051PolyExtStep::Mul(12626, 12628), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19052PolyExtStep::Mul(12626, 768), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19053PolyExtStep::Mul(766, 12628), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19054PolyExtStep::Mul(11130, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19055PolyExtStep::Add(12632, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19056PolyExtStep::Mul(12629, 12633), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19057PolyExtStep::Mul(12629, 761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19058PolyExtStep::Mul(12631, 12633), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19059PolyExtStep::Mul(12630, 12633), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19060PolyExtStep::Mul(11481, 12634), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19061PolyExtStep::Sub(12638, 12636), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19062PolyExtStep::Sub(12639, 12637), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19063PolyExtStep::Sub(12640, 12635), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19064PolyExtStep::AndEqz(6394, 12641), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19065PolyExtStep::Mul(11130, 772), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19066PolyExtStep::Add(12642, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19067PolyExtStep::Mul(11130, 757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19068PolyExtStep::Add(12644, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19069PolyExtStep::Mul(12643, 12645), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19070PolyExtStep::Mul(12643, 756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19071PolyExtStep::Mul(771, 12645), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19072PolyExtStep::Mul(11130, 781), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19073PolyExtStep::Add(12649, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19074PolyExtStep::Mul(12646, 12650), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19075PolyExtStep::Mul(12646, 762), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19076PolyExtStep::Mul(12648, 12650), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19077PolyExtStep::Mul(12647, 12650), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19078PolyExtStep::Mul(11698, 12651), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19079PolyExtStep::Sub(12655, 12653), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19080PolyExtStep::Sub(12656, 12654), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19081PolyExtStep::Sub(12657, 12652), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19082PolyExtStep::AndEqz(6395, 12658), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19083PolyExtStep::Mul(11130, 737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19084PolyExtStep::Add(12659, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19085PolyExtStep::Mul(12660, 12255), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19086PolyExtStep::Mul(12660, 764), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19087PolyExtStep::Mul(732, 12255), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19088PolyExtStep::Mul(11130, 802), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19089PolyExtStep::Add(12664, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19090PolyExtStep::Mul(12661, 12665), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19091PolyExtStep::Mul(12661, 800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19092PolyExtStep::Mul(12663, 12665), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19093PolyExtStep::Mul(12662, 12665), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19094PolyExtStep::Mul(11732, 12666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19095PolyExtStep::Sub(12670, 12668), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19096PolyExtStep::Sub(12671, 12669), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19097PolyExtStep::Sub(12672, 12667), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19098PolyExtStep::AndEqz(6396, 12673), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19099PolyExtStep::Mul(11130, 814), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19100PolyExtStep::Add(12674, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19101PolyExtStep::Mul(11130, 820), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19102PolyExtStep::Add(12676, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19103PolyExtStep::Mul(12675, 12677), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19104PolyExtStep::Mul(12675, 817), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19105PolyExtStep::Mul(804, 12677), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19106PolyExtStep::Mul(11130, 826), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19107PolyExtStep::Add(12681, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19108PolyExtStep::Mul(12678, 12682), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19109PolyExtStep::Mul(12678, 823), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19110PolyExtStep::Mul(12680, 12682), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19111PolyExtStep::Mul(12679, 12682), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19112PolyExtStep::Mul(11765, 12683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19113PolyExtStep::Sub(12687, 12685), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19114PolyExtStep::Sub(12688, 12686), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19115PolyExtStep::Sub(12689, 12684), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19116PolyExtStep::AndEqz(6397, 12690), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19117PolyExtStep::Mul(11130, 832), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19118PolyExtStep::Add(12691, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19119PolyExtStep::Mul(11130, 838), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19120PolyExtStep::Add(12693, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19121PolyExtStep::Mul(12692, 12694), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19122PolyExtStep::Mul(12692, 835), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19123PolyExtStep::Mul(829, 12694), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19124PolyExtStep::Mul(11130, 844), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19125PolyExtStep::Add(12698, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19126PolyExtStep::Mul(12695, 12699), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19127PolyExtStep::Mul(12695, 841), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19128PolyExtStep::Mul(12697, 12699), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19129PolyExtStep::Mul(12696, 12699), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19130PolyExtStep::Mul(11782, 12700), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19131PolyExtStep::Sub(12704, 12702), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19132PolyExtStep::Sub(12705, 12703), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19133PolyExtStep::Sub(12706, 12701), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19134PolyExtStep::AndEqz(6398, 12707), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19135PolyExtStep::Mul(11130, 856), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19136PolyExtStep::Add(12708, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19137PolyExtStep::Mul(12404, 12709), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19138PolyExtStep::Mul(12404, 853), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19139PolyExtStep::Mul(847, 12709), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19140PolyExtStep::Mul(11130, 893), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19141PolyExtStep::Add(12713, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19142PolyExtStep::Mul(12710, 12714), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19143PolyExtStep::Mul(12710, 859), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19144PolyExtStep::Mul(12712, 12714), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19145PolyExtStep::Mul(12711, 12714), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19146PolyExtStep::Mul(12020, 12715), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19147PolyExtStep::Sub(12719, 12717), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19148PolyExtStep::Sub(12720, 12718), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19149PolyExtStep::Sub(12721, 12716), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19150PolyExtStep::AndEqz(6399, 12722), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19151PolyExtStep::Mul(11504, 899), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19152PolyExtStep::Add(12723, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19153PolyExtStep::Mul(11504, 905), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19154PolyExtStep::Add(12725, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19155PolyExtStep::Mul(12724, 12726), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19156PolyExtStep::Mul(12724, 902), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19157PolyExtStep::Mul(896, 12726), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19158PolyExtStep::Mul(11504, 911), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19159PolyExtStep::Add(12730, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19160PolyExtStep::Mul(12727, 12731), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19161PolyExtStep::Mul(12727, 908), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19162PolyExtStep::Mul(12729, 12731), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19163PolyExtStep::Mul(12728, 12731), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19164PolyExtStep::Mul(12059, 12732), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19165PolyExtStep::Sub(12736, 12734), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19166PolyExtStep::Sub(12737, 12735), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19167PolyExtStep::Sub(12738, 12733), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19168PolyExtStep::AndEqz(6400, 12739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19169PolyExtStep::Mul(11504, 917), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19170PolyExtStep::Add(12740, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19171PolyExtStep::Mul(11504, 923), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19172PolyExtStep::Add(12742, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19173PolyExtStep::Mul(12741, 12743), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19174PolyExtStep::Mul(12741, 920), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19175PolyExtStep::Mul(914, 12743), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19176PolyExtStep::Mul(11504, 929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19177PolyExtStep::Add(12747, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19178PolyExtStep::Mul(12744, 12748), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19179PolyExtStep::Mul(12744, 926), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19180PolyExtStep::Mul(12746, 12748), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19181PolyExtStep::Mul(12745, 12748), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19182PolyExtStep::Mul(12081, 12749), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19183PolyExtStep::Sub(12753, 12751), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19184PolyExtStep::Sub(12754, 12752), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19185PolyExtStep::Sub(12755, 12750), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19186PolyExtStep::AndEqz(6401, 12756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19187PolyExtStep::Mul(11504, 935), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19188PolyExtStep::Add(12757, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19189PolyExtStep::Mul(11504, 972), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19190PolyExtStep::Add(12759, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19191PolyExtStep::Mul(12758, 12760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19192PolyExtStep::Mul(12758, 938), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19193PolyExtStep::Mul(932, 12760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19194PolyExtStep::Mul(11504, 978), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19195PolyExtStep::Add(12764, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19196PolyExtStep::Mul(12761, 12765), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19197PolyExtStep::Mul(12761, 975), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19198PolyExtStep::Mul(12763, 12765), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19199PolyExtStep::Mul(12762, 12765), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19200PolyExtStep::Get(102), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19201PolyExtStep::Get(101), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19202PolyExtStep::Mul(12770, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19203PolyExtStep::Add(12771, 12772), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19204PolyExtStep::Get(100), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19205PolyExtStep::Mul(12773, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19206PolyExtStep::Add(12774, 12775), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19207PolyExtStep::Get(99), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19208PolyExtStep::Mul(12776, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19209PolyExtStep::Add(12777, 12778), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19210PolyExtStep::Sub(12779, 12080), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19211PolyExtStep::Mul(12780, 12766), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19212PolyExtStep::Sub(12781, 12768), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19213PolyExtStep::Sub(12782, 12769), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19214PolyExtStep::Sub(12783, 12767), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19215PolyExtStep::AndEqz(6402, 12784), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19216PolyExtStep::Mul(11504, 984), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19217PolyExtStep::Add(12785, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19218PolyExtStep::Mul(11504, 990), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19219PolyExtStep::Add(12787, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19220PolyExtStep::Mul(12786, 12788), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19221PolyExtStep::Mul(12786, 987), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19222PolyExtStep::Mul(981, 12788), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19223PolyExtStep::Mul(11504, 996), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19224PolyExtStep::Add(12792, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19225PolyExtStep::Mul(12789, 12793), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19226PolyExtStep::Mul(12789, 993), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19227PolyExtStep::Mul(12791, 12793), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19228PolyExtStep::Mul(12790, 12793), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19229PolyExtStep::Get(106), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19230PolyExtStep::Get(105), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19231PolyExtStep::Mul(12798, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19232PolyExtStep::Add(12799, 12800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19233PolyExtStep::Get(104), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19234PolyExtStep::Mul(12801, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19235PolyExtStep::Add(12802, 12803), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19236PolyExtStep::Get(103), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19237PolyExtStep::Mul(12804, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19238PolyExtStep::Add(12805, 12806), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19239PolyExtStep::Sub(12807, 12779), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19240PolyExtStep::Mul(12808, 12794), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19241PolyExtStep::Sub(12809, 12796), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19242PolyExtStep::Sub(12810, 12797), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19243PolyExtStep::Sub(12811, 12795), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19244PolyExtStep::AndEqz(6403, 12812), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19245PolyExtStep::Mul(11504, 1002), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19246PolyExtStep::Add(12813, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19247PolyExtStep::Mul(11504, 1008), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19248PolyExtStep::Add(12815, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19249PolyExtStep::Mul(12814, 12816), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19250PolyExtStep::Mul(12814, 1005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19251PolyExtStep::Mul(999, 12816), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19252PolyExtStep::Mul(11504, 1014), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19253PolyExtStep::Add(12820, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19254PolyExtStep::Mul(12817, 12821), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19255PolyExtStep::Mul(12817, 1011), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19256PolyExtStep::Mul(12819, 12821), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19257PolyExtStep::Mul(12818, 12821), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19258PolyExtStep::Get(110), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19259PolyExtStep::Get(109), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19260PolyExtStep::Mul(12826, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19261PolyExtStep::Add(12827, 12828), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19262PolyExtStep::Get(108), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19263PolyExtStep::Mul(12829, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19264PolyExtStep::Add(12830, 12831), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19265PolyExtStep::Get(107), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19266PolyExtStep::Mul(12832, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19267PolyExtStep::Add(12833, 12834), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19268PolyExtStep::Sub(12835, 12807), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19269PolyExtStep::Mul(12836, 12822), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19270PolyExtStep::Sub(12837, 12824), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19271PolyExtStep::Sub(12838, 12825), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19272PolyExtStep::Sub(12839, 12823), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19273PolyExtStep::AndEqz(6404, 12840), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19274PolyExtStep::Mul(11504, 1051), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19275PolyExtStep::Add(12841, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19276PolyExtStep::Sub(11493, 12835), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19277PolyExtStep::Mul(12843, 12842), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19278PolyExtStep::Sub(12844, 1017), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19279PolyExtStep::AndEqz(6405, 12845), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19280PolyExtStep::AndCond(6386, 443, 6406), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19281PolyExtStep::Mul(11180, 570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19282PolyExtStep::Add(12846, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19283PolyExtStep::Mul(11180, 573), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19284PolyExtStep::Add(12848, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19285PolyExtStep::Mul(12847, 12849), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19286PolyExtStep::Mul(12847, 572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19287PolyExtStep::Mul(571, 12849), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19288PolyExtStep::Mul(11130, 577), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19289PolyExtStep::Add(12853, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19290PolyExtStep::Mul(12850, 12854), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19291PolyExtStep::Mul(12850, 576), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19292PolyExtStep::Mul(12852, 12854), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19293PolyExtStep::Mul(12851, 12854), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19294PolyExtStep::Mul(11224, 12855), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19295PolyExtStep::Sub(12859, 12857), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19296PolyExtStep::Sub(12860, 12858), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19297PolyExtStep::Sub(12861, 12856), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19298PolyExtStep::AndEqz(0, 12862), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19299PolyExtStep::Mul(11130, 739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19300PolyExtStep::Add(12863, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19301PolyExtStep::Mul(12864, 12426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19302PolyExtStep::Mul(12864, 807), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19303PolyExtStep::Mul(588, 12426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19304PolyExtStep::Mul(12865, 12441), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19305PolyExtStep::Mul(12865, 1148), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19306PolyExtStep::Mul(12867, 12441), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19307PolyExtStep::Mul(12866, 12441), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19308PolyExtStep::Mul(11263, 12868), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19309PolyExtStep::Sub(12872, 12870), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19310PolyExtStep::Sub(12873, 12871), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19311PolyExtStep::Sub(12874, 12869), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19312PolyExtStep::AndEqz(6408, 12875), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19313PolyExtStep::Mul(12449, 12459), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19314PolyExtStep::Mul(12449, 1383), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19315PolyExtStep::Mul(1160, 12459), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19316PolyExtStep::Mul(12876, 12475), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19317PolyExtStep::Mul(12876, 1394), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19318PolyExtStep::Mul(12878, 12475), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19319PolyExtStep::Mul(12877, 12475), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19320PolyExtStep::Mul(11291, 12879), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19321PolyExtStep::Sub(12883, 12881), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19322PolyExtStep::Sub(12884, 12882), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19323PolyExtStep::Sub(12885, 12880), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19324PolyExtStep::AndEqz(6409, 12886), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19325PolyExtStep::Mul(12482, 12493), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19326PolyExtStep::Mul(12482, 1428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19327PolyExtStep::Mul(1411, 12493), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19328PolyExtStep::Mul(12887, 12508), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19329PolyExtStep::Mul(12887, 1431), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19330PolyExtStep::Mul(12889, 12508), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19331PolyExtStep::Mul(12888, 12508), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19332PolyExtStep::Mul(11325, 12890), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19333PolyExtStep::Sub(12894, 12892), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19334PolyExtStep::Sub(12895, 12893), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19335PolyExtStep::Sub(12896, 12891), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19336PolyExtStep::AndEqz(6410, 12897), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19337PolyExtStep::Mul(11271, 11276), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19338PolyExtStep::Mul(11271, 2278), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19339PolyExtStep::Mul(1900, 11276), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19340PolyExtStep::Mul(12898, 11506), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19341PolyExtStep::Mul(12898, 591), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19342PolyExtStep::Mul(12900, 11506), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19343PolyExtStep::Mul(12899, 11506), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19344PolyExtStep::Mul(11364, 12901), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19345PolyExtStep::Sub(12905, 12903), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19346PolyExtStep::Sub(12906, 12904), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19347PolyExtStep::Sub(12907, 12902), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19348PolyExtStep::AndEqz(6411, 12908), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19349PolyExtStep::Mul(11180, 608), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19350PolyExtStep::Add(12909, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19351PolyExtStep::Mul(11130, 622), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19352PolyExtStep::Add(12911, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19353PolyExtStep::Mul(12910, 12912), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19354PolyExtStep::Mul(12910, 615), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19355PolyExtStep::Mul(601, 12912), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19356PolyExtStep::Mul(11130, 632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19357PolyExtStep::Add(12916, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19358PolyExtStep::Mul(12913, 12917), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19359PolyExtStep::Mul(12913, 629), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19360PolyExtStep::Mul(12915, 12917), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19361PolyExtStep::Mul(12914, 12917), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19362PolyExtStep::Mul(11408, 12918), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19363PolyExtStep::Sub(12922, 12920), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19364PolyExtStep::Sub(12923, 12921), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19365PolyExtStep::Sub(12924, 12919), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19366PolyExtStep::AndEqz(6412, 12925), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19367PolyExtStep::Mul(11130, 646), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19368PolyExtStep::Add(12926, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19369PolyExtStep::Mul(11130, 652), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19370PolyExtStep::Add(12928, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19371PolyExtStep::Mul(12927, 12929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19372PolyExtStep::Mul(12927, 649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19373PolyExtStep::Mul(639, 12929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19374PolyExtStep::Mul(12930, 11998), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19375PolyExtStep::Mul(12930, 659), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19376PolyExtStep::Mul(12932, 11998), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19377PolyExtStep::Mul(12931, 11998), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19378PolyExtStep::Mul(11436, 12933), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19379PolyExtStep::Sub(12937, 12935), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19380PolyExtStep::Sub(12938, 12936), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19381PolyExtStep::Sub(12939, 12934), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19382PolyExtStep::AndEqz(6413, 12940), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19383PolyExtStep::Mul(12000, 12005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19384PolyExtStep::Mul(12000, 544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19385PolyExtStep::Mul(673, 12005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19386PolyExtStep::Mul(11504, 555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19387PolyExtStep::Add(12944, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19388PolyExtStep::Mul(12941, 12945), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19389PolyExtStep::Mul(12941, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19390PolyExtStep::Mul(12943, 12945), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19391PolyExtStep::Mul(12942, 12945), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19392PolyExtStep::Mul(11464, 12946), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19393PolyExtStep::Sub(12950, 12948), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19394PolyExtStep::Sub(12951, 12949), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19395PolyExtStep::Sub(12952, 12947), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19396PolyExtStep::AndEqz(6414, 12953), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19397PolyExtStep::Mul(12692, 12402), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19398PolyExtStep::Mul(12692, 838), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19399PolyExtStep::Mul(829, 12402), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19400PolyExtStep::Mul(11481, 12954), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19401PolyExtStep::Sub(12957, 12956), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19402PolyExtStep::Sub(12958, 12955), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19403PolyExtStep::AndEqz(6415, 12959), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19404PolyExtStep::AndEqz(6416, 11494), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19405PolyExtStep::AndCond(6407, 446, 6417), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19406PolyExtStep::Mul(11180, 1090), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19407PolyExtStep::Add(12960, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19408PolyExtStep::Mul(11180, 1096), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19409PolyExtStep::Add(12962, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19410PolyExtStep::Mul(12961, 12963), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19411PolyExtStep::Mul(12961, 1093), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19412PolyExtStep::Mul(1087, 12963), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19413PolyExtStep::Mul(11140, 591), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19414PolyExtStep::Add(12967, 12116), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19415PolyExtStep::Add(12968, 12118), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19416PolyExtStep::Add(12969, 12120), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19417PolyExtStep::Add(12970, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19418PolyExtStep::Mul(12964, 12971), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19419PolyExtStep::Mul(12964, 539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19420PolyExtStep::Mul(12966, 12971), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19421PolyExtStep::Mul(12965, 12971), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19422PolyExtStep::Mul(11224, 12972), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19423PolyExtStep::Sub(12976, 12974), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19424PolyExtStep::Sub(12977, 12975), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19425PolyExtStep::Sub(12978, 12973), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19426PolyExtStep::AndEqz(0, 12979), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19427PolyExtStep::Mul(11150, 622), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19428PolyExtStep::Add(12967, 12980), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19429PolyExtStep::Mul(11160, 629), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19430PolyExtStep::Add(12981, 12982), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19431PolyExtStep::Mul(11170, 632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19432PolyExtStep::Add(12983, 12984), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19433PolyExtStep::Add(12985, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19434PolyExtStep::Mul(11140, 646), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19435PolyExtStep::Mul(11150, 649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19436PolyExtStep::Add(12987, 12988), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19437PolyExtStep::Mul(11160, 652), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19438PolyExtStep::Add(12989, 12990), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19439PolyExtStep::Mul(11170, 659), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19440PolyExtStep::Add(12991, 12992), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19441PolyExtStep::Add(12993, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19442PolyExtStep::Mul(12986, 12994), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19443PolyExtStep::Mul(12986, 639), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19444PolyExtStep::Mul(615, 12994), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19445PolyExtStep::Mul(11150, 673), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19446PolyExtStep::Add(12987, 12998), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19447PolyExtStep::Mul(11160, 676), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19448PolyExtStep::Add(12999, 13000), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19449PolyExtStep::Mul(11170, 544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19450PolyExtStep::Add(13001, 13002), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19451PolyExtStep::Add(13003, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19452PolyExtStep::Mul(12995, 13004), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19453PolyExtStep::Mul(12995, 666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19454PolyExtStep::Mul(12997, 13004), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19455PolyExtStep::Mul(12996, 13004), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19456PolyExtStep::Mul(11263, 13005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19457PolyExtStep::Sub(13009, 13007), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19458PolyExtStep::Sub(13010, 13008), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19459PolyExtStep::Sub(13011, 13006), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19460PolyExtStep::AndEqz(6419, 13012), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19461PolyExtStep::Mul(11140, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19462PolyExtStep::Mul(11150, 555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19463PolyExtStep::Add(13013, 13014), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19464PolyExtStep::Mul(11160, 556), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19465PolyExtStep::Add(13015, 13016), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19466PolyExtStep::Mul(11170, 563), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19467PolyExtStep::Add(13017, 13018), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19468PolyExtStep::Add(13019, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19469PolyExtStep::Mul(11150, 571), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19470PolyExtStep::Add(13013, 13021), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19471PolyExtStep::Mul(11160, 570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19472PolyExtStep::Add(13022, 13023), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19473PolyExtStep::Mul(11170, 572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19474PolyExtStep::Add(13024, 13025), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19475PolyExtStep::Add(13026, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19476PolyExtStep::Mul(13020, 13027), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19477PolyExtStep::Mul(13020, 564), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19478PolyExtStep::Mul(551, 13027), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19479PolyExtStep::Mul(11140, 574), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19480PolyExtStep::Mul(11150, 575), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19481PolyExtStep::Add(13031, 13032), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19482PolyExtStep::Mul(11160, 576), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19483PolyExtStep::Add(13033, 13034), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19484PolyExtStep::Mul(11170, 577), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19485PolyExtStep::Add(13035, 13036), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19486PolyExtStep::Add(13037, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19487PolyExtStep::Mul(13028, 13038), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19488PolyExtStep::Mul(13028, 573), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19489PolyExtStep::Mul(13030, 13038), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19490PolyExtStep::Mul(13029, 13038), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19491PolyExtStep::Mul(11291, 13039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19492PolyExtStep::Sub(13043, 13041), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19493PolyExtStep::Sub(13044, 13042), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19494PolyExtStep::Sub(13045, 13040), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19495PolyExtStep::AndEqz(6420, 13046), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19496PolyExtStep::Mul(11150, 587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19497PolyExtStep::Add(13031, 13047), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19498PolyExtStep::Mul(11160, 588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19499PolyExtStep::Add(13048, 13049), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19500PolyExtStep::Mul(11170, 739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19501PolyExtStep::Add(13050, 13051), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19502PolyExtStep::Add(13052, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19503PolyExtStep::Mul(11140, 741), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19504PolyExtStep::Mul(11150, 742), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19505PolyExtStep::Add(13054, 13055), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19506PolyExtStep::Mul(11160, 743), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19507PolyExtStep::Add(13056, 13057), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19508PolyExtStep::Mul(11170, 744), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19509PolyExtStep::Add(13058, 13059), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19510PolyExtStep::Add(13060, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19511PolyExtStep::Mul(13053, 13061), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19512PolyExtStep::Mul(13053, 740), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19513PolyExtStep::Mul(578, 13061), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19514PolyExtStep::Mul(11150, 746), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19515PolyExtStep::Add(13054, 13065), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19516PolyExtStep::Mul(11160, 747), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19517PolyExtStep::Add(13066, 13067), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19518PolyExtStep::Mul(11170, 760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19519PolyExtStep::Add(13068, 13069), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19520PolyExtStep::Add(13070, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19521PolyExtStep::Mul(13062, 13071), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19522PolyExtStep::Mul(13062, 745), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19523PolyExtStep::Mul(13064, 13071), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19524PolyExtStep::Mul(13063, 13071), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19525PolyExtStep::Mul(11325, 13072), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19526PolyExtStep::Sub(13076, 13074), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19527PolyExtStep::Sub(13077, 13075), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19528PolyExtStep::Sub(13078, 13073), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19529PolyExtStep::AndEqz(6421, 13079), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19530PolyExtStep::Mul(11150, 768), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19531PolyExtStep::Add(11805, 13080), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19532PolyExtStep::Mul(11160, 769), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19533PolyExtStep::Add(13081, 13082), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19534PolyExtStep::Mul(11170, 761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19535PolyExtStep::Add(13083, 13084), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19536PolyExtStep::Add(13085, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19537PolyExtStep::Mul(11150, 771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19538PolyExtStep::Add(11805, 13087), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19539PolyExtStep::Mul(11160, 772), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19540PolyExtStep::Add(13088, 13089), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19541PolyExtStep::Mul(11170, 756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19542PolyExtStep::Add(13090, 13091), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19543PolyExtStep::Add(13092, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19544PolyExtStep::Mul(13086, 13093), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19545PolyExtStep::Mul(13086, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19546PolyExtStep::Mul(766, 13093), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19547PolyExtStep::Mul(11140, 762), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19548PolyExtStep::Add(13097, 12347), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19549PolyExtStep::Add(13098, 12349), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19550PolyExtStep::Add(13099, 12351), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19551PolyExtStep::Add(13100, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19552PolyExtStep::Mul(13094, 13101), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19553PolyExtStep::Mul(13094, 757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19554PolyExtStep::Mul(13096, 13101), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19555PolyExtStep::Mul(13095, 13101), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19556PolyExtStep::Mul(11364, 13102), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19557PolyExtStep::Sub(13106, 13104), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19558PolyExtStep::Sub(13107, 13105), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19559PolyExtStep::Sub(13108, 13103), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19560PolyExtStep::AndEqz(6422, 13109), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19561PolyExtStep::Mul(11150, 798), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19562PolyExtStep::Add(13097, 13110), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19563PolyExtStep::Mul(11160, 800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19564PolyExtStep::Add(13111, 13112), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19565PolyExtStep::Mul(11170, 802), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19566PolyExtStep::Add(13113, 13114), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19567PolyExtStep::Add(13115, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19568PolyExtStep::Mul(11140, 814), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19569PolyExtStep::Mul(11150, 817), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19570PolyExtStep::Add(13117, 13118), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19571PolyExtStep::Mul(11160, 820), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19572PolyExtStep::Add(13119, 13120), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19573PolyExtStep::Mul(11170, 823), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19574PolyExtStep::Add(13121, 13122), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19575PolyExtStep::Add(13123, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19576PolyExtStep::Mul(13116, 13124), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19577PolyExtStep::Mul(13116, 804), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19578PolyExtStep::Mul(764, 13124), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19579PolyExtStep::Mul(11150, 829), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19580PolyExtStep::Add(13117, 13128), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19581PolyExtStep::Mul(11160, 832), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19582PolyExtStep::Add(13129, 13130), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19583PolyExtStep::Mul(11170, 835), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19584PolyExtStep::Add(13131, 13132), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19585PolyExtStep::Add(13133, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19586PolyExtStep::Mul(13125, 13134), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19587PolyExtStep::Mul(13125, 826), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19588PolyExtStep::Mul(13127, 13134), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19589PolyExtStep::Mul(13126, 13134), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19590PolyExtStep::Mul(11408, 13135), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19591PolyExtStep::Sub(13139, 13137), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19592PolyExtStep::Sub(13140, 13138), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19593PolyExtStep::Sub(13141, 13136), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19594PolyExtStep::AndEqz(6423, 13142), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19595PolyExtStep::Mul(11180, 841), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19596PolyExtStep::Add(13143, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19597PolyExtStep::Mul(11180, 847), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19598PolyExtStep::Add(13145, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19599PolyExtStep::Mul(13144, 13146), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19600PolyExtStep::Mul(13144, 844), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19601PolyExtStep::Mul(838, 13146), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19602PolyExtStep::Mul(11180, 853), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19603PolyExtStep::Add(13150, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19604PolyExtStep::Mul(13147, 13151), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19605PolyExtStep::Mul(13147, 850), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19606PolyExtStep::Mul(13149, 13151), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19607PolyExtStep::Mul(13148, 13151), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19608PolyExtStep::Mul(11436, 13152), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19609PolyExtStep::Sub(13156, 13154), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19610PolyExtStep::Sub(13157, 13155), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19611PolyExtStep::Sub(13158, 13153), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19612PolyExtStep::AndEqz(6424, 13159), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19613PolyExtStep::Mul(11180, 859), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19614PolyExtStep::Add(13160, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19615PolyExtStep::Mul(11180, 896), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19616PolyExtStep::Add(13162, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19617PolyExtStep::Mul(13161, 13163), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19618PolyExtStep::Mul(13161, 893), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19619PolyExtStep::Mul(856, 13163), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19620PolyExtStep::Mul(11180, 902), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19621PolyExtStep::Add(13167, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19622PolyExtStep::Mul(13164, 13168), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19623PolyExtStep::Mul(13164, 899), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19624PolyExtStep::Mul(13166, 13168), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19625PolyExtStep::Mul(13165, 13168), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19626PolyExtStep::Mul(11464, 13169), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19627PolyExtStep::Sub(13173, 13171), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19628PolyExtStep::Sub(13174, 13172), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19629PolyExtStep::Sub(13175, 13170), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19630PolyExtStep::AndEqz(6425, 13176), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19631PolyExtStep::Mul(11180, 908), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19632PolyExtStep::Add(13177, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19633PolyExtStep::Mul(11180, 914), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19634PolyExtStep::Add(13179, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19635PolyExtStep::Mul(13178, 13180), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19636PolyExtStep::Mul(13178, 911), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19637PolyExtStep::Mul(905, 13180), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19638PolyExtStep::Mul(11130, 629), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19639PolyExtStep::Add(13184, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19640PolyExtStep::Mul(13181, 13185), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19641PolyExtStep::Mul(13181, 917), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19642PolyExtStep::Mul(13183, 13185), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19643PolyExtStep::Mul(13182, 13185), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19644PolyExtStep::Mul(11481, 13186), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19645PolyExtStep::Sub(13190, 13188), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19646PolyExtStep::Sub(13191, 13189), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19647PolyExtStep::Sub(13192, 13187), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19648PolyExtStep::AndEqz(6426, 13193), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19649PolyExtStep::Mul(11130, 926), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19650PolyExtStep::Add(13194, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19651PolyExtStep::Mul(12917, 13195), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19652PolyExtStep::Mul(12917, 923), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19653PolyExtStep::Mul(920, 13195), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19654PolyExtStep::Mul(11130, 676), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19655PolyExtStep::Add(13199, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19656PolyExtStep::Mul(13196, 13200), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19657PolyExtStep::Mul(13196, 929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19658PolyExtStep::Mul(13198, 13200), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19659PolyExtStep::Mul(13197, 13200), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19660PolyExtStep::Mul(11698, 13201), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19661PolyExtStep::Sub(13205, 13203), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19662PolyExtStep::Sub(13206, 13204), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19663PolyExtStep::Sub(13207, 13202), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19664PolyExtStep::AndEqz(6427, 13208), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19665PolyExtStep::Mul(11130, 544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19666PolyExtStep::Add(13209, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19667PolyExtStep::Mul(11130, 938), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19668PolyExtStep::Add(13211, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19669PolyExtStep::Mul(13210, 13212), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19670PolyExtStep::Mul(13210, 935), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19671PolyExtStep::Mul(932, 13212), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19672PolyExtStep::Mul(13213, 11521), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19673PolyExtStep::Mul(13213, 972), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19674PolyExtStep::Mul(13215, 11521), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19675PolyExtStep::Mul(13214, 11521), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19676PolyExtStep::Mul(11732, 13216), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19677PolyExtStep::Sub(13220, 13218), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19678PolyExtStep::Sub(13221, 13219), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19679PolyExtStep::Sub(13222, 13217), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19680PolyExtStep::AndEqz(6428, 13223), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19681PolyExtStep::Mul(11130, 572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19682PolyExtStep::Add(13224, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19683PolyExtStep::Mul(11130, 981), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19684PolyExtStep::Add(13226, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19685PolyExtStep::Mul(13225, 13227), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19686PolyExtStep::Mul(13225, 978), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19687PolyExtStep::Mul(975, 13227), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19688PolyExtStep::Mul(11130, 588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19689PolyExtStep::Add(13231, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19690PolyExtStep::Mul(13228, 13232), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19691PolyExtStep::Mul(13228, 984), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19692PolyExtStep::Mul(13230, 13232), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19693PolyExtStep::Mul(13229, 13232), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19694PolyExtStep::Mul(11765, 13233), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19695PolyExtStep::Sub(13237, 13235), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19696PolyExtStep::Sub(13238, 13236), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19697PolyExtStep::Sub(13239, 13234), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19698PolyExtStep::AndEqz(6429, 13240), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19699PolyExtStep::Mul(12864, 11771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19700PolyExtStep::Mul(12864, 990), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19701PolyExtStep::Mul(987, 11771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19702PolyExtStep::Mul(11130, 747), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19703PolyExtStep::Add(13244, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19704PolyExtStep::Mul(13241, 13245), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19705PolyExtStep::Mul(13241, 996), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19706PolyExtStep::Mul(13243, 13245), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19707PolyExtStep::Mul(13242, 13245), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19708PolyExtStep::Mul(11782, 13246), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19709PolyExtStep::Sub(13250, 13248), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19710PolyExtStep::Sub(13251, 13249), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19711PolyExtStep::Sub(13252, 13247), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19712PolyExtStep::AndEqz(6430, 13253), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19713PolyExtStep::Mul(11130, 760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19714PolyExtStep::Add(13254, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19715PolyExtStep::Mul(11130, 1005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19716PolyExtStep::Add(13256, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19717PolyExtStep::Mul(13255, 13257), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19718PolyExtStep::Mul(13255, 1002), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19719PolyExtStep::Mul(999, 13257), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19720PolyExtStep::Mul(13258, 12643), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19721PolyExtStep::Mul(13258, 1008), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19722PolyExtStep::Mul(13260, 12643), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19723PolyExtStep::Mul(13259, 12643), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19724PolyExtStep::Mul(12020, 13261), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19725PolyExtStep::Sub(13265, 13263), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19726PolyExtStep::Sub(13266, 13264), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19727PolyExtStep::Sub(13267, 13262), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19728PolyExtStep::AndEqz(6431, 13268), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19729PolyExtStep::Mul(11130, 756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19730PolyExtStep::Add(13269, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19731PolyExtStep::Mul(11130, 1017), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19732PolyExtStep::Add(13271, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19733PolyExtStep::Mul(13270, 13272), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19734PolyExtStep::Mul(13270, 1014), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19735PolyExtStep::Mul(1011, 13272), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19736PolyExtStep::Mul(11130, 800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19737PolyExtStep::Add(13276, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19738PolyExtStep::Mul(13273, 13277), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19739PolyExtStep::Mul(13273, 1051), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19740PolyExtStep::Mul(13275, 13277), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19741PolyExtStep::Mul(13274, 13277), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19742PolyExtStep::Mul(12059, 13278), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19743PolyExtStep::Sub(13282, 13280), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19744PolyExtStep::Sub(13283, 13281), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19745PolyExtStep::Sub(13284, 13279), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19746PolyExtStep::AndEqz(6432, 13285), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19747PolyExtStep::Mul(11130, 1060), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19748PolyExtStep::Add(13286, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19749PolyExtStep::Mul(12665, 13287), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19750PolyExtStep::Mul(12665, 1057), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19751PolyExtStep::Mul(1054, 13287), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19752PolyExtStep::Mul(13288, 12692), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19753PolyExtStep::Mul(13288, 1063), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19754PolyExtStep::Mul(13290, 12692), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19755PolyExtStep::Mul(13289, 12692), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19756PolyExtStep::Mul(12081, 13291), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19757PolyExtStep::Sub(13295, 13293), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19758PolyExtStep::Sub(13296, 13294), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19759PolyExtStep::Sub(13297, 13292), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19760PolyExtStep::AndEqz(6433, 13298), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19761PolyExtStep::Mul(11130, 835), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19762PolyExtStep::Add(13299, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19763PolyExtStep::Mul(11130, 1072), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19764PolyExtStep::Add(13301, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19765PolyExtStep::Mul(13300, 13302), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19766PolyExtStep::Mul(13300, 1069), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19767PolyExtStep::Mul(1066, 13302), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19768PolyExtStep::Mul(11504, 1078), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19769PolyExtStep::Add(13306, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19770PolyExtStep::Mul(13303, 13307), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19771PolyExtStep::Mul(13303, 1075), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19772PolyExtStep::Mul(13305, 13307), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19773PolyExtStep::Mul(13304, 13307), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19774PolyExtStep::Mul(12780, 13308), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19775PolyExtStep::Sub(13312, 13310), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19776PolyExtStep::Sub(13313, 13311), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19777PolyExtStep::Sub(13314, 13309), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19778PolyExtStep::AndEqz(6434, 13315), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19779PolyExtStep::Mul(11504, 1084), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19780PolyExtStep::Add(13316, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19781PolyExtStep::Mul(12808, 13317), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19782PolyExtStep::Sub(13318, 1081), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19783PolyExtStep::AndEqz(6435, 13319), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19784PolyExtStep::Sub(11493, 12807), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19785PolyExtStep::AndEqz(6436, 13320), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19786PolyExtStep::AndCond(6418, 449, 6437), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19787PolyExtStep::Mul(11180, 591), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19788PolyExtStep::Add(13321, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19789PolyExtStep::Mul(11180, 601), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19790PolyExtStep::Add(13323, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19791PolyExtStep::Mul(13322, 13324), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19792PolyExtStep::Mul(13322, 594), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19793PolyExtStep::Mul(539, 13324), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19794PolyExtStep::Mul(11224, 13325), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19795PolyExtStep::Sub(13328, 13327), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19796PolyExtStep::Sub(13329, 13326), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19797PolyExtStep::AndEqz(0, 13330), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19798PolyExtStep::Sub(11493, 11223), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19799PolyExtStep::AndEqz(6439, 13331), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19800PolyExtStep::AndCond(6438, 452, 6440), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19801PolyExtStep::Mul(11180, 1075), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19802PolyExtStep::Add(13332, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19803PolyExtStep::Mul(11180, 1081), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19804PolyExtStep::Add(13334, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19805PolyExtStep::Mul(13333, 13335), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19806PolyExtStep::Mul(13333, 1078), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19807PolyExtStep::Mul(1072, 13335), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19808PolyExtStep::Mul(11140, 817), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19809PolyExtStep::Mul(11150, 820), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19810PolyExtStep::Add(13339, 13340), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19811PolyExtStep::Mul(11160, 823), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19812PolyExtStep::Add(13341, 13342), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19813PolyExtStep::Mul(11170, 826), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19814PolyExtStep::Add(13343, 13344), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19815PolyExtStep::Add(13345, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19816PolyExtStep::Mul(13336, 13346), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19817PolyExtStep::Mul(13336, 814), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19818PolyExtStep::Mul(13338, 13346), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19819PolyExtStep::Mul(13337, 13346), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19820PolyExtStep::Mul(11224, 13347), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19821PolyExtStep::Sub(13351, 13349), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19822PolyExtStep::Sub(13352, 13350), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19823PolyExtStep::Sub(13353, 13348), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19824PolyExtStep::AndEqz(0, 13354), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19825PolyExtStep::Mul(11150, 832), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19826PolyExtStep::Add(13339, 13355), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19827PolyExtStep::Mul(11160, 835), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19828PolyExtStep::Add(13356, 13357), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19829PolyExtStep::Mul(11170, 838), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19830PolyExtStep::Add(13358, 13359), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19831PolyExtStep::Add(13360, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19832PolyExtStep::Mul(11140, 844), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19833PolyExtStep::Mul(11150, 847), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19834PolyExtStep::Add(13362, 13363), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19835PolyExtStep::Mul(11160, 850), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19836PolyExtStep::Add(13364, 13365), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19837PolyExtStep::Mul(11170, 853), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19838PolyExtStep::Add(13366, 13367), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19839PolyExtStep::Add(13368, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19840PolyExtStep::Mul(13361, 13369), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19841PolyExtStep::Mul(13361, 841), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19842PolyExtStep::Mul(829, 13369), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19843PolyExtStep::Mul(11150, 859), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19844PolyExtStep::Add(13362, 13373), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19845PolyExtStep::Mul(11160, 893), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19846PolyExtStep::Add(13374, 13375), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19847PolyExtStep::Mul(11170, 896), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19848PolyExtStep::Add(13376, 13377), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19849PolyExtStep::Add(13378, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19850PolyExtStep::Mul(13370, 13379), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19851PolyExtStep::Mul(13370, 856), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19852PolyExtStep::Mul(13372, 13379), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19853PolyExtStep::Mul(13371, 13379), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19854PolyExtStep::Mul(11263, 13380), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19855PolyExtStep::Sub(13384, 13382), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19856PolyExtStep::Sub(13385, 13383), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19857PolyExtStep::Sub(13386, 13381), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19858PolyExtStep::AndEqz(6442, 13387), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19859PolyExtStep::Mul(11140, 902), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19860PolyExtStep::Mul(11150, 905), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19861PolyExtStep::Add(13388, 13389), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19862PolyExtStep::Mul(11160, 908), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19863PolyExtStep::Add(13390, 13391), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19864PolyExtStep::Mul(11170, 911), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19865PolyExtStep::Add(13392, 13393), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19866PolyExtStep::Add(13394, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19867PolyExtStep::Mul(11150, 917), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19868PolyExtStep::Add(13388, 13396), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19869PolyExtStep::Mul(11160, 920), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19870PolyExtStep::Add(13397, 13398), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19871PolyExtStep::Mul(11170, 923), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19872PolyExtStep::Add(13399, 13400), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19873PolyExtStep::Add(13401, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19874PolyExtStep::Mul(13395, 13402), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19875PolyExtStep::Mul(13395, 914), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19876PolyExtStep::Mul(899, 13402), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19877PolyExtStep::Mul(11140, 929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19878PolyExtStep::Mul(11150, 932), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19879PolyExtStep::Add(13406, 13407), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19880PolyExtStep::Mul(11160, 935), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19881PolyExtStep::Add(13408, 13409), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19882PolyExtStep::Mul(11170, 938), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19883PolyExtStep::Add(13410, 13411), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19884PolyExtStep::Add(13412, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19885PolyExtStep::Mul(13403, 13413), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19886PolyExtStep::Mul(13403, 926), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19887PolyExtStep::Mul(13405, 13413), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19888PolyExtStep::Mul(13404, 13413), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19889PolyExtStep::Mul(11291, 13414), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19890PolyExtStep::Sub(13418, 13416), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19891PolyExtStep::Sub(13419, 13417), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19892PolyExtStep::Sub(13420, 13415), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19893PolyExtStep::AndEqz(6443, 13421), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19894PolyExtStep::Mul(11150, 975), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19895PolyExtStep::Add(13406, 13422), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19896PolyExtStep::Mul(11160, 978), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19897PolyExtStep::Add(13423, 13424), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19898PolyExtStep::Mul(11170, 981), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19899PolyExtStep::Add(13425, 13426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19900PolyExtStep::Add(13427, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19901PolyExtStep::Mul(11140, 987), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19902PolyExtStep::Mul(11150, 990), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19903PolyExtStep::Add(13429, 13430), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19904PolyExtStep::Mul(11160, 993), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19905PolyExtStep::Add(13431, 13432), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19906PolyExtStep::Mul(11170, 996), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19907PolyExtStep::Add(13433, 13434), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19908PolyExtStep::Add(13435, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19909PolyExtStep::Mul(13428, 13436), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19910PolyExtStep::Mul(13428, 984), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19911PolyExtStep::Mul(972, 13436), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19912PolyExtStep::Mul(11150, 1002), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19913PolyExtStep::Add(13429, 13440), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19914PolyExtStep::Mul(11160, 1005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19915PolyExtStep::Add(13441, 13442), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19916PolyExtStep::Mul(11170, 1008), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19917PolyExtStep::Add(13443, 13444), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19918PolyExtStep::Add(13445, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19919PolyExtStep::Mul(13437, 13446), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19920PolyExtStep::Mul(13437, 999), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19921PolyExtStep::Mul(13439, 13446), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19922PolyExtStep::Mul(13438, 13446), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19923PolyExtStep::Mul(11325, 13447), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19924PolyExtStep::Sub(13451, 13449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19925PolyExtStep::Sub(13452, 13450), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19926PolyExtStep::Sub(13453, 13448), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19927PolyExtStep::AndEqz(6444, 13454), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19928PolyExtStep::Mul(11180, 1014), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19929PolyExtStep::Add(13455, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19930PolyExtStep::Mul(11180, 1051), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19931PolyExtStep::Add(13457, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19932PolyExtStep::Mul(13456, 13458), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19933PolyExtStep::Mul(13456, 1017), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19934PolyExtStep::Mul(1011, 13458), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19935PolyExtStep::Mul(11180, 1057), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19936PolyExtStep::Add(13462, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19937PolyExtStep::Mul(13459, 13463), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19938PolyExtStep::Mul(13459, 1054), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19939PolyExtStep::Mul(13461, 13463), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19940PolyExtStep::Mul(13460, 13463), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19941PolyExtStep::Mul(11364, 13464), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19942PolyExtStep::Sub(13468, 13466), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19943PolyExtStep::Sub(13469, 13467), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19944PolyExtStep::Sub(13470, 13465), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19945PolyExtStep::AndEqz(6445, 13471), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19946PolyExtStep::Mul(11180, 1063), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19947PolyExtStep::Add(13472, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19948PolyExtStep::Mul(11180, 1069), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19949PolyExtStep::Add(13474, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19950PolyExtStep::Mul(13473, 13475), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19951PolyExtStep::Mul(13473, 1066), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19952PolyExtStep::Mul(1060, 13475), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19953PolyExtStep::Mul(11408, 13476), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19954PolyExtStep::Sub(13479, 13478), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19955PolyExtStep::Sub(13480, 13477), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19956PolyExtStep::AndEqz(6446, 13481), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19957PolyExtStep::Sub(11493, 11407), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19958PolyExtStep::AndEqz(6447, 13482), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19959PolyExtStep::AndCond(6441, 455, 6448), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19960PolyExtStep::Mul(11180, 935), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19961PolyExtStep::Add(13483, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19962PolyExtStep::Mul(11180, 972), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19963PolyExtStep::Add(13485, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19964PolyExtStep::Mul(13484, 13486), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19965PolyExtStep::Mul(13484, 938), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19966PolyExtStep::Mul(932, 13486), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19967PolyExtStep::Mul(11140, 1411), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19968PolyExtStep::Add(13490, 12476), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19969PolyExtStep::Add(13491, 12478), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19970PolyExtStep::Add(13492, 12480), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19971PolyExtStep::Add(13493, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19972PolyExtStep::Mul(13487, 13494), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19973PolyExtStep::Mul(13487, 1410), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19974PolyExtStep::Mul(13489, 13494), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19975PolyExtStep::Mul(13488, 13494), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19976PolyExtStep::Mul(11224, 13495), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19977PolyExtStep::Sub(13499, 13497), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19978PolyExtStep::Sub(13500, 13498), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19979PolyExtStep::Sub(13501, 13496), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19980PolyExtStep::AndEqz(0, 13502), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19981PolyExtStep::Mul(11150, 1829), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19982PolyExtStep::Add(13490, 13503), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19983PolyExtStep::Mul(11160, 1830), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19984PolyExtStep::Add(13504, 13505), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19985PolyExtStep::Mul(11170, 1429), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19986PolyExtStep::Add(13506, 13507), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19987PolyExtStep::Add(13508, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19988PolyExtStep::Mul(11140, 1431), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19989PolyExtStep::Add(13510, 12502), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19990PolyExtStep::Add(13511, 12504), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19991PolyExtStep::Add(13512, 12506), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19992PolyExtStep::Add(13513, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19993PolyExtStep::Mul(13509, 13514), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19994PolyExtStep::Mul(13509, 1430), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19995PolyExtStep::Mul(1428, 13514), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19996PolyExtStep::Add(13510, 12106), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19997PolyExtStep::Add(13518, 12108), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19998PolyExtStep::Add(13519, 12110), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
19999PolyExtStep::Add(13520, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20000PolyExtStep::Mul(13515, 13521), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20001PolyExtStep::Mul(13515, 1900), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20002PolyExtStep::Mul(13517, 13521), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20003PolyExtStep::Mul(13516, 13521), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20004PolyExtStep::Mul(11263, 13522), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20005PolyExtStep::Sub(13526, 13524), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20006PolyExtStep::Sub(13527, 13525), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20007PolyExtStep::Sub(13528, 13523), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20008PolyExtStep::AndEqz(6450, 13529), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20009PolyExtStep::Mul(11140, 594), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20010PolyExtStep::Add(13530, 12520), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20011PolyExtStep::Add(13531, 12522), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20012PolyExtStep::Add(13532, 12524), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20013PolyExtStep::Add(13533, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20014PolyExtStep::Mul(11150, 629), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20015PolyExtStep::Add(13530, 13535), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20016PolyExtStep::Mul(11160, 632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20017PolyExtStep::Add(13536, 13537), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20018PolyExtStep::Mul(11170, 639), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20019PolyExtStep::Add(13538, 13539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20020PolyExtStep::Add(13540, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20021PolyExtStep::Mul(13534, 13541), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20022PolyExtStep::Mul(13534, 622), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20023PolyExtStep::Mul(591, 13541), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20024PolyExtStep::Mul(11140, 649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20025PolyExtStep::Add(13545, 12542), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20026PolyExtStep::Add(13546, 12544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20027PolyExtStep::Add(13547, 12546), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20028PolyExtStep::Add(13548, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20029PolyExtStep::Mul(13542, 13549), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20030PolyExtStep::Mul(13542, 646), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20031PolyExtStep::Mul(13544, 13549), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20032PolyExtStep::Mul(13543, 13549), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20033PolyExtStep::Mul(11291, 13550), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20034PolyExtStep::Sub(13554, 13552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20035PolyExtStep::Sub(13555, 13553), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20036PolyExtStep::Sub(13556, 13551), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20037PolyExtStep::AndEqz(6451, 13557), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20038PolyExtStep::Mul(11150, 676), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20039PolyExtStep::Add(13545, 13558), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20040PolyExtStep::Mul(11160, 544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20041PolyExtStep::Add(13559, 13560), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20042PolyExtStep::Mul(11170, 551), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20043PolyExtStep::Add(13561, 13562), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20044PolyExtStep::Add(13563, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20045PolyExtStep::Mul(11140, 555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20046PolyExtStep::Add(13565, 12568), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20047PolyExtStep::Add(13566, 12570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20048PolyExtStep::Add(13567, 12572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20049PolyExtStep::Add(13568, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20050PolyExtStep::Mul(13564, 13569), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20051PolyExtStep::Mul(13564, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20052PolyExtStep::Mul(673, 13569), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20053PolyExtStep::Mul(11150, 570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20054PolyExtStep::Add(13565, 13573), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20055PolyExtStep::Mul(11160, 572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20056PolyExtStep::Add(13574, 13575), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20057PolyExtStep::Mul(11170, 573), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20058PolyExtStep::Add(13576, 13577), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20059PolyExtStep::Add(13578, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20060PolyExtStep::Mul(13570, 13579), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20061PolyExtStep::Mul(13570, 571), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20062PolyExtStep::Mul(13572, 13579), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20063PolyExtStep::Mul(13571, 13579), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20064PolyExtStep::Mul(11325, 13580), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20065PolyExtStep::Sub(13584, 13582), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20066PolyExtStep::Sub(13585, 13583), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20067PolyExtStep::Sub(13586, 13581), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20068PolyExtStep::AndEqz(6452, 13587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20069PolyExtStep::Mul(11140, 575), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20070PolyExtStep::Add(13588, 11330), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20071PolyExtStep::Add(13589, 11332), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20072PolyExtStep::Add(13590, 11334), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20073PolyExtStep::Add(13591, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20074PolyExtStep::Mul(11150, 588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20075PolyExtStep::Add(13588, 13593), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20076PolyExtStep::Mul(11160, 739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20077PolyExtStep::Add(13594, 13595), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20078PolyExtStep::Mul(11170, 740), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20079PolyExtStep::Add(13596, 13597), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20080PolyExtStep::Add(13598, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20081PolyExtStep::Mul(13592, 13599), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20082PolyExtStep::Mul(13592, 587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20083PolyExtStep::Mul(574, 13599), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20084PolyExtStep::Mul(13600, 12599), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20085PolyExtStep::Mul(13600, 741), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20086PolyExtStep::Mul(13602, 12599), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20087PolyExtStep::Mul(13601, 12599), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20088PolyExtStep::Mul(11364, 13603), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20089PolyExtStep::Sub(13607, 13605), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20090PolyExtStep::Sub(13608, 13606), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20091PolyExtStep::Sub(13609, 13604), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20092PolyExtStep::AndEqz(6453, 13610), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20093PolyExtStep::Mul(11408, 12617), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20094PolyExtStep::Sub(13611, 12619), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20095PolyExtStep::Sub(13612, 12620), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20096PolyExtStep::Sub(13613, 12618), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20097PolyExtStep::AndEqz(6454, 13614), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20098PolyExtStep::Mul(11504, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20099PolyExtStep::Add(13615, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20100PolyExtStep::Mul(12629, 13616), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20101PolyExtStep::Mul(12631, 13616), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20102PolyExtStep::Mul(12630, 13616), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20103PolyExtStep::Mul(11436, 13617), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20104PolyExtStep::Sub(13620, 13618), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20105PolyExtStep::Sub(13621, 13619), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20106PolyExtStep::Sub(13622, 12635), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20107PolyExtStep::AndEqz(6455, 13623), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20108PolyExtStep::Mul(11504, 772), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20109PolyExtStep::Add(13624, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20110PolyExtStep::Mul(11504, 757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20111PolyExtStep::Add(13626, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20112PolyExtStep::Mul(13625, 13627), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20113PolyExtStep::Mul(13625, 756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20114PolyExtStep::Mul(771, 13627), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20115PolyExtStep::Mul(11504, 781), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20116PolyExtStep::Add(13631, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20117PolyExtStep::Mul(13628, 13632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20118PolyExtStep::Mul(13628, 762), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20119PolyExtStep::Mul(13630, 13632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20120PolyExtStep::Mul(13629, 13632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20121PolyExtStep::Mul(11464, 13633), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20122PolyExtStep::Sub(13637, 13635), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20123PolyExtStep::Sub(13638, 13636), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20124PolyExtStep::Sub(13639, 13634), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20125PolyExtStep::AndEqz(6456, 13640), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20126PolyExtStep::Mul(11504, 737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20127PolyExtStep::Add(13641, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20128PolyExtStep::Mul(11504, 798), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20129PolyExtStep::Add(13643, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20130PolyExtStep::Mul(13642, 13644), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20131PolyExtStep::Mul(13642, 764), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20132PolyExtStep::Mul(732, 13644), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20133PolyExtStep::Mul(11504, 802), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20134PolyExtStep::Add(13648, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20135PolyExtStep::Mul(13645, 13649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20136PolyExtStep::Mul(13645, 800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20137PolyExtStep::Mul(13647, 13649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20138PolyExtStep::Mul(13646, 13649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20139PolyExtStep::Mul(11481, 13650), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20140PolyExtStep::Sub(13654, 13652), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20141PolyExtStep::Sub(13655, 13653), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20142PolyExtStep::Sub(13656, 13651), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20143PolyExtStep::AndEqz(6457, 13657), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20144PolyExtStep::Mul(11504, 814), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20145PolyExtStep::Add(13658, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20146PolyExtStep::Mul(11504, 820), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20147PolyExtStep::Add(13660, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20148PolyExtStep::Mul(13659, 13661), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20149PolyExtStep::Mul(13659, 817), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20150PolyExtStep::Mul(804, 13661), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20151PolyExtStep::Mul(11504, 826), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20152PolyExtStep::Add(13665, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20153PolyExtStep::Mul(13662, 13666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20154PolyExtStep::Mul(13662, 823), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20155PolyExtStep::Mul(13664, 13666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20156PolyExtStep::Mul(13663, 13666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20157PolyExtStep::Mul(11698, 13667), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20158PolyExtStep::Sub(13671, 13669), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20159PolyExtStep::Sub(13672, 13670), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20160PolyExtStep::Sub(13673, 13668), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20161PolyExtStep::AndEqz(6458, 13674), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20162PolyExtStep::Mul(11504, 832), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20163PolyExtStep::Add(13675, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20164PolyExtStep::Mul(11504, 838), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20165PolyExtStep::Add(13677, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20166PolyExtStep::Mul(13676, 13678), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20167PolyExtStep::Mul(13676, 835), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20168PolyExtStep::Mul(829, 13678), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20169PolyExtStep::Mul(11504, 844), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20170PolyExtStep::Add(13682, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20171PolyExtStep::Mul(13679, 13683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20172PolyExtStep::Mul(13679, 841), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20173PolyExtStep::Mul(13681, 13683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20174PolyExtStep::Mul(13680, 13683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20175PolyExtStep::Mul(11732, 13684), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20176PolyExtStep::Sub(13688, 13686), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20177PolyExtStep::Sub(13689, 13687), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20178PolyExtStep::Sub(13690, 13685), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20179PolyExtStep::AndEqz(6459, 13691), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20180PolyExtStep::Mul(11504, 850), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20181PolyExtStep::Add(13692, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20182PolyExtStep::Mul(11504, 856), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20183PolyExtStep::Add(13694, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20184PolyExtStep::Mul(13693, 13695), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20185PolyExtStep::Mul(13693, 853), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20186PolyExtStep::Mul(847, 13695), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20187PolyExtStep::Mul(11504, 893), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20188PolyExtStep::Add(13699, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20189PolyExtStep::Mul(13696, 13700), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20190PolyExtStep::Mul(13696, 859), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20191PolyExtStep::Mul(13698, 13700), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20192PolyExtStep::Mul(13697, 13700), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20193PolyExtStep::Mul(11765, 13701), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20194PolyExtStep::Sub(13705, 13703), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20195PolyExtStep::Sub(13706, 13704), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20196PolyExtStep::Sub(13707, 13702), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20197PolyExtStep::AndEqz(6460, 13708), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20198PolyExtStep::Mul(11130, 911), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20199PolyExtStep::Add(13709, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20200PolyExtStep::Mul(12727, 13710), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20201PolyExtStep::Mul(12729, 13710), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20202PolyExtStep::Mul(12728, 13710), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20203PolyExtStep::Mul(11782, 13711), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20204PolyExtStep::Sub(13714, 13712), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20205PolyExtStep::Sub(13715, 13713), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20206PolyExtStep::Sub(13716, 12733), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20207PolyExtStep::AndEqz(6461, 13717), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20208PolyExtStep::Mul(11130, 917), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20209PolyExtStep::Add(13718, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20210PolyExtStep::Mul(11130, 923), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20211PolyExtStep::Add(13720, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20212PolyExtStep::Mul(13719, 13721), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20213PolyExtStep::Mul(13719, 920), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20214PolyExtStep::Mul(914, 13721), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20215PolyExtStep::Mul(11130, 929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20216PolyExtStep::Add(13725, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20217PolyExtStep::Mul(13722, 13726), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20218PolyExtStep::Mul(13722, 926), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20219PolyExtStep::Mul(13724, 13726), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20220PolyExtStep::Mul(13723, 13726), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20221PolyExtStep::Mul(12020, 13727), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20222PolyExtStep::Sub(13731, 13729), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20223PolyExtStep::Sub(13732, 13730), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20224PolyExtStep::Sub(13733, 13728), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20225PolyExtStep::AndEqz(6462, 13734), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20226PolyExtStep::Sub(11493, 12019), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20227PolyExtStep::AndEqz(6463, 13735), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20228PolyExtStep::AndCond(6449, 458, 6464), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))
20229],
20230 ret: 6465,
20231};
20232
20233impl PolyExt<BabyBear> for CircuitImpl {
20234 fn poly_ext(
20235 &self,
20236 mix: &BabyBearExtElem,
20237 u: &[BabyBearExtElem],
20238 args: &[&[BabyBearElem]],
20239 ) -> MixState<BabyBearExtElem> {
20240 DEF.step::<BabyBear>(mix, u, args)
20241 }
20242}