risc0_circuit_rv32im/
trace.rs

1// Copyright 2025 RISC Zero, Inc.
2//
3// Licensed under the Apache License, Version 2.0 (the "License");
4// you may not use this file except in compliance with the License.
5// You may obtain a copy of the License at
6//
7//     http://www.apache.org/licenses/LICENSE-2.0
8//
9// Unless required by applicable law or agreed to in writing, software
10// distributed under the License is distributed on an "AS IS" BASIS,
11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12// See the License for the specific language governing permissions and
13// limitations under the License.
14
15extern crate alloc;
16
17use alloc::vec::Vec;
18
19use anyhow::Result;
20use derive_more::Debug;
21use serde::{Deserialize, Serialize};
22
23/// An event traced from the running VM.
24#[derive(Clone, Debug, Eq, Ord, PartialEq, PartialOrd, Serialize, Deserialize)]
25#[non_exhaustive]
26pub enum TraceEvent {
27    /// An instruction has started at the given program counter
28    InstructionStart {
29        /// Cycle number since startup
30        cycle: u64,
31
32        /// Program counter of the instruction being executed
33        #[debug("{pc:#010x}")]
34        pc: u32,
35
36        /// Encoded instruction being executed.
37        #[debug("{pc:#010x}")]
38        insn: u32,
39    },
40
41    /// A register has been set
42    RegisterSet {
43        /// Register ID (0-16)
44        idx: usize,
45
46        /// New value in the register
47        #[debug("{value:#010x}")]
48        value: u32,
49    },
50
51    /// A memory location has been written
52    MemorySet {
53        /// Address of memory that's been written
54        #[debug("{addr:#010x}")]
55        addr: u32,
56
57        /// Data that's been written
58        #[debug("{region:#04x?}")]
59        region: Vec<u8>,
60    },
61
62    /// A page is read for the first time in a segment
63    PageIn { cycles: u64 },
64
65    /// A page has been written to for the first time in a segment
66    PageOut { cycles: u64 },
67}
68
69/// A callback used to collect [TraceEvent]s.
70pub trait TraceCallback {
71    fn trace_callback(&mut self, event: TraceEvent) -> Result<()>;
72}
73
74impl<F: FnMut(TraceEvent) -> Result<()>> TraceCallback for F {
75    fn trace_callback(&mut self, event: TraceEvent) -> Result<()> {
76        self(event)
77    }
78}
risc0_circuit_rv32im/trace.rs

risc0_circuit_rv32im/
trace.rs
